Commit 9a302781 authored by Russell King's avatar Russell King Committed by Linus Walleij

gpio: omap: remove dataout variation in context handling

When a GPIO block has the set/clear dataout registers implemented, it
also has the normal dataout register implemented. Reading this register
reads the current GPIO output state, and writing it sets the GPIOs to
the explicit state. This is the behaviour that we want when saving and
restoring the context, so use the dataout register exclusively.
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Tested-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 31b2d7f7
...@@ -1087,11 +1087,7 @@ static void omap_gpio_init_context(struct gpio_bank *p) ...@@ -1087,11 +1087,7 @@ static void omap_gpio_init_context(struct gpio_bank *p)
p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
p->context.irqenable1 = readl_relaxed(base + regs->irqenable); p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
p->context.dataout = readl_relaxed(base + regs->dataout);
if (regs->set_dataout && p->regs->clr_dataout)
p->context.dataout = readl_relaxed(base + regs->set_dataout);
else
p->context.dataout = readl_relaxed(base + regs->dataout);
p->context_valid = true; p->context_valid = true;
} }
...@@ -1109,11 +1105,7 @@ static void omap_gpio_restore_context(struct gpio_bank *bank) ...@@ -1109,11 +1105,7 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
bank->base + bank->regs->risingdetect); bank->base + bank->regs->risingdetect);
writel_relaxed(bank->context.fallingdetect, writel_relaxed(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect); bank->base + bank->regs->fallingdetect);
if (bank->regs->set_dataout && bank->regs->clr_dataout) writel_relaxed(bank->context.dataout,
writel_relaxed(bank->context.dataout,
bank->base + bank->regs->set_dataout);
else
writel_relaxed(bank->context.dataout,
bank->base + bank->regs->dataout); bank->base + bank->regs->dataout);
writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
......
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