Commit 9c333719 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Decrease gen2 vco frequency minimum to 908 MHz

On my 855 machine the BIOS uses the following DPLL settings:
DPLL 0x90016000
FP0 = 0x61207
FP1 = 0x21207

With the 66MHz SSC refclock, that puts the BIOS generated VCO
frequency at ~908 MHz, which is lower than the 930 MHz limit
we have currently. This also results in the pixel clock coming
out significantly higher than the requested 65 MHz when we try
to recompute it.

Reduce the the VCO limit to 908 MHz. Combined with the earlier
SSC reference clock accuracy fix, this results in the pixel clock
coming out as 65.08 MHz which is quite close to the target. For
some reason the BIOS uses 64.881 MHz, which isn't quite as close.

This makes kms_flip wf_vblank-ts-check pass for the first time
on this machine \o/

Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: default avatarBruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e91e941b
...@@ -90,7 +90,7 @@ intel_fdi_link_freq(struct drm_device *dev) ...@@ -90,7 +90,7 @@ intel_fdi_link_freq(struct drm_device *dev)
static const intel_limit_t intel_limits_i8xx_dac = { static const intel_limit_t intel_limits_i8xx_dac = {
.dot = { .min = 25000, .max = 350000 }, .dot = { .min = 25000, .max = 350000 },
.vco = { .min = 930000, .max = 1512000 }, .vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 }, .n = { .min = 2, .max = 16 },
.m = { .min = 96, .max = 140 }, .m = { .min = 96, .max = 140 },
.m1 = { .min = 18, .max = 26 }, .m1 = { .min = 18, .max = 26 },
...@@ -103,7 +103,7 @@ static const intel_limit_t intel_limits_i8xx_dac = { ...@@ -103,7 +103,7 @@ static const intel_limit_t intel_limits_i8xx_dac = {
static const intel_limit_t intel_limits_i8xx_dvo = { static const intel_limit_t intel_limits_i8xx_dvo = {
.dot = { .min = 25000, .max = 350000 }, .dot = { .min = 25000, .max = 350000 },
.vco = { .min = 930000, .max = 1512000 }, .vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 }, .n = { .min = 2, .max = 16 },
.m = { .min = 96, .max = 140 }, .m = { .min = 96, .max = 140 },
.m1 = { .min = 18, .max = 26 }, .m1 = { .min = 18, .max = 26 },
...@@ -116,7 +116,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = { ...@@ -116,7 +116,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
static const intel_limit_t intel_limits_i8xx_lvds = { static const intel_limit_t intel_limits_i8xx_lvds = {
.dot = { .min = 25000, .max = 350000 }, .dot = { .min = 25000, .max = 350000 },
.vco = { .min = 930000, .max = 1512000 }, .vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 }, .n = { .min = 2, .max = 16 },
.m = { .min = 96, .max = 140 }, .m = { .min = 96, .max = 140 },
.m1 = { .min = 18, .max = 26 }, .m1 = { .min = 18, .max = 26 },
......
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