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Commit 9e6f3d02 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
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drm/radeon/kms: reorganize surface callbacks 

tidy up the radeon_asic struct.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 798bcf73
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Showing with 76 additions and 41 deletions
drivers/gpu/drm/radeon/radeon.h
View file @ 9e6f3d02
...@@ -1188,10 +1188,12 @@ struct radeon_asic { ...@@ -1188,10 +1188,12 @@ struct radeon_asic {
u32 copy_ring_index; u32 copy_ring_index;
} copy; } copy;
int (*set_surface_reg)(struct radeon_device *rdev, int reg, struct {
uint32_t tiling_flags, uint32_t pitch, int (*set_reg)(struct radeon_device *rdev, int reg,
uint32_t offset, uint32_t obj_size); uint32_t tiling_flags, uint32_t pitch,
void (*clear_surface_reg)(struct radeon_device *rdev, int reg); uint32_t offset, uint32_t obj_size);
void (*clear_reg)(struct radeon_device *rdev, int reg);
} surface;
struct { struct {
void (*init)(struct radeon_device *rdev); void (*init)(struct radeon_device *rdev);
...@@ -1707,8 +1709,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); ...@@ -1707,8 +1709,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
......
drivers/gpu/drm/radeon/radeon_asic.c
View file @ 9e6f3d02
...@@ -168,8 +168,10 @@ static struct radeon_asic r100_asic = { ...@@ -168,8 +168,10 @@ static struct radeon_asic r100_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r100_hpd_init, .init = &r100_hpd_init,
.fini = &r100_hpd_fini, .fini = &r100_hpd_fini,
...@@ -240,8 +242,10 @@ static struct radeon_asic r200_asic = { ...@@ -240,8 +242,10 @@ static struct radeon_asic r200_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r100_hpd_init, .init = &r100_hpd_init,
.fini = &r100_hpd_fini, .fini = &r100_hpd_fini,
...@@ -312,8 +316,10 @@ static struct radeon_asic r300_asic = { ...@@ -312,8 +316,10 @@ static struct radeon_asic r300_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r100_hpd_init, .init = &r100_hpd_init,
.fini = &r100_hpd_fini, .fini = &r100_hpd_fini,
...@@ -384,8 +390,10 @@ static struct radeon_asic r300_asic_pcie = { ...@@ -384,8 +390,10 @@ static struct radeon_asic r300_asic_pcie = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r100_hpd_init, .init = &r100_hpd_init,
.fini = &r100_hpd_fini, .fini = &r100_hpd_fini,
...@@ -456,9 +464,10 @@ static struct radeon_asic r420_asic = { ...@@ -456,9 +464,10 @@ static struct radeon_asic r420_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r100_hpd_init, .init = &r100_hpd_init,
.fini = &r100_hpd_fini, .fini = &r100_hpd_fini,
...@@ -529,8 +538,10 @@ static struct radeon_asic rs400_asic = { ...@@ -529,8 +538,10 @@ static struct radeon_asic rs400_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r100_hpd_init, .init = &r100_hpd_init,
.fini = &r100_hpd_fini, .fini = &r100_hpd_fini,
...@@ -601,8 +612,10 @@ static struct radeon_asic rs600_asic = { ...@@ -601,8 +612,10 @@ static struct radeon_asic rs600_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &rs600_hpd_init, .init = &rs600_hpd_init,
.fini = &rs600_hpd_fini, .fini = &rs600_hpd_fini,
...@@ -673,8 +686,10 @@ static struct radeon_asic rs690_asic = { ...@@ -673,8 +686,10 @@ static struct radeon_asic rs690_asic = {
.copy = &r200_copy_dma, .copy = &r200_copy_dma,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &rs600_hpd_init, .init = &rs600_hpd_init,
.fini = &rs600_hpd_fini, .fini = &rs600_hpd_fini,
...@@ -745,8 +760,10 @@ static struct radeon_asic rv515_asic = { ...@@ -745,8 +760,10 @@ static struct radeon_asic rv515_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &rs600_hpd_init, .init = &rs600_hpd_init,
.fini = &rs600_hpd_fini, .fini = &rs600_hpd_fini,
...@@ -817,8 +834,10 @@ static struct radeon_asic r520_asic = { ...@@ -817,8 +834,10 @@ static struct radeon_asic r520_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r100_set_surface_reg, .surface = {
.clear_surface_reg = r100_clear_surface_reg, .set_reg = r100_set_surface_reg,
.clear_reg = r100_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &rs600_hpd_init, .init = &rs600_hpd_init,
.fini = &rs600_hpd_fini, .fini = &rs600_hpd_fini,
...@@ -888,8 +907,10 @@ static struct radeon_asic r600_asic = { ...@@ -888,8 +907,10 @@ static struct radeon_asic r600_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r600_set_surface_reg, .surface = {
.clear_surface_reg = r600_clear_surface_reg, .set_reg = r600_set_surface_reg,
.clear_reg = r600_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r600_hpd_init, .init = &r600_hpd_init,
.fini = &r600_hpd_fini, .fini = &r600_hpd_fini,
...@@ -959,8 +980,10 @@ static struct radeon_asic rs780_asic = { ...@@ -959,8 +980,10 @@ static struct radeon_asic rs780_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r600_set_surface_reg, .surface = {
.clear_surface_reg = r600_clear_surface_reg, .set_reg = r600_set_surface_reg,
.clear_reg = r600_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r600_hpd_init, .init = &r600_hpd_init,
.fini = &r600_hpd_fini, .fini = &r600_hpd_fini,
...@@ -1030,8 +1053,10 @@ static struct radeon_asic rv770_asic = { ...@@ -1030,8 +1053,10 @@ static struct radeon_asic rv770_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r600_set_surface_reg, .surface = {
.clear_surface_reg = r600_clear_surface_reg, .set_reg = r600_set_surface_reg,
.clear_reg = r600_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &r600_hpd_init, .init = &r600_hpd_init,
.fini = &r600_hpd_fini, .fini = &r600_hpd_fini,
...@@ -1101,8 +1126,10 @@ static struct radeon_asic evergreen_asic = { ...@@ -1101,8 +1126,10 @@ static struct radeon_asic evergreen_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r600_set_surface_reg, .surface = {
.clear_surface_reg = r600_clear_surface_reg, .set_reg = r600_set_surface_reg,
.clear_reg = r600_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &evergreen_hpd_init, .init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini, .fini = &evergreen_hpd_fini,
...@@ -1172,8 +1199,10 @@ static struct radeon_asic sumo_asic = { ...@@ -1172,8 +1199,10 @@ static struct radeon_asic sumo_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r600_set_surface_reg, .surface = {
.clear_surface_reg = r600_clear_surface_reg, .set_reg = r600_set_surface_reg,
.clear_reg = r600_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &evergreen_hpd_init, .init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini, .fini = &evergreen_hpd_fini,
...@@ -1243,8 +1272,10 @@ static struct radeon_asic btc_asic = { ...@@ -1243,8 +1272,10 @@ static struct radeon_asic btc_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r600_set_surface_reg, .surface = {
.clear_surface_reg = r600_clear_surface_reg, .set_reg = r600_set_surface_reg,
.clear_reg = r600_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &evergreen_hpd_init, .init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini, .fini = &evergreen_hpd_fini,
...@@ -1343,8 +1374,10 @@ static struct radeon_asic cayman_asic = { ...@@ -1343,8 +1374,10 @@ static struct radeon_asic cayman_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.set_surface_reg = r600_set_surface_reg, .surface = {
.clear_surface_reg = r600_clear_surface_reg, .set_reg = r600_set_surface_reg,
.clear_reg = r600_clear_surface_reg,
},
.hpd = { .hpd = {
.init = &evergreen_hpd_init, .init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini, .fini = &evergreen_hpd_fini,
......
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