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nexedi
linux
Commits
b656eba1
Commit
b656eba1
authored
Apr 23, 2009
by
Bartlomiej Zolnierkiewicz
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Merge branch 'for-linus' into for-next
parents
24fc484a
b930f964
Changes
2
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2 changed files
with
25 additions
and
56 deletions
+25
-56
MAINTAINERS
MAINTAINERS
+1
-1
drivers/ide/palm_bk3710.c
drivers/ide/palm_bk3710.c
+24
-55
No files found.
MAINTAINERS
View file @
b656eba1
...
@@ -2743,7 +2743,7 @@ IDE SUBSYSTEM
...
@@ -2743,7 +2743,7 @@ IDE SUBSYSTEM
P: Bartlomiej Zolnierkiewicz
P: Bartlomiej Zolnierkiewicz
M: bzolnier@gmail.com
M: bzolnier@gmail.com
L: linux-ide@vger.kernel.org
L: linux-ide@vger.kernel.org
T:
quilt kernel.org/pub/linux/kernel/people/bart/pata-2.6/
T:
git git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6.git
S: Maintained
S: Maintained
F: Documentation/ide/
F: Documentation/ide/
F: drivers/ide/
F: drivers/ide/
...
...
drivers/ide/palm_bk3710.c
View file @
b656eba1
...
@@ -42,16 +42,9 @@
...
@@ -42,16 +42,9 @@
#define BK3710_BMICP 0x00
#define BK3710_BMICP 0x00
#define BK3710_BMISP 0x02
#define BK3710_BMISP 0x02
#define BK3710_BMIDTP 0x04
#define BK3710_BMIDTP 0x04
#define BK3710_BMICS 0x08
#define BK3710_BMISS 0x0A
#define BK3710_BMIDTS 0x0C
#define BK3710_IDETIMP 0x40
#define BK3710_IDETIMP 0x40
#define BK3710_IDETIMS 0x42
#define BK3710_SIDETIM 0x44
#define BK3710_SLEWCTL 0x45
#define BK3710_IDESTATUS 0x47
#define BK3710_IDESTATUS 0x47
#define BK3710_UDMACTL 0x48
#define BK3710_UDMACTL 0x48
#define BK3710_UDMATIM 0x4A
#define BK3710_MISCCTL 0x50
#define BK3710_MISCCTL 0x50
#define BK3710_REGSTB 0x54
#define BK3710_REGSTB 0x54
#define BK3710_REGRCVR 0x58
#define BK3710_REGRCVR 0x58
...
@@ -63,7 +56,6 @@
...
@@ -63,7 +56,6 @@
#define BK3710_UDMATRP 0x70
#define BK3710_UDMATRP 0x70
#define BK3710_UDMAENV 0x74
#define BK3710_UDMAENV 0x74
#define BK3710_IORDYTMP 0x78
#define BK3710_IORDYTMP 0x78
#define BK3710_IORDYTMS 0x7C
static
unsigned
ideclk_period
;
/* in nanoseconds */
static
unsigned
ideclk_period
;
/* in nanoseconds */
...
@@ -74,12 +66,12 @@ struct palm_bk3710_udmatiming {
...
@@ -74,12 +66,12 @@ struct palm_bk3710_udmatiming {
};
};
static
const
struct
palm_bk3710_udmatiming
palm_bk3710_udmatimings
[
6
]
=
{
static
const
struct
palm_bk3710_udmatiming
palm_bk3710_udmatimings
[
6
]
=
{
{
160
,
240
/
2
,
},
/* UDMA Mode 0 */
{
160
,
240
/
2
},
/* UDMA Mode 0 */
{
125
,
160
/
2
,
},
/* UDMA Mode 1 */
{
125
,
160
/
2
},
/* UDMA Mode 1 */
{
100
,
120
/
2
,
},
/* UDMA Mode 2 */
{
100
,
120
/
2
},
/* UDMA Mode 2 */
{
100
,
90
/
2
,},
/* UDMA Mode 3 */
{
100
,
90
/
2
},
/* UDMA Mode 3 */
{
100
,
60
/
2
,},
/* UDMA Mode 4 */
{
100
,
60
/
2
},
/* UDMA Mode 4 */
{
85
,
40
/
2
,},
/* UDMA Mode 5 */
{
85
,
40
/
2
},
/* UDMA Mode 5 */
};
};
static
void
palm_bk3710_setudmamode
(
void
__iomem
*
base
,
unsigned
int
dev
,
static
void
palm_bk3710_setudmamode
(
void
__iomem
*
base
,
unsigned
int
dev
,
...
@@ -96,11 +88,6 @@ static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
...
@@ -96,11 +88,6 @@ static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
trp
=
DIV_ROUND_UP
(
palm_bk3710_udmatimings
[
mode
].
rptime
,
trp
=
DIV_ROUND_UP
(
palm_bk3710_udmatimings
[
mode
].
rptime
,
ideclk_period
)
-
1
;
ideclk_period
)
-
1
;
/* udmatim Register */
val16
=
readw
(
base
+
BK3710_UDMATIM
)
&
(
dev
?
0xFF0F
:
0xFFF0
);
val16
|=
(
mode
<<
(
dev
?
4
:
0
));
writew
(
val16
,
base
+
BK3710_UDMATIM
);
/* udmastb Ultra DMA Access Strobe Width */
/* udmastb Ultra DMA Access Strobe Width */
val32
=
readl
(
base
+
BK3710_UDMASTB
)
&
(
0xFF
<<
(
dev
?
0
:
8
));
val32
=
readl
(
base
+
BK3710_UDMASTB
)
&
(
0xFF
<<
(
dev
?
0
:
8
));
val32
|=
(
t0
<<
(
dev
?
8
:
0
));
val32
|=
(
t0
<<
(
dev
?
8
:
0
));
...
@@ -161,10 +148,11 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
...
@@ -161,10 +148,11 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
u32
val32
;
u32
val32
;
struct
ide_timing
*
t
;
struct
ide_timing
*
t
;
t
=
ide_timing_find_mode
(
XFER_PIO_0
+
mode
);
/* PIO Data Setup */
/* PIO Data Setup */
t0
=
DIV_ROUND_UP
(
cycletime
,
ideclk_period
);
t0
=
DIV_ROUND_UP
(
cycletime
,
ideclk_period
);
t2
=
DIV_ROUND_UP
(
ide_timing_find_mode
(
XFER_PIO_0
+
mode
)
->
active
,
t2
=
DIV_ROUND_UP
(
t
->
active
,
ideclk_period
);
ideclk_period
);
t2i
=
t0
-
t2
-
1
;
t2i
=
t0
-
t2
-
1
;
t2
-=
1
;
t2
-=
1
;
...
@@ -185,7 +173,6 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
...
@@ -185,7 +173,6 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
}
}
/* TASKFILE Setup */
/* TASKFILE Setup */
t
=
ide_timing_find_mode
(
XFER_PIO_0
+
mode
);
t0
=
DIV_ROUND_UP
(
t
->
cyc8b
,
ideclk_period
);
t0
=
DIV_ROUND_UP
(
t
->
cyc8b
,
ideclk_period
);
t2
=
DIV_ROUND_UP
(
t
->
act8b
,
ideclk_period
);
t2
=
DIV_ROUND_UP
(
t
->
act8b
,
ideclk_period
);
...
@@ -234,42 +221,23 @@ static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
...
@@ -234,42 +221,23 @@ static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
static
void
__devinit
palm_bk3710_chipinit
(
void
__iomem
*
base
)
static
void
__devinit
palm_bk3710_chipinit
(
void
__iomem
*
base
)
{
{
/*
/*
* enable the reset_en of ATA controller so that when ata signals
* REVISIT: the ATA reset signal needs to be managed through a
* are brought out, by writing into device config. at that
* GPIO, which means it should come from platform_data. Until
* time por_n signal should not be 'Z' and have a stable value.
* we get and use such information, we have to trust that things
* have been reset before we get here.
*/
*/
writel
(
0x0300
,
base
+
BK3710_MISCCTL
);
/* wait for some time and deassert the reset of ATA Device. */
mdelay
(
100
);
/* Deassert the Reset */
writel
(
0x0200
,
base
+
BK3710_MISCCTL
);
/*
/*
* Program the IDETIMP Register Value based on the following assumptions
* Program the IDETIMP Register Value based on the following assumptions
*
*
* (ATA_IDETIMP_IDEEN , ENABLE ) |
* (ATA_IDETIMP_IDEEN , ENABLE ) |
* (ATA_IDETIMP_SLVTIMEN , DISABLE) |
* (ATA_IDETIMP_RDYSMPL , 70NS) |
* (ATA_IDETIMP_RDYRCVRY , 50NS) |
* (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) |
* (ATA_IDETIMP_PREPOST1 , DISABLE) |
* (ATA_IDETIMP_PREPOST1 , DISABLE) |
* (ATA_IDETIMP_RDYSEN1 , DISABLE) |
* (ATA_IDETIMP_PIOFTIM1 , DISABLE) |
* (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) |
* (ATA_IDETIMP_PREPOST0 , DISABLE) |
* (ATA_IDETIMP_PREPOST0 , DISABLE) |
* (ATA_IDETIMP_RDYSEN0 , DISABLE) |
*
* (ATA_IDETIMP_PIOFTIM0 , DISABLE)
* DM6446 silicon rev 2.1 and earlier have no observed net benefit
*/
* from enabling prefetch/postwrite.
writew
(
0xB388
,
base
+
BK3710_IDETIMP
);
/*
* Configure SIDETIM Register
* (ATA_SIDETIM_RDYSMPS1 ,120NS ) |
* (ATA_SIDETIM_RDYRCYS1 ,120NS )
*/
*/
write
b
(
0
,
base
+
BK3710_SIDETIM
);
write
w
(
BIT
(
15
),
base
+
BK3710_IDETIMP
);
/*
/*
* UDMACTL Ultra-ATA DMA Control
* UDMACTL Ultra-ATA DMA Control
...
@@ -281,11 +249,11 @@ static void __devinit palm_bk3710_chipinit(void __iomem *base)
...
@@ -281,11 +249,11 @@ static void __devinit palm_bk3710_chipinit(void __iomem *base)
/*
/*
* MISCCTL Miscellaneous Conrol Register
* MISCCTL Miscellaneous Conrol Register
* (ATA_MISCCTL_
RSTMODEP , 1) |
* (ATA_MISCCTL_
HWNHLD1P , 1 cycle)
* (ATA_MISCCTL_
RESETP , 0) |
* (ATA_MISCCTL_
HWNHLD0P , 1 cycle)
* (ATA_MISCCTL_TIMORIDE , 1)
* (ATA_MISCCTL_TIMORIDE , 1)
*/
*/
writel
(
0x
2
01
,
base
+
BK3710_MISCCTL
);
writel
(
0x
0
01
,
base
+
BK3710_MISCCTL
);
/*
/*
* IORDYTMP IORDY Timer for Primary Register
* IORDYTMP IORDY Timer for Primary Register
...
@@ -355,10 +323,9 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
...
@@ -355,10 +323,9 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
clk_enable
(
clk
);
clk_enable
(
clk
);
rate
=
clk_get_rate
(
clk
);
rate
=
clk_get_rate
(
clk
);
ideclk_period
=
1000000000UL
/
rate
;
/*
Register the IDE interface with Linux ATA Interface
*/
/*
NOTE: round *down* to meet minimum timings; we count in clocks
*/
memset
(
&
hw
,
0
,
sizeof
(
hw
))
;
ideclk_period
=
1000000000UL
/
rate
;
mem
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
mem
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
if
(
mem
==
NULL
)
{
if
(
mem
==
NULL
)
{
...
@@ -388,6 +355,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
...
@@ -388,6 +355,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
/* Configure the Palm Chip controller */
/* Configure the Palm Chip controller */
palm_bk3710_chipinit
(
base
);
palm_bk3710_chipinit
(
base
);
memset
(
&
hw
,
0
,
sizeof
(
hw
));
for
(
i
=
0
;
i
<
IDE_NR_PORTS
-
2
;
i
++
)
for
(
i
=
0
;
i
<
IDE_NR_PORTS
-
2
;
i
++
)
hw
.
io_ports_array
[
i
]
=
(
unsigned
long
)
hw
.
io_ports_array
[
i
]
=
(
unsigned
long
)
(
base
+
IDE_PALM_ATA_PRI_REG_OFFSET
+
i
);
(
base
+
IDE_PALM_ATA_PRI_REG_OFFSET
+
i
);
...
@@ -400,6 +368,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
...
@@ -400,6 +368,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
palm_bk3710_port_info
.
udma_mask
=
rate
<
100000000
?
ATA_UDMA4
:
palm_bk3710_port_info
.
udma_mask
=
rate
<
100000000
?
ATA_UDMA4
:
ATA_UDMA5
;
ATA_UDMA5
;
/* Register the IDE interface with Linux */
rc
=
ide_host_add
(
&
palm_bk3710_port_info
,
hws
,
NULL
);
rc
=
ide_host_add
(
&
palm_bk3710_port_info
,
hws
,
NULL
);
if
(
rc
)
if
(
rc
)
goto
out
;
goto
out
;
...
...
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