Commit b8be5663 authored by Matthias Brugger's avatar Matthias Brugger

ARM: mediatek: dts: Add uart to mt6592

This patch adds the uart ports and the uart clock to Mediateks
mt6592 SoC.
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 3aa2e281
...@@ -78,6 +78,12 @@ rtc_clk: dummy32k { ...@@ -78,6 +78,12 @@ rtc_clk: dummy32k {
#clock-cells = <0>; #clock-cells = <0>;
}; };
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
timer: timer@10008000 { timer: timer@10008000 {
compatible = "mediatek,mt6577-timer"; compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>; reg = <0x10008000 0x80>;
...@@ -102,4 +108,36 @@ gic: interrupt-controller@10211000 { ...@@ -102,4 +108,36 @@ gic: interrupt-controller@10211000 {
reg = <0x10211000 0x1000>, reg = <0x10211000 0x1000>,
<0x10212000 0x1000>; <0x10212000 0x1000>;
}; };
uart0: serial@11002000 {
compatible = "mediatek,mt6577-uart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6577-uart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6577-uart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt6577-uart";
reg = <0x11005000 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
}; };
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