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Commit ba66d7f0 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'omap/cleanup' into next/soc 

This is a dependency for the omap/soc branch
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 60c70c8c 3db53918
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Showing with 516 additions and 2382 deletions
arch/arm/mach-omap2/clkt_dpll.c
View file @ ba66d7f0
...@@ -21,10 +21,7 @@ ...@@ -21,10 +21,7 @@
#include <asm/div64.h> #include <asm/div64.h>
#include "soc.h"
#include "clock.h" #include "clock.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
/* DPLL rate rounding: minimum DPLL multiplier, divider values */ /* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER 2 #define DPLL_MIN_MULTIPLIER 2
...@@ -44,20 +41,12 @@ ...@@ -44,20 +41,12 @@
#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
/* /*
* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
* From device data manual section 4.3 "DPLL and DLL Specifications". * From device data manual section 4.3 "DPLL and DLL Specifications".
*/ */
#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
#define OMAP3PLUS_DPLL_FINT_MIN 32000
#define OMAP3PLUS_DPLL_FINT_MAX 52000000
/* _dpll_test_fint() return codes */ /* _dpll_test_fint() return codes */
#define DPLL_FINT_UNDERFLOW -1 #define DPLL_FINT_UNDERFLOW -1
...@@ -87,33 +76,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) ...@@ -87,33 +76,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
/* DPLL divider must result in a valid jitter correction val */ /* DPLL divider must result in a valid jitter correction val */
fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
if (cpu_is_omap24xx()) { if (dd->flags & DPLL_J_TYPE) {
/* Should not be called for OMAP2, so warn if it is called */
WARN(1, "No fint limits available for OMAP2!\n");
return DPLL_FINT_INVALID;
} else if (cpu_is_omap3430()) {
fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
} else if (dd->flags & DPLL_J_TYPE) {
fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
} else { } else {
fint_min = OMAP3PLUS_DPLL_FINT_MIN; fint_min = ti_clk_features.fint_min;
fint_max = OMAP3PLUS_DPLL_FINT_MAX; fint_max = ti_clk_features.fint_max;
} }
if (fint < fint_min) { if (!fint_min || !fint_max) {
WARN(1, "No fint limits available!\n");
return DPLL_FINT_INVALID;
}
if (fint < ti_clk_features.fint_min) {
pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
n); n);
dd->max_divider = n; dd->max_divider = n;
ret = DPLL_FINT_UNDERFLOW; ret = DPLL_FINT_UNDERFLOW;
} else if (fint > fint_max) { } else if (fint > ti_clk_features.fint_max) {
pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
n); n);
dd->min_divider = n; dd->min_divider = n;
ret = DPLL_FINT_INVALID; ret = DPLL_FINT_INVALID;
} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && } else if (fint > ti_clk_features.fint_band1_max &&
fint < OMAP3430_DPLL_FINT_BAND2_MIN) { fint < ti_clk_features.fint_band2_min) {
pr_debug("rejecting n=%d due to Fint failure\n", n); pr_debug("rejecting n=%d due to Fint failure\n", n);
ret = DPLL_FINT_INVALID; ret = DPLL_FINT_INVALID;
} }
...@@ -185,6 +172,34 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, ...@@ -185,6 +172,34 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
return r; return r;
} }
/**
* _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
* @v: bitfield value of the DPLL enable
*
* Checks given DPLL enable bitfield to see whether the DPLL is in bypass
* mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
*/
static int _omap2_dpll_is_in_bypass(u32 v)
{
u8 mask, val;
mask = ti_clk_features.dpll_bypass_vals;
/*
* Each set bit in the mask corresponds to a bypass value equal
* to the bitshift. Go through each set-bit in the mask and
* compare against the given register value.
*/
while (mask) {
val = __ffs(mask);
mask ^= (1 << val);
if (v == val)
return 1;
}
return 0;
}
/* Public functions */ /* Public functions */
u8 omap2_init_dpll_parent(struct clk_hw *hw) u8 omap2_init_dpll_parent(struct clk_hw *hw)
{ {
...@@ -201,20 +216,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) ...@@ -201,20 +216,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
v >>= __ffs(dd->enable_mask); v >>= __ffs(dd->enable_mask);
/* Reparent the struct clk in case the dpll is in bypass */ /* Reparent the struct clk in case the dpll is in bypass */
if (cpu_is_omap24xx()) { if (_omap2_dpll_is_in_bypass(v))
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
return 1;
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return 1; return 1;
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
return 1;
}
return 0; return 0;
} }
...@@ -247,20 +251,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) ...@@ -247,20 +251,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
v &= dd->enable_mask; v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask); v >>= __ffs(dd->enable_mask);
if (cpu_is_omap24xx()) { if (_omap2_dpll_is_in_bypass(v))
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
return __clk_get_rate(dd->clk_bypass); return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return __clk_get_rate(dd->clk_bypass);
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
return __clk_get_rate(dd->clk_bypass);
}
v = omap2_clk_readl(clk, dd->mult_div1_reg); v = omap2_clk_readl(clk, dd->mult_div1_reg);
dpll_mult = v & dd->mult_mask; dpll_mult = v & dd->mult_mask;
......
arch/arm/mach-omap2/clkt_iclk.c
View file @ ba66d7f0
...@@ -14,11 +14,11 @@ ...@@ -14,11 +14,11 @@
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/io.h> #include <linux/io.h>
#include "clock.h" #include "clock.h"
#include "clock2xxx.h"
#include "cm2xxx_3xxx.h" /* Register offsets */
#include "cm-regbits-24xx.h" #define CM_AUTOIDLE 0x30
#define CM_ICLKEN 0x10
/* Private functions */ /* Private functions */
......
arch/arm/mach-omap2/clock.c
View file @ ba66d7f0
...@@ -46,6 +46,24 @@ ...@@ -46,6 +46,24 @@
u16 cpu_mask; u16 cpu_mask;
/*
* Clock features setup. Used instead of CPU type checks.
*/
struct ti_clk_features ti_clk_features;
/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
/*
* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
* From device data manual section 4.3 "DPLL and DLL Specifications".
*/
#define OMAP3PLUS_DPLL_FINT_MIN 32000
#define OMAP3PLUS_DPLL_FINT_MAX 52000000
/* /*
* clkdm_control: if true, then when a clock is enabled in the * clkdm_control: if true, then when a clock is enabled in the
* hardware, its clockdomain will first be enabled; and when a clock * hardware, its clockdomain will first be enabled; and when a clock
...@@ -287,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, ...@@ -287,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
* 34xx reverses this, just to keep us on our toes * 34xx reverses this, just to keep us on our toes
* AM35xx uses both, depending on the module. * AM35xx uses both, depending on the module.
*/ */
if (cpu_is_omap24xx()) *idlest_val = ti_clk_features.cm_idlest_val;
*idlest_val = OMAP24XX_CM_IDLEST_VAL;
else if (cpu_is_omap34xx())
*idlest_val = OMAP34XX_CM_IDLEST_VAL;
else
BUG();
} }
/** /**
...@@ -731,3 +743,53 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, ...@@ -731,3 +743,53 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
(clk_get_rate(core_ck) / 1000000), (clk_get_rate(core_ck) / 1000000),
(clk_get_rate(mpu_ck) / 1000000)); (clk_get_rate(mpu_ck) / 1000000));
} }
/**
* ti_clk_init_features - init clock features struct for the SoC
*
* Initializes the clock features struct based on the SoC type.
*/
void __init ti_clk_init_features(void)
{
/* Fint setup for DPLLs */
if (cpu_is_omap3430()) {
ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
} else {
ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
}
/* Bypass value setup for DPLLs */
if (cpu_is_omap24xx()) {
ti_clk_features.dpll_bypass_vals |=
(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
} else if (cpu_is_omap34xx()) {
ti_clk_features.dpll_bypass_vals |=
(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
soc_is_omap54xx() || soc_is_dra7xx()) {
ti_clk_features.dpll_bypass_vals |=
(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
}
/* Jitter correction only available on OMAP343X */
if (cpu_is_omap343x())
ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
/* Idlest value for interface clocks.
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
* 34xx reverses this, just to keep us on our toes
* AM35xx uses both, depending on the module.
*/
if (cpu_is_omap24xx())
ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
else if (cpu_is_omap34xx())
ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
arch/arm/mach-omap2/clock.h
View file @ ba66d7f0
...@@ -101,31 +101,6 @@ struct clockdomain; ...@@ -101,31 +101,6 @@ struct clockdomain;
}; \ }; \
DEFINE_STRUCT_CLK(_name, _parent_names, _ops); DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
_parent_ptr, _flags, \
_clksel_reg, _clksel_mask) \
static const struct clksel _name##_div[] = { \
{ \
.parent = _parent_ptr, \
.rates = div31_1to31_rates \
}, \
{ .parent = NULL }, \
}; \
static struct clk _name; \
static const char *_name##_parent_names[] = { \
_parent_name, \
}; \
static struct clk_hw_omap _name##_hw = { \
.hw = { \
.clk = &_name, \
}, \
.clksel = _name##_div, \
.clksel_reg = _clksel_reg, \
.clksel_mask = _clksel_mask, \
.ops = &clkhwops_omap4_dpllmx, \
}; \
DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
/* struct clksel_rate.flags possibilities */ /* struct clksel_rate.flags possibilities */
#define RATE_IN_242X (1 << 0) #define RATE_IN_242X (1 << 0)
#define RATE_IN_243X (1 << 1) #define RATE_IN_243X (1 << 1)
...@@ -248,6 +223,23 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); ...@@ -248,6 +223,23 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
extern u16 cpu_mask; extern u16 cpu_mask;
/*
* Clock features setup. Used instead of CPU type checks.
*/
struct ti_clk_features {
u32 flags;
long fint_min;
long fint_max;
long fint_band1_max;
long fint_band2_min;
u8 dpll_bypass_vals;
u8 cm_idlest_val;
};
#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
extern struct ti_clk_features ti_clk_features;
extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy; extern const struct clkops clkops_dummy;
extern const struct clkops clkops_omap2_dflt; extern const struct clkops clkops_omap2_dflt;
...@@ -286,4 +278,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); ...@@ -286,4 +278,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
extern void omap_clocks_register(struct omap_clk *oclks, int cnt); extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
void __init ti_clk_init_features(void);
#endif #endif
arch/arm/mach-omap2/control.c
View file @ ba66d7f0
...@@ -44,8 +44,7 @@ struct omap3_scratchpad { ...@@ -44,8 +44,7 @@ struct omap3_scratchpad {
}; };
struct omap3_scratchpad_prcm_block { struct omap3_scratchpad_prcm_block {
u32 prm_clksrc_ctrl; u32 prm_contents[2];
u32 prm_clksel;
u32 cm_contents[11]; u32 cm_contents[11];
u32 prcm_block_size; u32 prcm_block_size;
}; };
...@@ -282,13 +281,9 @@ void omap3_clear_scratchpad_contents(void) ...@@ -282,13 +281,9 @@ void omap3_clear_scratchpad_contents(void)
void __iomem *v_addr; void __iomem *v_addr;
u32 offset = 0; u32 offset = 0;
v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & if (omap3xxx_prm_clear_global_cold_reset()) {
OMAP3430_GLOBAL_COLD_RST_MASK) {
for ( ; offset <= max_offset; offset += 0x4) for ( ; offset <= max_offset; offset += 0x4)
writel_relaxed(0x0, (v_addr + offset)); writel_relaxed(0x0, (v_addr + offset));
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
OMAP3430_GR_MOD,
OMAP3_PRM_RSTST_OFFSET);
} }
} }
...@@ -331,13 +326,7 @@ void omap3_save_scratchpad_contents(void) ...@@ -331,13 +326,7 @@ void omap3_save_scratchpad_contents(void)
scratchpad_contents.sdrc_block_offset = 0x64; scratchpad_contents.sdrc_block_offset = 0x64;
/* Populate the PRCM block contents */ /* Populate the PRCM block contents */
prcm_block_contents.prm_clksrc_ctrl = omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
prcm_block_contents.prm_clksel =
omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
OMAP3_PRM_CLKSEL_OFFSET);
omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
prcm_block_contents.prcm_block_size = 0x0; prcm_block_contents.prcm_block_size = 0x0;
...@@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void) ...@@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void)
* Sets the bootmode for IVA2 to idle. This is needed by the PM code to * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
* force disable IVA2 so that it does not prevent any low-power states. * force disable IVA2 so that it does not prevent any low-power states.
*/ */
void omap3_ctrl_set_iva_bootmode_idle(void) static void __init omap3_ctrl_set_iva_bootmode_idle(void)
{ {
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
OMAP343X_CONTROL_IVA2_BOOTMOD); OMAP343X_CONTROL_IVA2_BOOTMOD);
} }
/**
* omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
*
* Sets up the pads controlling the stacked modem in such way that the
* device can enter idle.
*/
static void __init omap3_ctrl_setup_d2d_padconf(void)
{
u16 mask, padconf;
/*
* In a stand alone OMAP3430 where there is not a stacked
* modem for the D2D Idle Ack and D2D MStandby must be pulled
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
*/
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
padconf |= mask;
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
padconf |= mask;
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
}
/**
* omap3_ctrl_init - does static initializations for control module
*
* Initializes system control module. This sets up the sysconfig autoidle,
* and sets up modem and iva2 so that they can be idled properly.
*/
void __init omap3_ctrl_init(void)
{
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
omap3_ctrl_set_iva_bootmode_idle();
omap3_ctrl_setup_d2d_padconf();
}
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
arch/arm/mach-omap2/control.h
View file @ ba66d7f0
...@@ -16,11 +16,6 @@ ...@@ -16,11 +16,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
#define __ARCH_ARM_MACH_OMAP2_CONTROL_H #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
#include "ctrl_module_core_44xx.h"
#include "ctrl_module_wkup_44xx.h"
#include "ctrl_module_pad_core_44xx.h"
#include "ctrl_module_pad_wkup_44xx.h"
#include "am33xx.h" #include "am33xx.h"
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
...@@ -254,6 +249,39 @@ ...@@ -254,6 +249,39 @@
/* TI81XX CONTROL_DEVCONF register offsets */ /* TI81XX CONTROL_DEVCONF register offsets */
#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
/* OMAP4 CONTROL MODULE */
#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
/* OMAP4 CONTROL_DSIPHY */
#define OMAP4_DSI2_LANEENABLE_SHIFT 29
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_DSI1_PIPD_SHIFT 19
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
#define OMAP4_DSI2_PIPD_SHIFT 14
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
/* OMAP4 CONTROL_CAMERA_RX */
#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
/* OMAP54XX CONTROL STATUS register */ /* OMAP54XX CONTROL STATUS register */
#define OMAP5XXX_CONTROL_STATUS 0x134 #define OMAP5XXX_CONTROL_STATUS 0x134
#define OMAP5_DEVICETYPE_MASK (0x7 << 6) #define OMAP5_DEVICETYPE_MASK (0x7 << 6)
...@@ -427,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); ...@@ -427,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void); extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void); extern int omap3_ctrl_save_padconf(void);
extern void omap3_ctrl_set_iva_bootmode_idle(void); void omap3_ctrl_init(void);
extern void omap2_set_globals_control(void __iomem *ctrl, extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad); void __iomem *ctrl_pad);
#else #else
......
arch/arm/mach-omap2/ctrl_module_core_44xx.h deleted 100644 → 0
View file @ 60c70c8c
/*
* OMAP44xx CTRL_MODULE_CORE registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
* Santosh Shilimkar (santosh.shilimkar@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
/* Base address */
#define OMAP4_CTRL_MODULE_CORE 0x4a002000
/* Registers offset */
#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
/* Registers shifts and masks */
/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT 30
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT 16
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT 11
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT 8
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT 0
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT 0
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
/* STD_FUSE_DIE_ID_0 */
#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
/* ID_CODE */
#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
/* STD_FUSE_DIE_ID_1 */
#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
/* STD_FUSE_DIE_ID_2 */
#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
/* STD_FUSE_DIE_ID_3 */
#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
/* STD_FUSE_PROD_ID_0 */
#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
/* STD_FUSE_PROD_ID_1 */
#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
/* STD_FUSE_USB_CONF */
#define OMAP4_USB_PROD_ID_SHIFT 16
#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
#define OMAP4_USB_VENDOR_ID_SHIFT 0
#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
/* STD_FUSE_OPP_VDD_WKUP */
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
/* STD_FUSE_OPP_BGAP */
#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
/* STD_FUSE_OPP_DPLL_0 */
#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
/* STD_FUSE_OPP_DPLL_1 */
#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
/* STATUS */
#define OMAP4_ATTILA_CONF_SHIFT 11
#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
#define OMAP4_DEVICE_TYPE_SHIFT 8
#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
#define OMAP4_SYS_BOOT_SHIFT 0
#define OMAP4_SYS_BOOT_MASK (0xff << 0)
/* DEV_CONF */
#define OMAP4_DEV_CONF_SHIFT 1
#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
#define OMAP4_USBPHY_PD_SHIFT 0
#define OMAP4_USBPHY_PD_MASK (1 << 0)
/* LDOVBB_IVA_VOLTAGE_CTRL */
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
/* LDOVBB_MPU_VOLTAGE_CTRL */
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
/* LDOSRAM_IVA_VOLTAGE_CTRL */
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
/* LDOSRAM_MPU_VOLTAGE_CTRL */
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
/* LDOSRAM_CORE_VOLTAGE_CTRL */
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
/* TEMP_SENSOR */
#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
#define OMAP4_BGAP_TSHUT_SHIFT 11
#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
/* DPLL_NWELL_TRIM_0 */
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
/* DPLL_NWELL_TRIM_1 */
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
/* USBOTGHS_CONTROL */
#define OMAP4_DISCHRGVBUS_SHIFT 8
#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
#define OMAP4_CHRGVBUS_SHIFT 7
#define OMAP4_CHRGVBUS_MASK (1 << 7)
#define OMAP4_DRVVBUS_SHIFT 6
#define OMAP4_DRVVBUS_MASK (1 << 6)
#define OMAP4_IDPULLUP_SHIFT 5
#define OMAP4_IDPULLUP_MASK (1 << 5)
#define OMAP4_IDDIG_SHIFT 4
#define OMAP4_IDDIG_MASK (1 << 4)
#define OMAP4_SESSEND_SHIFT 3
#define OMAP4_SESSEND_MASK (1 << 3)
#define OMAP4_VBUSVALID_SHIFT 2
#define OMAP4_VBUSVALID_MASK (1 << 2)
#define OMAP4_BVALID_SHIFT 1
#define OMAP4_BVALID_MASK (1 << 1)
#define OMAP4_AVALID_SHIFT 0
#define OMAP4_AVALID_MASK (1 << 0)
/* DSS_CONTROL */
#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
/* HWOBS_CONTROL */
#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
/* DEBOBS_FINAL_MUX_SEL */
#define OMAP4_SELECT_SHIFT 0
#define OMAP4_SELECT_MASK (0xffffffff << 0)
/* DEBOBS_MMR_MPU */
#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
/* CONF_SDMA_REQ_SEL0 */
#define OMAP4_MULT_SHIFT 0
#define OMAP4_MULT_MASK (0x7f << 0)
/* CONF_CLK_SEL0 */
#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
/* CONF_CLK_SEL1 */
#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
/* CONF_CLK_SEL2 */
#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
/* CONF_DPLL_FREQLOCK_SEL */
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
/* CONF_DPLL_TINITZ_SEL */
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
/* CONF_DPLL_PHASELOCK_SEL */
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
/* CONF_DEBUG_SEL_TST_0 */
#define OMAP4_MODE_SHIFT 0
#define OMAP4_MODE_MASK (0xf << 0)
#endif
arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h deleted 100644 → 0
View file @ 60c70c8c
/*
* OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
* Santosh Shilimkar (santosh.shilimkar@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
/* Base address */
#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
/* Registers offset */
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
/* Registers shifts and masks */
/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT 30
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT 16
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT 11
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT 8
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT 0
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT 0
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
/* PADCONF_WAKEUPEVENT_0 */
#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_1 */
#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_2 */
#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_3 */
#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_4 */
#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_5 */
#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_6 */
#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* CONTROL_PADCONF_GLOBAL */
#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
/* CONTROL_PADCONF_MODE */
#define OMAP4_VDDS_DV_BANK0_SHIFT 31
#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
#define OMAP4_VDDS_DV_BANK1_SHIFT 30
#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
#define OMAP4_VDDS_DV_BANK3_SHIFT 29
#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
#define OMAP4_VDDS_DV_BANK4_SHIFT 28
#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
#define OMAP4_VDDS_DV_BANK5_SHIFT 27
#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
#define OMAP4_VDDS_DV_BANK6_SHIFT 26
#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
#define OMAP4_VDDS_DV_C2C_SHIFT 25
#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
#define OMAP4_VDDS_DV_CAM_SHIFT 24
#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
#define OMAP4_VDDS_DV_GPMC_SHIFT 23
#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
/* CONTROL_SMART1IO_PADCONF_0 */
#define OMAP4_ABE_DR0_SC_SHIFT 30
#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
#define OMAP4_CAM_DR0_SC_SHIFT 28
#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
#define OMAP4_FREF_DR2_SC_SHIFT 26
#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
#define OMAP4_FREF_DR3_SC_SHIFT 24
#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
#define OMAP4_GPIO_DR8_SC_SHIFT 22
#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
#define OMAP4_GPIO_DR9_SC_SHIFT 20
#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
#define OMAP4_GPMC_DR2_SC_SHIFT 18
#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
#define OMAP4_GPMC_DR3_SC_SHIFT 16
#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
#define OMAP4_GPMC_DR6_SC_SHIFT 14
#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
#define OMAP4_HDMI_DR0_SC_SHIFT 12
#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
#define OMAP4_UART1_DR0_SC_SHIFT 8
#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
#define OMAP4_UART3_DR0_SC_SHIFT 6
#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
#define OMAP4_UART3_DR1_SC_SHIFT 4
#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
/* CONTROL_SMART1IO_PADCONF_1 */
#define OMAP4_ABE_DR0_LB_SHIFT 30
#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
#define OMAP4_CAM_DR0_LB_SHIFT 28
#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
#define OMAP4_FREF_DR2_LB_SHIFT 26
#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
#define OMAP4_FREF_DR3_LB_SHIFT 24
#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
#define OMAP4_GPIO_DR8_LB_SHIFT 22
#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
#define OMAP4_GPIO_DR9_LB_SHIFT 20
#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
#define OMAP4_GPMC_DR2_LB_SHIFT 18
#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
#define OMAP4_GPMC_DR3_LB_SHIFT 16
#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
#define OMAP4_GPMC_DR6_LB_SHIFT 14
#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
#define OMAP4_HDMI_DR0_LB_SHIFT 12
#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
#define OMAP4_UART1_DR0_LB_SHIFT 8
#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
#define OMAP4_UART3_DR0_LB_SHIFT 6
#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
#define OMAP4_UART3_DR1_LB_SHIFT 4
#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
/* CONTROL_SMART2IO_PADCONF_0 */
#define OMAP4_C2C_DR0_LB_SHIFT 31
#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
#define OMAP4_DPM_DR1_LB_SHIFT 30
#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
#define OMAP4_DPM_DR2_LB_SHIFT 29
#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
#define OMAP4_DPM_DR3_LB_SHIFT 28
#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
#define OMAP4_GPIO_DR0_LB_SHIFT 27
#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
#define OMAP4_GPIO_DR1_LB_SHIFT 26
#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
#define OMAP4_GPIO_DR10_LB_SHIFT 25
#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
#define OMAP4_GPIO_DR2_LB_SHIFT 24
#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
#define OMAP4_GPMC_DR0_LB_SHIFT 23
#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
#define OMAP4_GPMC_DR1_LB_SHIFT 22
#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
#define OMAP4_GPMC_DR4_LB_SHIFT 21
#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
#define OMAP4_GPMC_DR5_LB_SHIFT 20
#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
#define OMAP4_GPMC_DR7_LB_SHIFT 19
#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
#define OMAP4_HSI2_DR0_LB_SHIFT 18
#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
#define OMAP4_HSI2_DR1_LB_SHIFT 17
#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
#define OMAP4_HSI2_DR2_LB_SHIFT 16
#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
#define OMAP4_KPD_DR0_LB_SHIFT 15
#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
#define OMAP4_KPD_DR1_LB_SHIFT 14
#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
#define OMAP4_PDM_DR0_LB_SHIFT 13
#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
#define OMAP4_SPI3_DR0_LB_SHIFT 8
#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
#define OMAP4_SPI3_DR1_LB_SHIFT 7
#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
#define OMAP4_UART3_DR2_LB_SHIFT 6
#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
#define OMAP4_UART3_DR3_LB_SHIFT 5
#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
#define OMAP4_UART3_DR4_LB_SHIFT 4
#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
#define OMAP4_UART3_DR5_LB_SHIFT 3
#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
#define OMAP4_USBA0_DR1_LB_SHIFT 2
#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
#define OMAP4_USBA_DR2_LB_SHIFT 1
#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
/* CONTROL_SMART2IO_PADCONF_1 */
#define OMAP4_USBB1_DR0_LB_SHIFT 31
#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
#define OMAP4_USBB2_DR0_LB_SHIFT 30
#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
#define OMAP4_USBA0_DR0_LB_SHIFT 29
#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
/* CONTROL_SMART3IO_PADCONF_0 */
#define OMAP4_DMIC_DR0_MB_SHIFT 30
#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
#define OMAP4_GPIO_DR3_MB_SHIFT 28
#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
#define OMAP4_GPIO_DR4_MB_SHIFT 26
#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
#define OMAP4_GPIO_DR5_MB_SHIFT 24
#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
#define OMAP4_GPIO_DR6_MB_SHIFT 22
#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
#define OMAP4_HSI_DR1_MB_SHIFT 20
#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
#define OMAP4_HSI_DR2_MB_SHIFT 18
#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
#define OMAP4_HSI_DR3_MB_SHIFT 16
#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
#define OMAP4_SPI2_DR0_MB_SHIFT 0
#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
/* CONTROL_SMART3IO_PADCONF_1 */
#define OMAP4_SPI2_DR1_MB_SHIFT 30
#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
#define OMAP4_SPI2_DR2_MB_SHIFT 28
#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
#define OMAP4_UART2_DR0_MB_SHIFT 26
#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
#define OMAP4_UART2_DR1_MB_SHIFT 24
#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
#define OMAP4_UART4_DR0_MB_SHIFT 22
#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
#define OMAP4_HSI_DR0_MB_SHIFT 20
#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
/* CONTROL_SMART3IO_PADCONF_2 */
#define OMAP4_DMIC_DR0_LB_SHIFT 31
#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
#define OMAP4_GPIO_DR3_LB_SHIFT 30
#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
#define OMAP4_GPIO_DR4_LB_SHIFT 29
#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
#define OMAP4_GPIO_DR5_LB_SHIFT 28
#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
#define OMAP4_GPIO_DR6_LB_SHIFT 27
#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
#define OMAP4_HSI_DR1_LB_SHIFT 26
#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
#define OMAP4_HSI_DR2_LB_SHIFT 25
#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
#define OMAP4_HSI_DR3_LB_SHIFT 24
#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
#define OMAP4_SPI2_DR0_LB_SHIFT 16
#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
#define OMAP4_SPI2_DR1_LB_SHIFT 15
#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
#define OMAP4_SPI2_DR2_LB_SHIFT 14
#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
#define OMAP4_UART2_DR0_LB_SHIFT 13
#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
#define OMAP4_UART2_DR1_LB_SHIFT 12
#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
#define OMAP4_UART4_DR0_LB_SHIFT 11
#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
#define OMAP4_HSI_DR0_LB_SHIFT 10
#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
/* CONTROL_USBB_HSIC */
#define OMAP4_USBB2_DR1_SR_SHIFT 30
#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
#define OMAP4_USBB2_DR1_I_SHIFT 27
#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
#define OMAP4_USBB1_DR1_SR_SHIFT 25
#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
#define OMAP4_USBB1_DR1_I_SHIFT 22
#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
/* CONTROL_SLIMBUS */
#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
/* CONTROL_PBIASLITE */
#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
#define OMAP4_MMC1_PWRDNZ_SHIFT 26
#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
/* CONTROL_I2C_0 */
#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
/* CONTROL_CAMERA_RX */
#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
/* CONTROL_AVDAC */
#define OMAP4_AVDAC_ACEN_SHIFT 31
#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
#define OMAP4_AVDAC_INPUTINV_SHIFT 29
#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
#define OMAP4_AVDAC_CTL_SHIFT 13
#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
/* CONTROL_HDMI_TX_PHY */
#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
/* CONTROL_MMC2 */
#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
/* CONTROL_DSIPHY */
#define OMAP4_DSI2_LANEENABLE_SHIFT 29
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_DSI1_PIPD_SHIFT 19
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
#define OMAP4_DSI2_PIPD_SHIFT 14
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
/* CONTROL_MCBSPLP */
#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
/* CONTROL_USB2PHYCORE */
#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
#define OMAP4_USB2PHY_DATADET_SHIFT 18
#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
/* CONTROL_I2C_1 */
#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
/* CONTROL_MMC1 */
#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
#define OMAP4_USB_FD_CDEN_SHIFT 23
#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
/* CONTROL_HSI */
#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
/* CONTROL_USB */
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
/* CONTROL_HDQ */
#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
/* CONTROL_LPDDR2IO1_0 */
#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO1_1 */
#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO1_2 */
#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
/* CONTROL_LPDDR2IO1_3 */
#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
/* CONTROL_LPDDR2IO2_0 */
#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO2_1 */
#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO2_2 */
#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
/* CONTROL_LPDDR2IO2_3 */
#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
/* CONTROL_BUS_HOLD */
#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
/* CONTROL_C2C */
#define OMAP4_MIRROR_MODE_EN_SHIFT 31
#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
#define OMAP4_C2C_SPARE_SHIFT 24
#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
/* CORE_CONTROL_SPARE_RW */
#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
/* CORE_CONTROL_SPARE_R */
#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
/* CORE_CONTROL_SPARE_R_C0 */
#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
/* CONTROL_EFUSE_1 */
#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
/* CONTROL_EFUSE_2 */
#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
/* CONTROL_EFUSE_3 */
#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
/* CONTROL_EFUSE_4 */
#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
#endif
arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h deleted 100644 → 0
View file @ 60c70c8c
/*
* OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
* Santosh Shilimkar (santosh.shilimkar@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
/* Base address */
#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
/* Registers offset */
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
/* Registers shifts and masks */
/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT 30
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT 16
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT 11
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT 8
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT 0
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT 0
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
/* PADCONF_WAKEUPEVENT_0 */
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* CONTROL_SMART1NOPMIO_PADCONF_0 */
#define OMAP4_FREF_DR0_SC_SHIFT 30
#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
#define OMAP4_FREF_DR1_SC_SHIFT 28
#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
#define OMAP4_FREF_DR4_SC_SHIFT 26
#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
#define OMAP4_FREF_DR5_SC_SHIFT 24
#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
#define OMAP4_FREF_DR6_SC_SHIFT 22
#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
#define OMAP4_FREF_DR7_SC_SHIFT 20
#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
#define OMAP4_GPIO_DR7_SC_SHIFT 18
#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
#define OMAP4_DPM_DR0_SC_SHIFT 14
#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
#define OMAP4_SIM_DR0_SC_SHIFT 12
#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
/* CONTROL_SMART1NOPMIO_PADCONF_1 */
#define OMAP4_FREF_DR0_LB_SHIFT 30
#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
#define OMAP4_FREF_DR1_LB_SHIFT 28
#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
#define OMAP4_FREF_DR4_LB_SHIFT 26
#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
#define OMAP4_FREF_DR5_LB_SHIFT 24
#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
#define OMAP4_FREF_DR6_LB_SHIFT 22
#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
#define OMAP4_FREF_DR7_LB_SHIFT 20
#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
#define OMAP4_GPIO_DR7_LB_SHIFT 18
#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
#define OMAP4_DPM_DR0_LB_SHIFT 14
#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
#define OMAP4_SIM_DR0_LB_SHIFT 12
#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
/* CONTROL_PADCONF_MODE */
#define OMAP4_VDDS_DV_FREF_SHIFT 31
#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
#define OMAP4_VDDS_DV_BANK2_SHIFT 30
#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
/* CONTROL_XTAL_OSCILLATOR */
#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
/* CONTROL_USIMIO */
#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
#define OMAP4_USIM_PWRDNZ_SHIFT 28
#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
/* CONTROL_I2C_2 */
#define OMAP4_SR_SDA_GLFENB_SHIFT 31
#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
#define OMAP4_SR_SCL_GLFENB_SHIFT 27
#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
/* CONTROL_JTAG */
#define OMAP4_JTAG_NTRST_EN_SHIFT 31
#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
#define OMAP4_JTAG_TCK_EN_SHIFT 30
#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
#define OMAP4_JTAG_RTCK_EN_SHIFT 29
#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
#define OMAP4_JTAG_TDI_EN_SHIFT 28
#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
#define OMAP4_JTAG_TDO_EN_SHIFT 27
#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
/* CONTROL_SYS */
#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
/* WKUP_CONTROL_SPARE_RW */
#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
/* WKUP_CONTROL_SPARE_R */
#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
/* WKUP_CONTROL_SPARE_R_C0 */
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
#endif
arch/arm/mach-omap2/dpll3xxx.c
View file @ ba66d7f0
...@@ -28,11 +28,8 @@ ...@@ -28,11 +28,8 @@
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include "soc.h"
#include "clockdomain.h" #include "clockdomain.h"
#include "clock.h" #include "clock.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
#define DPLL_AUTOIDLE_DISABLE 0x0 #define DPLL_AUTOIDLE_DISABLE 0x0
...@@ -310,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) ...@@ -310,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
* Set jitter correction. Jitter correction applicable for OMAP343X * Set jitter correction. Jitter correction applicable for OMAP343X
* only since freqsel field is no longer present on other devices. * only since freqsel field is no longer present on other devices.
*/ */
if (cpu_is_omap343x()) { if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
v = omap2_clk_readl(clk, dd->control_reg); v = omap2_clk_readl(clk, dd->control_reg);
v &= ~dd->freqsel_mask; v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask); v |= freqsel << __ffs(dd->freqsel_mask);
...@@ -512,7 +509,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -512,7 +509,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL; return -EINVAL;
/* Freqsel is available only on OMAP343X devices */ /* Freqsel is available only on OMAP343X devices */
if (cpu_is_omap343x()) { if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
freqsel = _omap3_dpll_compute_freqsel(clk, freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n); dd->last_rounded_n);
WARN_ON(!freqsel); WARN_ON(!freqsel);
......
arch/arm/mach-omap2/dpll44xx.c
View file @ ba66d7f0
...@@ -15,10 +15,7 @@ ...@@ -15,10 +15,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include "soc.h"
#include "clock.h" #include "clock.h"
#include "clock44xx.h"
#include "cm-regbits-44xx.h"
/* /*
* Maximum DPLL input frequency (FINT) and output frequency (FOUT) that * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
...@@ -29,13 +26,23 @@ ...@@ -29,13 +26,23 @@
#define OMAP4_DPLL_LP_FINT_MAX 1000000 #define OMAP4_DPLL_LP_FINT_MAX 1000000
#define OMAP4_DPLL_LP_FOUT_MAX 100000000 #define OMAP4_DPLL_LP_FOUT_MAX 100000000
/*
* Bitfield declarations
*/
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
/* Static rate multiplier for OMAP4 REGM4XEN clocks */
#define OMAP4430_REGM4XEN_MULT 4
/* Supported only on OMAP4 */ /* Supported only on OMAP4 */
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
{ {
u32 v; u32 v;
u32 mask; u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) if (!clk || !clk->clksel_reg)
return -EINVAL; return -EINVAL;
mask = clk->flags & CLOCK_CLKOUTX2 ? mask = clk->flags & CLOCK_CLKOUTX2 ?
...@@ -54,7 +61,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) ...@@ -54,7 +61,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
u32 v; u32 v;
u32 mask; u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) if (!clk || !clk->clksel_reg)
return; return;
mask = clk->flags & CLOCK_CLKOUTX2 ? mask = clk->flags & CLOCK_CLKOUTX2 ?
...@@ -72,7 +79,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) ...@@ -72,7 +79,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
u32 v; u32 v;
u32 mask; u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) if (!clk || !clk->clksel_reg)
return; return;
mask = clk->flags & CLOCK_CLKOUTX2 ? mask = clk->flags & CLOCK_CLKOUTX2 ?
......
arch/arm/mach-omap2/io.c
View file @ ba66d7f0
...@@ -728,6 +728,8 @@ int __init omap_clk_init(void) ...@@ -728,6 +728,8 @@ int __init omap_clk_init(void)
if (!omap_clk_soc_init) if (!omap_clk_soc_init)
return 0; return 0;
ti_clk_init_features();
ret = of_prcm_init(); ret = of_prcm_init();
if (!ret) if (!ret)
ret = omap_clk_soc_init(); ret = omap_clk_soc_init();
......
arch/arm/mach-omap2/pm24xx.c
View file @ ba66d7f0
...@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void) ...@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
/* Clear old wake-up events */ /* Clear old wake-up events */
/* REVISIT: These write to reserved bits? */ /* REVISIT: These write to reserved bits? */
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
...@@ -104,23 +104,18 @@ static int omap2_enter_full_retention(void) ...@@ -104,23 +104,18 @@ static int omap2_enter_full_retention(void)
clk_enable(osc_ck); clk_enable(osc_ck);
/* clear CORE wake-up events */ /* clear CORE wake-up events */
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
/* wakeup domain events - bit 1: GPT1, bit5 GPIO */ /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
/* MPU domain wake events */ /* MPU domain wake events */
l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
if (l & 0x01) 0x1);
omap2_prm_write_mod_reg(0x01, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
if (l & 0x20)
omap2_prm_write_mod_reg(0x20, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
/* Mask future PRCM-to-MPU interrupts */ omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 0x20);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
...@@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void) ...@@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void)
* it is in retention mode. */ * it is in retention mode. */
if (omap2_allow_mpu_retention()) { if (omap2_allow_mpu_retention()) {
/* REVISIT: These write to reserved bits? */ /* REVISIT: These write to reserved bits? */
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
/* Try to enter MPU retention */ /* Try to enter MPU retention */
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
......
arch/arm/mach-omap2/pm34xx.c
View file @ ba66d7f0
...@@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void) ...@@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void)
} }
} }
/*
* PRCM Interrupt Handler Helper Function
*
* The purpose of this function is to clear any wake-up events latched
* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
* may occur whilst attempting to clear a PM_WKST_x register and thus
* set another bit in this register. A while loop is used to ensure
* that any peripheral wake-up events occurring while attempting to
* clear the PM_WKST_x are detected and cleared.
*/
static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
{
u32 wkst, fclk, iclk, clken;
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
u16 grpsel_off = (regs == 3) ?
OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
int c = 0;
wkst = omap2_prm_read_mod_reg(module, wkst_off);
wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
wkst &= ~ignore_bits;
if (wkst) {
iclk = omap2_cm_read_mod_reg(module, iclk_off);
fclk = omap2_cm_read_mod_reg(module, fclk_off);
while (wkst) {
clken = wkst;
omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
/*
* For USBHOST, we don't know whether HOST1 or
* HOST2 woke us up, so enable both f-clocks
*/
if (module == OMAP3430ES2_USBHOST_MOD)
clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
omap2_prm_write_mod_reg(wkst, module, wkst_off);
wkst = omap2_prm_read_mod_reg(module, wkst_off);
wkst &= ~ignore_bits;
c++;
}
omap2_cm_write_mod_reg(iclk, module, iclk_off);
omap2_cm_write_mod_reg(fclk, module, fclk_off);
}
return c;
}
static irqreturn_t _prcm_int_handle_io(int irq, void *unused) static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
{ {
int c; int c;
c = prcm_clear_mod_irqs(WKUP_MOD, 1, c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); ~(OMAP3430_ST_IO_MASK |
OMAP3430_ST_IO_CHAIN_MASK));
return c ? IRQ_HANDLED : IRQ_NONE; return c ? IRQ_HANDLED : IRQ_NONE;
} }
...@@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) ...@@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
* these are handled in a separate handler to avoid acking * these are handled in a separate handler to avoid acking
* IO events before parsing in mux code * IO events before parsing in mux code
*/ */
c = prcm_clear_mod_irqs(WKUP_MOD, 1, c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); OMAP3430_ST_IO_MASK |
c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); OMAP3430_ST_IO_CHAIN_MASK);
c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
if (omap_rev() > OMAP3430_REV_ES1_0) { if (omap_rev() > OMAP3430_REV_ES1_0) {
c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
} }
return c ? IRQ_HANDLED : IRQ_NONE; return c ? IRQ_HANDLED : IRQ_NONE;
...@@ -399,159 +353,11 @@ static int omap3_pm_suspend(void) ...@@ -399,159 +353,11 @@ static int omap3_pm_suspend(void)
#define omap3_pm_suspend NULL #define omap3_pm_suspend NULL
#endif /* CONFIG_SUSPEND */ #endif /* CONFIG_SUSPEND */
/**
* omap3_iva_idle(): ensure IVA is in idle so it can be put into
* retention
*
* In cases where IVA2 is activated by bootcode, it may prevent
* full-chip retention or off-mode because it is not idle. This
* function forces the IVA2 into idle state so it can go
* into retention/off and thus allow full-chip retention/off.
*
**/
static void __init omap3_iva_idle(void)
{
/* ensure IVA2 clock is disabled */
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
/* if no clock activity, nothing else to do */
if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
OMAP3430_CLKACTIVITY_IVA2_MASK))
return;
/* Reset IVA2 */
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
OMAP3430_RST2_IVA2_MASK |
OMAP3430_RST3_IVA2_MASK,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Enable IVA2 clock */
omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Set IVA2 boot mode to 'idle' */
omap3_ctrl_set_iva_bootmode_idle();
/* Un-reset IVA2 */
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Disable IVA2 clock */
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Reset IVA2 */
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
OMAP3430_RST2_IVA2_MASK |
OMAP3430_RST3_IVA2_MASK,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
}
static void __init omap3_d2d_idle(void)
{
u16 mask, padconf;
/* In a stand alone OMAP3430 where there is not a stacked
* modem for the D2D Idle Ack and D2D MStandby must be pulled
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
padconf |= mask;
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
padconf |= mask;
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
/* reset modem */
omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
CORE_MOD, OMAP2_RM_RSTCTRL);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
}
static void __init prcm_setup_regs(void) static void __init prcm_setup_regs(void)
{ {
u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? omap3_ctrl_init();
OMAP3630_EN_UART4_MASK : 0;
u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
OMAP3630_GRPSEL_UART4_MASK : 0;
/* XXX This should be handled by hwmod code or SCM init code */
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
/*
* Enable control of expternal oscillator through
* sys_clkreq. In the long run clock framework should
* take care of this.
*/
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
OMAP3430_GR_MOD,
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
/* setup wakup source */
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
WKUP_MOD, PM_WKEN);
/* No need to write EN_IO, that is always enabled */
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
OMAP3430_GRPSEL_GPT1_MASK |
OMAP3430_GRPSEL_GPT12_MASK,
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
/* Enable PM_WKEN to support DSS LPR */
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
OMAP3430_DSS_MOD, PM_WKEN);
/* Enable wakeups in PER */
omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
OMAP3430_EN_MCBSP4_MASK,
OMAP3430_PER_MOD, PM_WKEN);
/* and allow them to wake up MPU */
omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
OMAP3430_GRPSEL_GPIO2_MASK |
OMAP3430_GRPSEL_GPIO3_MASK |
OMAP3430_GRPSEL_GPIO4_MASK |
OMAP3430_GRPSEL_GPIO5_MASK |
OMAP3430_GRPSEL_GPIO6_MASK |
OMAP3430_GRPSEL_UART3_MASK |
OMAP3430_GRPSEL_MCBSP2_MASK |
OMAP3430_GRPSEL_MCBSP3_MASK |
OMAP3430_GRPSEL_MCBSP4_MASK,
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
/* Don't attach IVA interrupts */
if (omap3_has_iva()) {
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
OMAP3430_PM_IVAGRPSEL);
}
/* Clear any pending 'reset' flags */
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
/* Clear any pending PRCM interrupts */
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
/*
* We need to idle iva2_pwrdm even on am3703 with no iva2.
*/
omap3_iva_idle();
omap3_d2d_idle(); omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
} }
void omap3_pm_off_mode_enable(int enable) void omap3_pm_off_mode_enable(int enable)
......
arch/arm/mach-omap2/prm2xxx.c
View file @ ba66d7f0
...@@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void) ...@@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void)
omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
} }
/**
* omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
* @module: PRM module to clear wakeups from
* @regs: register offset to clear
* @wkst_mask: wakeup status mask to clear
*
* Clears wakeup status bits for a given module, so that the device can
* re-enter idle.
*/
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
{
u32 wkst;
wkst = omap2_prm_read_mod_reg(module, regs);
wkst &= wkst_mask;
omap2_prm_write_mod_reg(wkst, module, regs);
}
int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
{ {
omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
......
arch/arm/mach-omap2/prm2xxx.h
View file @ ba66d7f0
...@@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); ...@@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
extern void omap2xxx_prm_dpll_reset(void); extern void omap2xxx_prm_dpll_reset(void);
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
extern int __init omap2xxx_prm_init(void); extern int __init omap2xxx_prm_init(void);
......
arch/arm/mach-omap2/prm3xxx.c
View file @ ba66d7f0
...@@ -26,6 +26,8 @@ ...@@ -26,6 +26,8 @@
#include "prm2xxx_3xxx.h" #include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h" #include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h" #include "prm-regbits-34xx.h"
#include "cm3xxx.h"
#include "cm-regbits-34xx.h"
static const struct omap_prcm_irq omap3_prcm_irqs[] = { static const struct omap_prcm_irq omap3_prcm_irqs[] = {
OMAP_PRCM_IRQ("wkup", 0, 0), OMAP_PRCM_IRQ("wkup", 0, 0),
...@@ -205,6 +207,167 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask) ...@@ -205,6 +207,167 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
OMAP3_PRM_IRQENABLE_MPU_OFFSET); OMAP3_PRM_IRQENABLE_MPU_OFFSET);
} }
/**
* omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
* @module: PRM module to clear wakeups from
* @regs: register set to clear, 1 or 3
* @ignore_bits: wakeup status bits to ignore
*
* The purpose of this function is to clear any wake-up events latched
* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
* may occur whilst attempting to clear a PM_WKST_x register and thus
* set another bit in this register. A while loop is used to ensure
* that any peripheral wake-up events occurring while attempting to
* clear the PM_WKST_x are detected and cleared.
*/
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
{
u32 wkst, fclk, iclk, clken;
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
u16 grpsel_off = (regs == 3) ?
OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
int c = 0;
wkst = omap2_prm_read_mod_reg(module, wkst_off);
wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
wkst &= ~ignore_bits;
if (wkst) {
iclk = omap2_cm_read_mod_reg(module, iclk_off);
fclk = omap2_cm_read_mod_reg(module, fclk_off);
while (wkst) {
clken = wkst;
omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
/*
* For USBHOST, we don't know whether HOST1 or
* HOST2 woke us up, so enable both f-clocks
*/
if (module == OMAP3430ES2_USBHOST_MOD)
clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
omap2_prm_write_mod_reg(wkst, module, wkst_off);
wkst = omap2_prm_read_mod_reg(module, wkst_off);
wkst &= ~ignore_bits;
c++;
}
omap2_cm_write_mod_reg(iclk, module, iclk_off);
omap2_cm_write_mod_reg(fclk, module, fclk_off);
}
return c;
}
/**
* omap3_prm_reset_modem - toggle reset signal for modem
*
* Toggles the reset signal to modem IP block. Required to allow
* OMAP3430 without stacked modem to idle properly.
*/
void __init omap3_prm_reset_modem(void)
{
omap2_prm_write_mod_reg(
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
CORE_MOD, OMAP2_RM_RSTCTRL);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
}
/**
* omap3_prm_init_pm - initialize PM related registers for PRM
* @has_uart4: SoC has UART4
* @has_iva: SoC has IVA
*
* Initializes PRM registers for PM use. Called from PM init.
*/
void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
{
u32 en_uart4_mask;
u32 grpsel_uart4_mask;
/*
* Enable control of expternal oscillator through
* sys_clkreq. In the long run clock framework should
* take care of this.
*/
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
OMAP3430_GR_MOD,
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
/* setup wakup source */
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
WKUP_MOD, PM_WKEN);
/* No need to write EN_IO, that is always enabled */
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
OMAP3430_GRPSEL_GPT1_MASK |
OMAP3430_GRPSEL_GPT12_MASK,
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
/* Enable PM_WKEN to support DSS LPR */
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
OMAP3430_DSS_MOD, PM_WKEN);
if (has_uart4) {
en_uart4_mask = OMAP3630_EN_UART4_MASK;
grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
}
/* Enable wakeups in PER */
omap2_prm_write_mod_reg(en_uart4_mask |
OMAP3430_EN_GPIO2_MASK |
OMAP3430_EN_GPIO3_MASK |
OMAP3430_EN_GPIO4_MASK |
OMAP3430_EN_GPIO5_MASK |
OMAP3430_EN_GPIO6_MASK |
OMAP3430_EN_UART3_MASK |
OMAP3430_EN_MCBSP2_MASK |
OMAP3430_EN_MCBSP3_MASK |
OMAP3430_EN_MCBSP4_MASK,
OMAP3430_PER_MOD, PM_WKEN);
/* and allow them to wake up MPU */
omap2_prm_write_mod_reg(grpsel_uart4_mask |
OMAP3430_GRPSEL_GPIO2_MASK |
OMAP3430_GRPSEL_GPIO3_MASK |
OMAP3430_GRPSEL_GPIO4_MASK |
OMAP3430_GRPSEL_GPIO5_MASK |
OMAP3430_GRPSEL_GPIO6_MASK |
OMAP3430_GRPSEL_UART3_MASK |
OMAP3430_GRPSEL_MCBSP2_MASK |
OMAP3430_GRPSEL_MCBSP3_MASK |
OMAP3430_GRPSEL_MCBSP4_MASK,
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
/* Don't attach IVA interrupts */
if (has_iva) {
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
OMAP3430_PM_IVAGRPSEL);
}
/* Clear any pending 'reset' flags */
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
OMAP2_RM_RSTST);
/* Clear any pending PRCM interrupts */
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
/* We need to idle iva2_pwrdm even on am3703 with no iva2. */
omap3xxx_prm_iva_idle();
omap3_prm_reset_modem();
}
/** /**
* omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
* *
...@@ -276,6 +439,76 @@ static u32 omap3xxx_prm_read_reset_sources(void) ...@@ -276,6 +439,76 @@ static u32 omap3xxx_prm_read_reset_sources(void)
return r; return r;
} }
/**
* omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
*
* In cases where IVA2 is activated by bootcode, it may prevent
* full-chip retention or off-mode because it is not idle. This
* function forces the IVA2 into idle state so it can go
* into retention/off and thus allow full-chip retention/off.
*/
void omap3xxx_prm_iva_idle(void)
{
/* ensure IVA2 clock is disabled */
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
/* if no clock activity, nothing else to do */
if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
OMAP3430_CLKACTIVITY_IVA2_MASK))
return;
/* Reset IVA2 */
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
OMAP3430_RST2_IVA2_MASK |
OMAP3430_RST3_IVA2_MASK,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Enable IVA2 clock */
omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Un-reset IVA2 */
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Disable IVA2 clock */
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Reset IVA2 */
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
OMAP3430_RST2_IVA2_MASK |
OMAP3430_RST3_IVA2_MASK,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
}
/**
* omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
* and clears it if asserted
*
* Checks if cold-reset has occurred and clears the status bit if yes. Returns
* 1 if cold-reset has occurred, 0 otherwise.
*/
int omap3xxx_prm_clear_global_cold_reset(void)
{
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
OMAP3430_GLOBAL_COLD_RST_MASK) {
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
OMAP3430_GR_MOD,
OMAP3_PRM_RSTST_OFFSET);
return 1;
}
return 0;
}
void omap3_prm_save_scratchpad_contents(u32 *ptr)
{
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
OMAP3_PRM_CLKSEL_OFFSET);
}
/* Powerdomain low-level functions */ /* Powerdomain low-level functions */
static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
......
arch/arm/mach-omap2/prm3xxx.h
View file @ ba66d7f0
...@@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void); ...@@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void);
extern int __init omap3xxx_prm_init(void); extern int __init omap3xxx_prm_init(void);
extern u32 omap3xxx_prm_get_reset_sources(void); extern u32 omap3xxx_prm_get_reset_sources(void);
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
void omap3xxx_prm_iva_idle(void);
void omap3_prm_reset_modem(void);
int omap3xxx_prm_clear_global_cold_reset(void);
void omap3_prm_save_scratchpad_contents(u32 *ptr);
void omap3_prm_init_pm(bool has_uart4, bool has_iva);
#endif /* __ASSEMBLER */ #endif /* __ASSEMBLER */
......
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