Commit c4e7aba6 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Krzysztof Kozlowski

arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC

This patch adds support for MFC power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, MFC codec device and its
SYSMMUs.
Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent e45dda53
...@@ -486,6 +486,7 @@ cmu_mfc: clock-controller@15280000 { ...@@ -486,6 +486,7 @@ cmu_mfc: clock-controller@15280000 {
clock-names = "oscclk", "aclk_mfc_400"; clock-names = "oscclk", "aclk_mfc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
power-domains = <&pd_mfc>;
}; };
cmu_hevc: clock-controller@14f80000 { cmu_hevc: clock-controller@14f80000 {
...@@ -567,6 +568,13 @@ pd_disp: power-domain@105c4080 { ...@@ -567,6 +568,13 @@ pd_disp: power-domain@105c4080 {
label = "DISP"; label = "DISP";
}; };
pd_mfc: power-domain@105c4180 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4180 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
tmu_atlas0: tmu@10060000 { tmu_atlas0: tmu@10060000 {
compatible = "samsung,exynos5433-tmu"; compatible = "samsung,exynos5433-tmu";
reg = <0x10060000 0x200>; reg = <0x10060000 0x200>;
...@@ -992,6 +1000,7 @@ mfc: codec@152E0000 { ...@@ -992,6 +1000,7 @@ mfc: codec@152E0000 {
<&cmu_mfc CLK_ACLK_XIU_MFCX>; <&cmu_mfc CLK_ACLK_XIU_MFCX>;
iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
iommu-names = "left", "right"; iommu-names = "left", "right";
power-domains = <&pd_mfc>;
}; };
sysmmu_decon0x: sysmmu@13a00000 { sysmmu_decon0x: sysmmu@13a00000 {
...@@ -1090,6 +1099,7 @@ sysmmu_mfc_0: sysmmu@15200000 { ...@@ -1090,6 +1099,7 @@ sysmmu_mfc_0: sysmmu@15200000 {
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_0>; <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_mfc>;
}; };
sysmmu_mfc_1: sysmmu@15210000 { sysmmu_mfc_1: sysmmu@15210000 {
...@@ -1100,6 +1110,7 @@ sysmmu_mfc_1: sysmmu@15210000 { ...@@ -1100,6 +1110,7 @@ sysmmu_mfc_1: sysmmu@15210000 {
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_1>; <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_mfc>;
}; };
serial_0: serial@14c10000 { serial_0: serial@14c10000 {
......
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