Commit d0ac6119 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'tegra-for-4.5-soc' of...

Merge tag 'tegra-for-4.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into late/tegra

ARM: tegra: Core SoC changes for v4.5-rc1

The big thing here is Tegra210 support, which is really only the Kconfig
symbol. Other than that there's a few miscellaneous fixes.

* tag 'tegra-for-4.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: select USB_ULPI from EHCI rather than platform
  ARM: tegra: Ensure entire dcache is flushed on entering LP0/1
  amba: Hide TEGRA_AHB symbol
  soc/tegra: Add Tegra210 support
  soc/tegra: Provide per-SoC Kconfig symbols
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3e912195 a262e87f
...@@ -13,57 +13,5 @@ menuconfig ARCH_TEGRA ...@@ -13,57 +13,5 @@ menuconfig ARCH_TEGRA
select ARCH_HAS_RESET_CONTROLLER select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER select RESET_CONTROLLER
select SOC_BUS select SOC_BUS
select USB_ULPI if USB_PHY
select USB_ULPI_VIEWPORT if USB_PHY
help help
This enables support for NVIDIA Tegra based systems. This enables support for NVIDIA Tegra based systems.
if ARCH_TEGRA
config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_ERRATA_720789
select ARM_ERRATA_754327 if SMP
select ARM_ERRATA_764369 if SMP
select PINCTRL_TEGRA20
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select TEGRA_TIMER
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select PINCTRL_TEGRA30
select PL310_ERRATA_769419 if CACHE_L2X0
select TEGRA_TIMER
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_114_SOC
bool "Enable support for Tegra114 family"
select ARM_ERRATA_798181 if SMP
select ARM_L1_CACHE_SHIFT_6
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA114
select TEGRA_TIMER
help
Support for NVIDIA Tegra T114 processor family, based on the
ARM CortexA15MP CPU
config ARCH_TEGRA_124_SOC
bool "Enable support for Tegra124 family"
select ARM_L1_CACHE_SHIFT_6
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA124
select TEGRA_TIMER
help
Support for NVIDIA Tegra T124 processor family, based on the
ARM CortexA15MP CPU
endif
...@@ -231,8 +231,11 @@ ENDPROC(tegra20_cpu_is_resettable_soon) ...@@ -231,8 +231,11 @@ ENDPROC(tegra20_cpu_is_resettable_soon)
* tegra20_tear_down_core in IRAM * tegra20_tear_down_core in IRAM
*/ */
ENTRY(tegra20_sleep_core_finish) ENTRY(tegra20_sleep_core_finish)
mov r4, r0
/* Flush, disable the L1 data cache and exit SMP */ /* Flush, disable the L1 data cache and exit SMP */
mov r0, #TEGRA_FLUSH_CACHE_ALL
bl tegra_disable_clean_inv_dcache bl tegra_disable_clean_inv_dcache
mov r0, r4
mov32 r3, tegra_shut_off_mmu mov32 r3, tegra_shut_off_mmu
add r3, r3, r0 add r3, r3, r0
......
...@@ -242,8 +242,11 @@ ENDPROC(tegra30_cpu_shutdown) ...@@ -242,8 +242,11 @@ ENDPROC(tegra30_cpu_shutdown)
* tegra30_tear_down_core in IRAM * tegra30_tear_down_core in IRAM
*/ */
ENTRY(tegra30_sleep_core_finish) ENTRY(tegra30_sleep_core_finish)
mov r4, r0
/* Flush, disable the L1 data cache and exit SMP */ /* Flush, disable the L1 data cache and exit SMP */
mov r0, #TEGRA_FLUSH_CACHE_ALL
bl tegra_disable_clean_inv_dcache bl tegra_disable_clean_inv_dcache
mov r0, r4
/* /*
* Preload all the address literals that are needed for the * Preload all the address literals that are needed for the
......
...@@ -86,18 +86,6 @@ config ARCH_TEGRA ...@@ -86,18 +86,6 @@ config ARCH_TEGRA
help help
This enables support for the NVIDIA Tegra SoC family. This enables support for the NVIDIA Tegra SoC family.
config ARCH_TEGRA_132_SOC
bool "NVIDIA Tegra132 SoC"
depends on ARCH_TEGRA
select PINCTRL_TEGRA124
select USB_ULPI if USB_PHY
select USB_ULPI_VIEWPORT if USB_PHY
help
Enable support for NVIDIA Tegra132 SoC, based on the Denver
ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
but contains an NVIDIA Denver CPU complex in place of
Tegra124's "4+1" Cortex-A15 CPU complex.
config ARCH_SPRD config ARCH_SPRD
bool "Spreadtrum SoC platform" bool "Spreadtrum SoC platform"
help help
......
...@@ -4,7 +4,7 @@ config ARM_AMBA ...@@ -4,7 +4,7 @@ config ARM_AMBA
if ARM_AMBA if ARM_AMBA
config TEGRA_AHB config TEGRA_AHB
bool "Enable AHB driver for NVIDIA Tegra SoCs" bool
default y if ARCH_TEGRA default y if ARCH_TEGRA
help help
Adds AHB configuration functionality for NVIDIA Tegra SoCs, Adds AHB configuration functionality for NVIDIA Tegra SoCs,
......
...@@ -5,6 +5,7 @@ source "drivers/soc/mediatek/Kconfig" ...@@ -5,6 +5,7 @@ source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig" source "drivers/soc/qcom/Kconfig"
source "drivers/soc/rockchip/Kconfig" source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/sunxi/Kconfig" source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/tegra/Kconfig"
source "drivers/soc/ti/Kconfig" source "drivers/soc/ti/Kconfig"
source "drivers/soc/versatile/Kconfig" source "drivers/soc/versatile/Kconfig"
......
if ARCH_TEGRA
# 32-bit ARM SoCs
if ARM
config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_ERRATA_720789
select ARM_ERRATA_754327 if SMP
select ARM_ERRATA_764369 if SMP
select PINCTRL_TEGRA20
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select TEGRA_TIMER
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select PINCTRL_TEGRA30
select PL310_ERRATA_769419 if CACHE_L2X0
select TEGRA_TIMER
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_114_SOC
bool "Enable support for Tegra114 family"
select ARM_ERRATA_798181 if SMP
select ARM_L1_CACHE_SHIFT_6
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA114
select TEGRA_TIMER
help
Support for NVIDIA Tegra T114 processor family, based on the
ARM CortexA15MP CPU
config ARCH_TEGRA_124_SOC
bool "Enable support for Tegra124 family"
select ARM_L1_CACHE_SHIFT_6
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA124
select TEGRA_TIMER
help
Support for NVIDIA Tegra T124 processor family, based on the
ARM CortexA15MP CPU
endif
# 64-bit ARM SoCs
if ARM64
config ARCH_TEGRA_132_SOC
bool "NVIDIA Tegra132 SoC"
select PINCTRL_TEGRA124
help
Enable support for NVIDIA Tegra132 SoC, based on the Denver
ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
but contains an NVIDIA Denver CPU complex in place of
Tegra124's "4+1" Cortex-A15 CPU complex.
config ARCH_TEGRA_210_SOC
bool "NVIDIA Tegra210 SoC"
select PINCTRL_TEGRA210
help
Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
cores in a switched configuration. It features a GPU of the Maxwell
architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
and providing 256 CUDA cores. It supports hardware-accelerated en-
and decoding of various video standards including H.265, H.264 and
VP8 at 4K resolution and up to 60 fps.
Besides the multimedia features it also comes with a variety of I/O
controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.
endif
endif
...@@ -220,6 +220,8 @@ config USB_EHCI_TEGRA ...@@ -220,6 +220,8 @@ config USB_EHCI_TEGRA
depends on ARCH_TEGRA depends on ARCH_TEGRA
select USB_EHCI_ROOT_HUB_TT select USB_EHCI_ROOT_HUB_TT
select USB_PHY select USB_PHY
select USB_ULPI
select USB_ULPI_VIEWPORT
help help
This driver enables support for the internal USB Host Controllers This driver enables support for the internal USB Host Controllers
found in NVIDIA Tegra SoCs. The controllers are EHCI compliant. found in NVIDIA Tegra SoCs. The controllers are EHCI compliant.
......
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