- 23 Aug, 2017 5 commits
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Stephen Boyd authored
Silence the sparse warning clk/rockchip/clk.c:172:6: warning: symbol 'rockchip_fractional_approximation' was not declared. Should it be static? Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by:Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: The biggest change is fixing the jitter on the fractional clock-type Rockchip socs experience with the default approximation. For that we introduce the ability to override it with a clock-specific approximation and use that to create the needed rate settings as described in the Rockchip soc manuals (same for all Rockchip socs). Apart from that we have support for the rk3126 clock controller which is similar to the rk3128 with some minimal differences and a lot of improvements and fixes for the rv1108 clock controller (missing clocks, some clock-ids, naming fixes, register fixes). * tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rv1108 clk_mac sel register description clk: rockchip: rename rv1108 macphy clock to mac clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID clk: rockchip: add rk3228 sclk_sdio_src ID clk: rockchip: add special approximation to fix up fractional clk's jitter clk: fractional-divider: allow overriding of approximation clk: rockchip: modify rk3128 clk driver to also support rk3126 dt-bindings: add documentation for rk3126 clock clk: rockchip: add some critical clocks for rv1108 SoC clk: rockchip: rename some of clks for rv1108 SoC clk: rockchip: fix up some clks describe error for rv1108 SoC clk: rockchip: support more clks for rv1108 clk: rockchip: fix up the pll clks error for rv1108 SoC clk: rockchip: support more rates for rv1108 cpuclk clk: rockchip: fix up indentation of some RV1108 clock-ids clk: rockchip: rename the clk id for HCLK_I2S1_2CH clk: rockchip: add more clk ids for rv1108
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock changes from Chen-Yu Tsai: * Added support for fixed post-divider on divider and NKM-style clocks * Added driver for R40 CCU * Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo * Make fractional clock modes really used and correctly configured * Make H3 cpu clock rate change correctly to be used with cpufreq * tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: support R40 SoC dt-bindings: add compatible string for Allwinner R40 CCU clk: sunxi-ng: nkm: add support for fixed post-divider clk: sunxi-ng: div: Add support for fixed post-divider dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change clk: sunxi-ng: Wait for lock when using fractional mode clk: sunxi-ng: Make fractional helper less chatty clk: sunxi-ng: multiplier: Fix fractional mode clk: sunxi-ng: Fix fractional mode for N-M clocks clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
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Stephen Boyd authored
Merge tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: Changes in definitions of audio related clocks for Exynos5420/5422/5800 SoCs: a fix of mau_epll clock definition and changes enabling clock rate setting propagation on a path from the I2S IP block up the EPLL. * tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks clk: samsung: Fix mau_epll clock definition for exynos5422
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git://github.com/baylibre/clk-mesonStephen Boyd authored
Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller
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- 22 Aug, 2017 4 commits
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Elaine Zhang authored
The source clock ordering is wrong, as shown in the TRM: cru_sel24_con[8] rmii_extclk_sel clock source select control register 1'b0: from internal PLL 1'b1: from external IO Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by:
David Wu <david.wu@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Elaine Zhang authored
This MAC has no internal phy for rv1108 and the whole clock infrastructure hasn't been used yet, so is safe to fix. Signed-off-by:
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Elaine Zhang authored
Add gmac aclk and pclk clock gates. Signed-off-by:
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Elaine Zhang authored
In some special circumstances, may be need to reparent clk for sclk_sdio_src. Signed-off-by:
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- 21 Aug, 2017 3 commits
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Heiko Stuebner authored
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Elaine Zhang authored
This patch exports gmac aclk and pclk for dts reference. Signed-off-by:
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Elaine Zhang authored
This patch exports sdio src clock for dts reference. Signed-off-by:
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- 19 Aug, 2017 2 commits
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Icenowy Zheng authored
Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
Chen-Yu Tsai <wens@csie.org>
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Icenowy Zheng authored
Allwinner R40 has a clock controlling unit like the ones on other Allwinner SoCs after sun6i, and can also use a CCU-based driver. Add a compatible string for it. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 14 Aug, 2017 2 commits
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Icenowy Zheng authored
SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is the fixed post-divider. Add post-divider support for NKM type clock. Signed-off-by:
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Priit Laes authored
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by:
Priit Laes <plaes@plaes.org> Signed-off-by:
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- 11 Aug, 2017 1 commit
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Jonathan Liu authored
The bindings were not updated when the sun5i CCU driver was added in commit 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver"). Signed-off-by:
Jonathan Liu <net147@gmail.com> Acked-by:
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- 10 Aug, 2017 1 commit
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Sylwester Nawrocki authored
The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL and the audio subsystem clock controller so that the EPLL's output frequency can be set indirectly with clk_set_rate() on a leaf clock. That should be safe as EPLL is normally only used to generate clock for the audio subsystem. With this change we can avoid passing the EPLL clock to the ASoC machine driver. Signed-off-by:Sylwester Nawrocki <s.nawrocki@samsung.com>
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- 09 Aug, 2017 2 commits
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Sylwester Nawrocki authored
This allows clk rate propagation up to the clock tree so EPLL can be reprogrammed indirectly when setting rate of the Audio Subsystem clocks. The advantage is that sound machine driver can operate only on the leaf clocks rather than explicitly re-configuring the root clock (EPLL). Signed-off-by: -
Sylwester Nawrocki authored
Parent clock of the MAU_EPLL gate clock on exynos5422 is "mout_user_mau_epll", not "mout_mau_epll_clk". This change only affects exynos5422/5800. Signed-off-by:
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- 08 Aug, 2017 9 commits
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Elaine Zhang authored
>From Rockchips fractional divider description: 3.1.9 Fractional divider usage To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART. Therefore add a special approximation function that handles this special requirement. Signed-off-by:
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Elaine Zhang authored
Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation. For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies. Therefore add the ability to provide custom approximation functions. Signed-off-by:
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Elaine Zhang authored
rk3128 and rk3126 have some gate registers describe differences. So need to make some distinctions. The RK3126 and RK3128 Same clock description we move it to the common clock branches. And the different clks description use the own clock branches. Signed-off-by:
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Elaine Zhang authored
This add bindings documentation for rk3126 SoCs. Signed-off-by:
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Elaine Zhang authored
the bus/periph/nclk_ddrupctl/pclk_ddrmon/pclk_acodecphy/pclk_pmu no driver to handle them, Chip design requirements for these clock to always on. Signed-off-by:
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Elaine Zhang authored
Rename some of clks to keep the consistency with the TRM. Signed-off-by:
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Elaine Zhang authored
1. fix up the parent name 2. remove the CLK_IGNORE_UNUSED flag for some clk not need to always on. 3. fix up some clks regs describe error. Signed-off-by:
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Elaine Zhang authored
Add the description of the missing clock, make the clock more complete. Signed-off-by:
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Heiko Stuebner authored
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- 07 Aug, 2017 1 commit
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Elaine Zhang authored
fix up the lock_shift describe error. remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll. Signed-off-by:
Andy Yan <andy.yan@rock-chips.com> Signed-off-by:
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- 06 Aug, 2017 4 commits
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Elaine Zhang authored
fix up the cpuclk rates table for support more freqs. fix up the mux_core_mask describe error. Signed-off-by:
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Elaine Zhang authored
Make the code look better. Signed-off-by:
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Elaine Zhang authored
i2s1 has 2 channels but not 8 channels. Signed-off-by:
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Elaine Zhang authored
Add new clk ids for the peripherals on rv1108 soc. Signed-off-by:
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- 04 Aug, 2017 6 commits
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Neil Armstrong authored
The CEC 32K AO Clock is a dual divider with dual counter to provide a more precise 32768Hz clock for the CEC subsystem from the external xtal. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com>
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Neil Armstrong authored
Switch the aoclk driver to use the new bindings and switch all the registers access to regmap only. Signed-off-by: -
Neil Armstrong authored
On the first revision of the bindings, only the gates + resets were known in the AO Clock HW, but more registers used to configures AO clock are known to be spread among the AO register space. This patch adds a parent node for the entire system control zone for the AO domain then moves the clock controller as a subnode of the system control node. Signed-off-by: -
Jerome Brunet authored
Input source 0 of the mmc controllers is not directly xtal, as currently described in DT. Each controller is fed by a composite clock (the usual mux, divider and gate). The muxes inputs are the xtal (default) and the fclk_div clocks. These parents, along with the divider, should be able to provide the necessary rates for mmc and nand operation. The input muxes should also be able to take mpll2, mpll3 and gp0_pll but these are precious clocks, needed for other usage. It is better if the mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is not listed among the possible parents. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Jerome Brunet authored
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 3c277c24 ("clk: meson: gxbb: add cts_mclk_i958") Signed-off-by:
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Jerome Brunet authored
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 4087bd4b ("clk: meson: gxbb: add cts_amclk") Signed-off-by:
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