- 16 Jun, 2016 6 commits
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Daniel Vetter authored
Currently it's part of prepare_fb, still in the first phase of atomic_commit which might fail. Which means that we need to have some heuristics in cleanup_fb to figure out whether things failed, or whether we just clean up the old fbs. That's fragile, and worse, once we start pipelining commits gets confused: While the last commit is still getting cleanup up we already hammer in the new one, and fb_bits aren't refcounted, resulting in lost bits and WARN_ON galore. We could instead try to make cleanup_fb more clever, but a simpler fix is to postpone the fb_bits tracking past the point of no return, where we commit all the software state. That also makes conceptually more sense, since fb_bits must be updated synchronously from the ioctl (they track usage from userspace pov, not from the hw pov), right before we're fully committed to the updated. This fixes WARNING splats from track_fb with page_flip implemented through atomic_commit. Testcase: igt/kms_flip/flip-vs-rmfb Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1465827229-1704-4-git-send-email-daniel.vetter@ffwll.ch
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Daniel Vetter authored
Simply split intel_atomic_commit in half and place the new nonblocking commit helpers at the right spots. NOTE: There's still trouble with obj->frontbuffer bits getting mangled when pipelining atomic commits. v2: - Remove the check for nonblocking which returned -EINVAL. - Do wait for requests in the worker thread before committing hw state. v3: Move hw_done after the optimize_wm/post_plane_update step, plus add FIXME comment how to fix that up again properly. v4: Update FIXME for intel_atomic_commit - more stuff works now. v5: Still reject nonblocking modeset commits (Maarten). v6: Use intel_state->modeset (Maarten). Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
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Maarten Lankhorst authored
The patch was reverted as part of the original nonblocking commit support, but is required for any kind of nonblocking commit. This is required to let fbc updates run async. It has a lot of checks whether certain locks are taken, which can be removed when the relevant states are passed in as pointers. Signed-off-by:
Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/28208c38-8738-abdf-0cce-8d8f266b9c28@linux.intel.com
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Daniel Vetter authored
Right now still all blocking, no worker anywhere to be seen. Reviewed-by:
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Daniel Vetter authored
This is part of what atomic must implement. And it's also required to be able to use the helper nonblocking support. v2: Always send out the drm event, remove the planes_changed check. Reviewed-by:
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Daniel Vetter authored
Backmerge drm-next to get at the nonblocking atomic helpers, needed to merge the i915 conversion. Signed-off-by:
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- 15 Jun, 2016 4 commits
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
- best_encoder cleanup from Boris. - drm_simple_display_pipe helpers from Noralf. Looks really neat imo, and there's 2-3 in-flight drivers which look like they could/should use it. Anyway, with this we have now helpers and everything in place to write drivers for simple hw with fewer complexity in the driver than what fbdev would need. That was the last complaint I've heard from embedded folks after we made atomic happen. Mission accomplished! - nonblocking commit helpers for atomic, plus a bunch of driver patches for that. - Prep patch from Laurent for cleaned up pixel format functions. - More of Gustavo's cleanup for drm vblank functions. - and a few oddball things in between Plus the merge of docs-next to prep the docbook->sphinx conversion as discussed. Jon cc'ed as fyi. * tag 'topic/drm-misc-2016-06-15' of git://anongit.freedesktop.org/drm-intel: (108 commits) drm/atomic-helpers: Clear up cleanup_done a bit drm/atomic-helpers: Stall on the right commit drm/vmwgfx: use *_32_bits() macros drm/virtio: Don't reinvent a flipping wheel drm/i915: Fix missing unlock on error in i915_ppgtt_info() drm/gma500: use drm_crtc_vblank_{on,off}() drm/radeon: use crtc directly in drm_crtc_vblank_put() drm/amdgpu: use crtc directly in drm_crtc_vblank_put() drm/radeon: use drm_crtc_vblank_{on,off}() drm/amdgpu: use drm_crtc_vblank_{on,off}() drm: make drm_vblank_{get,put}() static drm: remove legacy drm_arm_vblank_event() drm: remove legacy drm_send_vblank_event() drm/nouveau: replace legacy vblank helpers drm/prime: fix error path deadlock fail drm/dsi: Add uevent callback drm: fb: cma: fix memory leak drm: i915: Rely on the default ->best_encoder() behavior where appropriate drm: Add helper for simple display pipeline drm/bridge: dw-hdmi: Use drm_atomic_helper_best_encoder() ...
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Daniel Vetter authored
It's not obvious at first sight that this is a fastpath, make that clearer with a goto. Fallout from a discussion with Liviu on irc. v2: Drop bogus hunks that crept in. v3: Make it compile. Cc: Liviu.Dudau@arm.com Acked-by: Liviu.Dudau@arm.com Signed-off-by:
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Daniel Vetter authored
stall_checks carefully picked out the right commit to stall on, then promptly used the wrong variable. Due to the break in the next loop iteration this could be the 3rd commit, or if the list only has 2 entries commit would now point into the struct drm_crtc itself, at some offset. Hilarity eventually ensues. For added safety, also break right away instead of iterating once more, but the real fix is waiting on stall_commit instead of commit. Reported-and-tested-by:
Liviu Dudau <Liviu.Dudau@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by:
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Paul Bolle authored
Use the upper_32_bits() macro instead of the four line equivalent that triggers a GCC warning on 32 bits x86: drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c: In function 'vmw_cmdbuf_header_submit': drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c:297:25: warning: right shift count >= width of type [-Wshift-count-overflow] val = (header->handle >> 32); ^ And use the lower_32_bits() macro instead of and-ing with a 32 bits mask. Signed-off-by:Paul Bolle <pebolle@tiscali.nl> Acked-by:
Joe Perches <joe@perches.com> Signed-off-by:
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- 14 Jun, 2016 15 commits
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Lyude authored
Thanks to Ville Syrjälä for pointing me towards the cause of this issue. Unfortunately one of the sideaffects of having the refclk for a DPLL set to SSC is that as long as it's set to SSC, the GPU will prevent us from powering down any of the pipes or transcoders using it. A couple of BIOSes enable SSC in both PCH_DREF_CONTROL and in the DPLL configurations. This causes issues on the first modeset, since we don't expect SSC to be left on and as a result, can't successfully power down the pipes or the transcoders using it. Here's an example from this Dell OptiPlex 990: [drm:intel_modeset_init] SSC enabled by BIOS, overriding VBT which says disabled [drm:intel_modeset_init] 2 display pipes available. [drm:intel_update_cdclk] Current CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max dotclock rate: 360000 kHz vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [drm:intel_crt_reset] crt adpa set to 0xf40000 [drm:intel_dp_init_connector] Adding DP connector on port C [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-1 [drm:ironlake_init_pch_refclk] has_panel 0 has_lvds 0 has_ck505 0 [drm:ironlake_init_pch_refclk] Disabling SSC entirely … later we try committing the first modeset … [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88041b02e800 for pipe A [drm:intel_dump_pipe_config] cpu_transcoder: A … [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xc4016001, dpll_md: 0x0, fp0: 0x20e08, fp1: 0x30d07 [drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [drm:intel_dump_pipe_config] FB:42, fb = 800x600 format = 0x34325258 [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 800x600 dst (0, 0) 800x600 [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [drm:intel_get_shared_dpll] CRTC:26 allocated PCH DPLL A [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [drm:ilk_audio_codec_disable] Disable audio codec on port C, pipe A [drm:intel_disable_pipe] disabling pipe A ------------[ cut here ]------------ WARNING: CPU: 1 PID: 130 at drivers/gpu/drm/i915/intel_display.c:1146 intel_disable_pipe+0x297/0x2d0 [i915] pipe_off wait timed out … ---[ end trace 94fc8aa03ae139e8 ]--- [drm:intel_dp_link_down] [drm:ironlake_crtc_disable [i915]] *ERROR* failed to disable transcoder A Later modesets succeed since they reset the DPLL's configuration anyway, but this is enough to get stuck with a big fat warning in dmesg. A better solution would be to add refcounts for the SSC source, but for now leaving the source clock on should suffice. Changes since v4: - Fix calculation of final for systems with LVDS panels (fixes BUG() on CI test suite) Changes since v3: - Move temp variable into loop - Move checks for using_ssc_source to after we've figured out has_ck505 - Add using_ssc_source to debug output Changes since v2: - Fix debug output for when we disable the CPU source Changes since v1: - Leave the SSC source clock on instead of just shutting it off on all of the DPLL configurations. Cc: stable@vger.kernel.org Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Lyude <cpaul@redhat.com> Signed-off-by:
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git://git.lwn.net/linuxDaniel Vetter authored
Stable tag for sphinx work Pull current state of the sphinx rework from Jonathan into drm-misc so that we can start converting gpu.tmpl. Signed-off-by: -
Daniel Vetter authored
Now that the core helpers support nonblocking atomic commits there's no need to invent that wheel separately (instead of fixing the bug in the atomic implementation of virtio, as it should have been done!). v2: Rebased on top of commit e7cf0963 Author: Gerd Hoffmann <kraxel@redhat.com> Date: Tue May 31 08:50:47 2016 +0200 virtio-gpu: add atomic_commit function Cc: Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
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Dave Gordon authored
During a hibernate/resume cycle, the whole system is reset, including the GuC and the doorbell hardware. Then the system is booted up, drivers are loaded, etc -- the GuC firmware may be loaded and set running at this point. But then, the booted kernel is replaced by the hibernated image, and this resumed kernel will also try to reload the GuC firmware (which will fail). To recover, we reset the GuC and try again (which should work). But this GuC reset doesn't also reset the doorbell hardware, so it can be left in a state inconsistent with that assumed by the driver and/or the newly-loaded GuC firmware. It would be better if the GuC reset also cleared all doorbell state, but that's not how the hardware currently works; also, the driver cannot directly reprogram the doorbell hardware (only the GuC can do that). So this patch cycles through all doorbells, assigning and releasing each in turn, so that all the doorbell hardware is left in a consistent state, no matter how it was programmed by the previously-running kernel and/or GuC firmware. v2: don't use kmap_atomic() now that client page 0 is kept mapped. Signed-off-by:
Dave Gordon <david.s.gordon@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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Dave Gordon authored
This version doesn't update the doorbell bitmap, as that will be done when the selected doorbell is associated with a client. The call is now slightly earlier, just on the general principle that potentially-failing operations should be done as early as possible, to eliminate late failures and simplify recovery. Suggested-by:
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Dave Gordon authored
This patch refactors the driver's handling and tracking of doorbells, in preparation for a later one which will resolve a suspend-resume issue. There are three resources to be managed: 1. Cachelines: a single line within the client-object's page 0 is snooped by doorbell hardware for writes from the host. 2. Doorbell registers: each defines one cacheline to be snooped. 3. Bitmap: tracks which doorbell registers are in use. The doorbell setup/teardown protocol starts with: 1. Pick a cacheline: select_doorbell_cacheline() 2. Find an available doorbell register: assign_doorbell() (These values are passed to the GuC via the shared context descriptor; this part of the sequence remains unchanged). 3. Update the bitmap to reflect registers-in-use 4. Prepare the cacheline for use by setting its status to ENABLED 5. Ask the GuC to program the doorbell to snoop the cacheline and of course teardown is very similar: 6. Set the cacheline to DISABLED 7. Ask the GuC to reprogram the doorbell to stop snooping 8. Record that the doorbell is not in use. Operations 6-8 (guc_disable_doorbell(), host2guc_release_doorbell(), and release_doorbell()) were called in sequence from guc_client_free(), but are now moved into the teardown phase of the common function. Steps 4-5 (guc_init_doorbell() and host2guc_allocate_doorbell()) were similarly done as sequential steps in guc_client_alloc(), but since it turns out that we don't need to be able to do them separately they're now collected into the setup phase of the common function. The only new code (and new capability) is the block tagged /* Update the GuC's idea of the doorbell ID */ i.e. we can now *change* the doorbell register used by an existing client, whereas previously it was set once for the entire lifetime of the client. We will use this new feature in the next patch. v2: Trivial independent fixes pushed ahead as separate patches. MUCH longer commit message :) [Tvrtko Ursulin] Signed-off-by: -
Dave Gordon authored
Just code movement, no actual change to the function. This is in preparation for the next patch, which will reorganise all the other doorbell code, but doesn't change this function. So let's shuffle it down near its caller rather than leaving it mixed in with the setup code. Unlike the doorbell management code, this function is somewhat time-critical, so putting it near its caller may even yield a tiny performance improvement. Signed-off-by:
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Dave Gordon authored
These registers are not actually writable by the CPU; only the GuC can actually program them. So let's not do writes that have no effect. Signed-off-by:
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Dave Gordon authored
Bitmap operators are overkill when touching only one bit. Signed-off-by:
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Dave Gordon authored
To properly verify the driver->doorbell->GuC functionality, validation needs to know how the driver has assigned the doorbell cache lines and registers, so make them visible through debugfs. v2: use kernel bitmap-printing format (%pb) rather than %x. Signed-off-by:
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arun.siluvery@linux.intel.com authored
This is a WA affecting pooled eu which is a bxt specific feature. Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Cc: Winiarski, Michal <michal.winiarski@intel.com> Cc: Zou, Nanhai <nanhai.zou@intel.com> Cc: Yang, Rong R <rong.r.yang@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Signed-off-by:
Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by:
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arun.siluvery@linux.intel.com authored
Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is advised to turn it off. But there is another HW issue in these parts (fused down 2x6 parts) before C0 that requires Pooled EU to be enabled as a workaround. In this case the pool configuration changes depending upon which subslice is disabled. This doesn't affect if the device has all 3 subslices enabled. Userspace need to know min no. of eus in a pool as it varies based on which subslice is disabled, this is not yet exported because userspace support is not available yet. Once the support is available this needs to be exported using getparam ioctls. v2: s/subslice_total/subslice_per_slice as it is a more logical field (Mika) Reviewed-by:
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arun.siluvery@linux.intel.com authored
This mode allows to assign EUs to pools which can process work collectively. The command to enable this mode should be issued as part of context initialization. The pooled mode is global, once enabled it has to stay the same across all contexts until HW reset hence this is sent in auxiliary golden context batch. Thanks to Mika for the preliminary review and comments. v2: explain why this is enabled in golden context, use feature flag while enabling the support (Chris) v3: Include only kernel support as userspace support is not available yet. User space clients need to know when the pooled EU feature is present and enabled on the hardware so that they can adapt work submissions. Create a new device info flag for this purpose. Set has_pooled_eu to true in the Broxton static device info - Broxton supports the feature in hardware and the driver will enable it by default. We need to add getparam ioctls to enable userspace to query availability of this feature and to retrieve min. no of eus in a pool but we will expose them once userspace support is available. Opensource users for this feature are mesa, libva and beignet. Beignet team is currently working on adding userspace support. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2) Cc: Winiarski, Michal <michal.winiarski@intel.com> Cc: Zou, Nanhai <nanhai.zou@intel.com> Cc: Yang, Rong R <rong.r.yang@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Armin Reese <armin.c.reese@intel.com> Cc: Tim Gore <tim.gore@intel.com> Signed-off-by:
Jeff McGee <jeff.mcgee@intel.com> Signed-off-by:
Michał Winiarski <michal.winiarski@intel.com> Signed-off-by:
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Wei Yongjun authored
Add the missing unlock before return from function i915_ppgtt_info() in the error handling case. Fixes: 1d2ac403(drm: Protect dev->filelist with its own mutex) Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by:
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Dave Airlie authored
Merge branch 'topic-arcpgu-sim' of https://github.com/foss-for-synopsys-dwc-arc-processors/linux into drm-next Add support for arcgpu on the sim platform. * 'topic-arcpgu-sim' of https://github.com/foss-for-synopsys-dwc-arc-processors/linux: ARC: [nsimosci] Enable ARC PGU on nSIM OSCI virtual platforms ARCv2: [vdk] Enable ARC PGU on HS38 VDK drm/arcpgu: Make ARC PGU usable on simulation platforms
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- 13 Jun, 2016 15 commits
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Gustavo Padovan authored
Replace the legacy drm_vblank_{on,off}() with the new helper functions. Signed-off-by:Gustavo Padovan <gustavo.padovan@collabora.co.uk> Acked-by:
Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by:
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Gustavo Padovan authored
We don't need to use &radeon_crtc->base there as crtc is available in the function. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Gustavo Padovan authored
We don't need to use &amdgpu_crtc->base there as crtc is available in the function. Signed-off-by:
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Gustavo Padovan authored
Replace the legacy drm_vblank_{on,off}() with the new helper functions. Signed-off-by: -
Gustavo Padovan authored
Replace the legacy drm_vblank_{on,off}() with the new helper functions. Signed-off-by: -
Gustavo Padovan authored
As they are not used anywhere outside drm_irq.c make them static. Signed-off-by:
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Gustavo Padovan authored
We don't have any user of this function anymore, let's remove it. Signed-off-by:
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Gustavo Padovan authored
We don't have any user of this function anymore, let's remove it. Signed-off-by:
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Gustavo Padovan authored
Replace the legacy drm_send_vblank_event(), drm_arm_vblank_event() and drm_vblank_{get,put}() with the new helper functions. v2: add crtc to nouveau_page_flip_state (comment from Mario Kleiner) Signed-off-by: -
Dave Gordon authored
There are four non-static functions in i915_guc_submission.c that take a 'dev' parameter. All are called only from GuC loader code, and can be easily converted to accept 'dev_priv' instead. Signed-off-by:
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Dave Gordon authored
Convert all static functions in i915_guc_submission.c that currently take a 'dev' pointer to take 'dev_priv' instead (there are three, guc_client_alloc(), guc_client_free(), and gem_allocate_guc_obj(). Signed-off-by:
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Imre Deak authored
We can check the power state of the PHY data and common lanes as reported by the PHY. Do this in case we need to debug problems where the PHY gets stuck in an unexpected state. Note that I only check these when the lanes are expected to be powered on purpose, since it's not clear at what point the PHY power/clock gates things. v2: - Don't report the encoder as disabled when the sanity check fails. (Ville) CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Imre Deak authored
Rename these remaining function prefixes to better align with the corresponding SKL functions. No functional change. Signed-off-by:
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Imre Deak authored
So far we configured a static lane latency optimization during driver loading/resuming. The specification changed at one point and now this configuration depends on the lane count, so move the configuration to modeset time accordingly. It's not clear when this lane configuration takes effect. The specification only requires that the programming is done before enabling the port. On CHV OTOH the lanes start to power up already right after enabling the PLL. To be safe preserve the current order and set things up already before enabling the PLL. v2: (Ander) - Simplify the optimization mask calculation. - Use the correct pipe_config always during the calculation instead of the bogus intel_crtc->config. CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95476Signed-off-by:
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Imre Deak authored
So far we depended on the HW to dynamically power down unused PHYs and so we enabled them manually once during driver loading/resuming. There are indications however that we can achieve better power savings by manual powering toggling. So make the PHY enabling/disabling to happen on-demand whenever we need either the corresponding AUX or port functionality. CHV does this already by enabling the PHY along the corresponding PHY common lane power wells there, do the same on BXT by adding virtual power wells for the same purpose. Also sanity check the common lane power down ack signal from the PHY. Do this only when the PHY is enabled, since it's not clear at what point the HW power/clock gates things. While at it rename broxton_ prefix to bxt_ in related function names to better align with the SKL code. Signed-off-by:
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