- 23 Nov, 2019 2 commits
-
-
Thomas Bogendoerfer authored
PROM only enables ethernet PHY on first Origin 200 module, so we must do it ourselves for the second module. Signed-off-by:
Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by:
Paul Burton <paulburton@kernel.org> Cc: Jakub Kicinski <jakub.kicinski@netronome.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: Lee Jones <lee.jones@linaro.org> Cc: David S. Miller <davem@davemloft.net> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: netdev@vger.kernel.org Cc: linux-rtc@vger.kernel.org Cc: linux-serial@vger.kernel.org
-
Thomas Bogendoerfer authored
Generation of fake subdevice ID had vendor and device ID swapped. Signed-off-by:
-
- 22 Nov, 2019 6 commits
-
-
Zhou Yanjie authored
JZ4760/JZ4770/JZ4775/X1000/X1500 has an abandoned huge page tlb, this mode is not compatible with the MIPS standard, it will cause tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S) when starting the init process. write 0xa9000000 to cp0 register 5 sel 4 to disable this function to prevent getting stuck. Confirmed by Ingenic, this operation will not adversely affect processors without HPTLB function. Signed-off-by:
Zhou Yanjie <zhouyanjie@zoho.com> Acked-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
-
Thomas Bogendoerfer authored
When changing interrupt affinity remember the possible changed nasid, otherwise an interrupt deactivate/activate sequence will incorrectly setup interrupt. Fixes: e6308b6d ("MIPS: SGI-IP27: abstract chipset irq from bridge") Signed-off-by:
-
Thomas Bogendoerfer authored
If number of CPUs are limited by the kernel commandline parameter nr_cpus assignment of interrupts accourding to numa rules might not be possibe. As a fallback use one of the online CPUs as interrupt destination. Fixes: 69a07a41 ("MIPS: SGI-IP27: rework HUB interrupts") Signed-off-by:
-
Mike Rapoport authored
Implement primitives necessary for the 4th level folding, add walks of p4d level where appropriate, replace 5leve-fixup.h with pgtable-nop4d.h and drop usage of __ARCH_USE_5LEVEL_HACK. Signed-off-by:
Mike Rapoport <rppt@linux.ibm.com> Signed-off-by:
-
Mike Rapoport authored
The __pXd_offset() macros are identical to the pXd_index() macros and there is no point to keep both of them. All architectures define and use pXd_index() so let's keep only those to make mips consistent with the rest of the kernel. Signed-off-by:
-
Mike Rapoport authored
With CONFIG_MIPS_VA_BITS_48=y the build fails miserably: CC arch/mips/kernel/asm-offsets.s In file included from arch/mips/include/asm/pgtable.h:644, from include/linux/mm.h:99, from arch/mips/kernel/asm-offsets.c:15: include/asm-generic/pgtable.h:16:2: error: #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED ^~~~~ include/asm-generic/pgtable.h:390:28: error: unknown type name 'p4d_t'; did you mean 'pmd_t'? static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) ^~~~~ pmd_t [ ... more such errors ... ] scripts/Makefile.build:99: recipe for target 'arch/mips/kernel/asm-offsets.s' failed make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1 This happens because when CONFIG_MIPS_VA_BITS_48 enables 4th level of the page tables, but neither pgtable-nop4d.h nor 5level-fixup.h are included to cope with the 5th level. Replace #ifdef conditions around includes of the pgtable-nop{m,u}d.h with explicit CONFIG_PGTABLE_LEVELS and add include of 5level-fixup.h for the case when CONFIG_PGTABLE_LEVELS==4 Signed-off-by:
-
- 11 Nov, 2019 9 commits
-
-
Paul Burton authored
The FPU_STAT_CREATE_EX() macro used 114 times in debugfs_fpuemu() declares a 32 byte char array to hold the name of a debugfs file. Since each use of the macro declares a new char array out of the scope of all the other uses, we end up with an unnecessarily large stack frame of 3648 bytes (ie. 114*32) plus the size of 2 pointers (fpuemu_debugfs_base_dir & fpuemu_debugfs_inst_dir). This is enough to trigger the frame size warnings from GCC in common configurations. Avoid the unnecessary stack bloat by using a single name char array which each usage of FPU_STAT_CREATE_EX() will reinitialize via the strcpy() in adjust_instruction_counter_name(). Signed-off-by:
kbuild test robot <lkp@intel.com> URL: https://lore.kernel.org/linux-mips/201911090929.xvXYuHUz%25lkp@intel.com/
-
Alexey Khoroshilov authored
Add ARCH_HAS_KCOV and HAVE_GCC_PLUGINS to MIPS config. Disable instrumentation of vdso to avoid build failure. Signed-off-by:
Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by:
-
Jiaxun Yang authored
setup_pcimap is used to setup address windows for Loongson-3 built-in PCI-X controller, but this function is never been used in the real world and lack of support in kernel. Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
-
Jiaxun Yang authored
early_printk.c is doing the same with early_printk_8250. Remove duplicated code. Signed-off-by:
-
Jiaxun Yang authored
CPU_SUPPORTS_UNCACHED_ACCELERATED was introduced when kernel can't handle writecombine remap well. Nowadays drivers can try writecombine remap by themselves so this function is nolonger needed. Signed-off-by:
-
Jiaxun Yang authored
All of Loongson firmwares are passing boot cmdline/env in the manner of YAMON/PMON. Thus we can remove duplicated cmdline initialize code and convert to generic fw method. Signed-off-by:
-
Jiaxun Yang authored
There is no code still using pmon callvectors. Signed-off-by:
-
Huacai Chen authored
There are mixed LOONGSON3/LOONGSON64 usages in recently changes, let's establish some rules: 1, In Kconfig symbols, we only use CPU_LOONGSON64, MACH_LOONGSON64 and SYS_HAS_CPU_LOONGSON64, all other derived symbols use "LOONGSON3" since they all not widely-used symbols and sometimes not suitable for all 64-bit Loongson processors. E.g., we use symbols LOONGSON3_ENHANCEMENT, CPU_LOONGSON3_WORKAROUNDS, etc. 2, Hide GSx64/GSx64E in Kconfig title since it is not useful for general users. However, in the full description we use a more detailed manner. E.g., GS264/GS464/GS464E/GS464V. All Kconfig titles and descriptions of Loongson processors and machines have also been updated in this patch for consistency. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
-
Huacai Chen authored
Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future, newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32 will make the naming style more unified. Signed-off-by:
-
- 04 Nov, 2019 1 commit
-
-
Tiezhu Yang authored
When call function hwmon_device_register failed, use the actual return value instead of always -ENOMEM. Fixes: 64f09aa9 ("MIPS: Loongson-3: Add CPU Hwmon platform driver") Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by:
-
- 01 Nov, 2019 10 commits
-
-
Thomas Bogendoerfer authored
This changeset adds support for SGI Octane/Octane2 workstations. Signed-off-by:
-
Thomas Bogendoerfer authored
All platforms using pci-xtalk-bridge can share common phys_to_dma/ dma_to_phys function. So we move it form ip27 specific file to pci-xtalk-bridge.c Signed-off-by:
-
Paul Burton authored
Pull in mips-fixes primarily to gain build fixes in order to allow better testing of mips-next. A few MIPS fixes: - Fix VDSO time-related function behavior for systems where we need to fall back to syscalls, but were instead returning bogus results. - A fix to TLB exception handlers for Cavium Octeon systems where they would inadvertently clobber the $1/$at register. - A build fix for bcm63xx configurations. - Switch to using my @kernel.org email address. Signed-off-by: -
Tiezhu Yang authored
When I update kernel with loongson3_defconfig based on the Loongson 3A3000 platform, then using dmesg command to show kernel ring buffer, the initial kernel messages have disappeared due to the log buffer is too small, it is better to change the kernel log buffer size from 16KB to 128KB which is enough to save the boot messages. Since the default LOG_BUF_SHIFT value is 17, the default kernel log buffer size is 128KB, just delete the CONFIG_LOG_BUF_SHIFT line. Signed-off-by:
-
Thomas Bogendoerfer authored
MAX_COMPACT_NODE is a leftover from the compact node implementation, which is removed now. Use MAX_NUMNODES instead. Signed-off-by:
-
Paul Menzel authored
Fixes: 5b3b1688 ("MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.") Signed-off-by:
Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by:
-
Jiaxun Yang authored
Current Loongson-3 code can share among all Loongson64 processors. Signed-off-by:
-
Jiaxun Yang authored
Clean up legacy code after stripping out Loongson2ef code. Signed-off-by:
-
Jiaxun Yang authored
Remove unrelevent macros, defines and codes from loongson2ef mach. Also rename some defines to match new naming. Signed-off-by:
-
Jiaxun Yang authored
As later model of GSx64 family processors including 2-series-soc have similar design with initial loongson3a while loongson2e/f seems less identical, we separate loongson2e/f support code out of mach-loongson64 to make our life easier. This patch contains mostly file moving works. Signed-off-by:
-
- 31 Oct, 2019 1 commit
-
-
Jiaxun Yang authored
CPU_LOONGSON2 -> CPU_LOONGSON2EF CPU_LOONGSON3 -> CPU_LOONGSON64 As newer loongson-2 products (2G/2H/2K1000) can share kernel implementation with loongson-3 while 2E/2F are less similar with other LOONGSON64 products. Signed-off-by:
-
- 24 Oct, 2019 9 commits
-
-
Thomas Bogendoerfer authored
asm/sgi/sgi.h is unused, time to remove it. Signed-off-by:
-
Paul Burton authored
build_restore_pagemask() will restore the value of register $1/$at when its restore_scratch argument is non-zero, and aims to do so by filling a branch delay slot. Commit 0b24cae4 ("MIPS: Add missing EHB in mtc0 -> mfc0 sequence.") added an EHB instruction (Execution Hazard Barrier) prior to restoring $1 from a KScratch register, in order to resolve a hazard that can result in stale values of the KScratch register being observed. In particular, P-class CPUs from MIPS with out of order execution pipelines such as the P5600 & P6600 are affected. Unfortunately this EHB instruction was inserted in the branch delay slot causing the MFC0 instruction which performs the restoration to no longer execute along with the branch. The result is that the $1 register isn't actually restored, ie. the TLB refill exception handler clobbers it - which is exactly the problem the EHB is meant to avoid for the P-class CPUs. Similarly build_get_pgd_vmalloc() will restore the value of $1/$at when its mode argument equals refill_scratch, and suffers from the same problem. Fix this by in both cases moving the EHB earlier in the emitted code. There's no reason it needs to immediately precede the MFC0 - it simply needs to be between the MTC0 & MFC0. This bug only affects Cavium Octeon systems which use build_fast_tlb_refill_handler(). Signed-off-by:
-
Thomas Bogendoerfer authored
IP27 uses ARC prom only for parsing prom arguments and has a hack for IP27 to make the ARC code behave. By introducing config symbol ARC_CMDLINE_ONLY IP27 only drags in ARC cmdline parsing and does everything else in IP27 specific code. Signed-off-by:
-
Thomas Bogendoerfer authored
prom_argc and prom_argv are only used by prom_init_cmdline(), so we could pass them directly as function argument. Signed-off-by:
-
Thomas Bogendoerfer authored
remove unused _prom_envp and prom_argc macro. Signed-off-by:
-
Thomas Bogendoerfer authored
Calling register_smp_ops() in plat_mem_setup() is still early enough. So by doing this we could remove the ugly #ifdef CONFIG_SGI_IP27 in fw/arc/init.c. Signed-off-by:
-
Thomas Bogendoerfer authored
IP27 code has a few externs distributed over .c files. Collect them together into one commcon header file. Signed-off-by:
-
Jonas Gorski authored
The vectors span more than one byte, so mark them as arrays. Fixes the following build error when building when using GCC 8.3: In file included from ./include/linux/string.h:19, from ./include/linux/bitmap.h:9, from ./include/linux/cpumask.h:12, from ./arch/mips/include/asm/processor.h:15, from ./arch/mips/include/asm/thread_info.h:16, from ./include/linux/thread_info.h:38, from ./include/asm-generic/preempt.h:5, from ./arch/mips/include/generated/asm/preempt.h:1, from ./include/linux/preempt.h:81, from ./include/linux/spinlock.h:51, from ./include/linux/mmzone.h:8, from ./include/linux/bootmem.h:8, from arch/mips/bcm63xx/prom.c:10: arch/mips/bcm63xx/prom.c: In function 'prom_init': ./arch/mips/include/asm/string.h:162:11: error: '__builtin_memcpy' forming offset [2, 32] is out of the bounds [0, 1] of object 'bmips_smp_movevec' with type 'char' [-Werror=array-bounds] __ret = __builtin_memcpy((dst), (src), __len); \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/bcm63xx/prom.c:97:3: note: in expansion of macro 'memcpy' memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); ^~~~~~ In file included from arch/mips/bcm63xx/prom.c:14: ./arch/mips/include/asm/bmips.h:80:13: note: 'bmips_smp_movevec' declared here extern char bmips_smp_movevec; Fixes: 18a1eef9 ("MIPS: BMIPS: Introduce bmips.h") Signed-off-by:Jonas Gorski <jonas.gorski@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
-
Rikard Falkeborn authored
Arguments are supposed to be ordered high then low. Fixes: 6a6f9b7d ("MIPS: Loongson: Add CFUCFG&CSR support") Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by:
-
- 18 Oct, 2019 2 commits
-
-
Vincenzo Frascino authored
On some MIPS variants (e.g. MIPS r1), vDSO clock_mode is set to VDSO_CLOCK_NONE. When VDSO_CLOCK_NONE is set the expected kernel behavior is to fallback on syscalls. To do that the generic vDSO library expects UULONG_MAX as return value of __arch_get_hw_counter(). Fix __arch_get_hw_counter() on MIPS defining a __VDSO_USE_SYSCALL case that addressed the described scenario. Reported-by:
Maxime Bizon <mbizon@freebox.fr> Signed-off-by:
Vincenzo Frascino <vincenzo.frascino@arm.com> Tested-by:
-
Paul Burton authored
Switch to using my paulburton@kernel.org email address in order to avoid subject mangling that's being imposed on my previous address. Signed-off-by:
Paul Burton <paul.burton@mips.com> Signed-off-by:
-
