- 08 Nov, 2013 40 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Removes the need for special handling of messages in init paths. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
We don't necessarily have fbcon on all devices these days. Fixes suspend on (at least) Quadro NVS 450. Signed-off-by: -
Ben Skeggs authored
Matches the nv94-nvc0 commit with the same title. Doesn't fix a reported issue, but NVIDIA use this ordering here too, so let's do it just in case. Signed-off-by: -
Ben Skeggs authored
Fixes link training issues on some boards. Signed-off-by: -
Ben Skeggs authored
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Martin Peres authored
This patch adds a way to define a custom delay when scanning for i2c devices because the adt7473 sometimes doesn't like the default bitbanging udelay. Signed-off-by:
Martin Peres <martin.peres@labri.fr> Signed-off-by:
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Ilia Mirkin authored
Certain combinations of hardware can't actually support the maximum detected speed. Add a quirk list that lists pairs of hostbridge/chip pci ids and the mode that they should work with. See https://bugs.freedesktop.org/show_bug.cgi?id=20341Reported-by:
Jason Detring <detringj@gmail.com> Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
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Ben Skeggs authored
Reported-by:
Andy Ritger <aritger@nvidia.com> Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
These will diverge further in the future. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This is what NVIDIA do on these chipsets, let's hope it works around the reported MSI failures for us on NV86. v2: updated to include G92, as per information provided by NVIDIA. Signed-off-by: -
Ben Skeggs authored
v2. updated to cover GF104, as per information provided by NVIDIA. Reported-by:
Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This looks to be what NVIDIA do pretty much everywhere, since forever. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
This way we can catch it with debugging on for PMC subdev. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Martin Peres authored
This is safe because ptherm hasn't been configured yet and will be a little further down the initialization path. Ptherm should be safe regarding to runtime reconfiguration. v2: - do not limit this patch to nv84-a3 and make it nv84+ v3: - move the ack to fini() - disable IRQs on fini() - silently ignore un-requested IRQs Signed-off-by:
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Ilia Mirkin authored
NV31 has different config bits than NV40+ do. Also fix the DMA_IMAGE VRAM-only setting to check the right bits. Signed-off-by:
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Ilia Mirkin authored
This makes nv31+ able to actually perform the nv_call, since previously the inst was not available. Signed-off-by:
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Ilia Mirkin authored
Since nv40 only covers pre-nv44 now, it can use the nv31-provided functions. Signed-off-by:
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Ilia Mirkin authored
The nv31/nv40 impls are actually fairly nv44-specific, since they assume the presence of the instance register/context switching. Create a copy before nv31/nv40 get fixed. Signed-off-by:
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Ilia Mirkin authored
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Ilia Mirkin authored
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Ilia Mirkin authored
NV1A is numerically higher than NV17 but generationally lower. Use the new card type to help disambiguate. Signed-off-by:
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