- 14 Jan, 2019 40 commits
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Felix Kuehling authored
ifdef x86_64 specific code. Allow enabling CONFIG_HSA_AMD on ARM64. v2: Fixed a compiler warning due to an unused variable CC: Mark Nutter <Mark.Nutter@arm.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Tested-by:
Mark Nutter <Mark.Nutter@arm.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
To deal with situations like kexec or GPU VM passthrough where the device may have been used previously without a proper GPU reset between. v2: rebase bug: https://bugs.freedesktop.org/show_bug.cgi?id=108585 bug: https://bugs.freedesktop.org/show_bug.cgi?id=108754Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Alex Deucher authored
SOC15 chips require a reset if the driver was previously loaded because the PSP can only be loaded once between each reset. v2: rebase, handle multiple asic funcs Reviewed-by:
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Alex Deucher authored
VI chips require a reset if the driver was previously loaded because the SMU can only be loaded once between each reset. v2: rebase Reviewed-by:
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Alex Deucher authored
CIK chips require a reset if the driver was previously loaded because the SMU can only be loaded once between each reset. v2: rebase Reviewed-by:
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Alex Deucher authored
SI chips don't require a reset on reload due to the nature of the SMU on them. v2: rebase Reviewed-by:
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Alex Deucher authored
Used to determine if we need to reset the asic on init due to the driver having been previously loaded or not shutdown cleanly. E.g., kexec or VM passthrough. v2: rebase Reviewed-by:
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Alex Deucher authored
Expose sclk (gfx clock) and mclk (memory clock) via hwmon compatible interface. hwmon does not actually formally specify a frequency type attribute, but these are compatible with the format of the other attributes exposed via hwmon. Units are hertz. freq1_input - GPU gfx/compute clock in hertz freq2_input - GPU memory clock in hertz (dGPU only) Reviewed-by:
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Kent Russell authored
Add a sysfs file that reports the number of bytes transmitted and received in the last second. This can be used to approximate the PCIe bandwidth usage over the last second. v2: Clarify use of mps as estimation of bandwidth v3: Don't make the file on APUs v4: Early exit for APUs in the read function, change output to display "packets-received packets-sent mps" v5: fix missing header for si (Alex) Signed-off-by:Kent Russell <kent.russell@amd.com> Reviewed-by:
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Kent Russell authored
We need these offsets for PCIE perf counters, so include them as well as the the previously-used defines from the nbio_*.c files v2: Return NBIF definitions back to previous files Signed-off-by:
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Tom St Denis authored
v2: Move locks around in other functions so that this function can stand on its own. Also only hold the hive specific lock for add/remove device instead of the driver global lock so you can't add/remove devices in parallel from one hive. v3: add reset_lock Acked-by: Shaoyun.liu < Shaoyun.liu@amd.com> Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Leo Li authored
[Why] To reduce indent in dm_update_crtcs, and to make it operate on single instances. [How] Move iteration of plane states into atomic_check. No functional change is intended. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Leo Li authored
[Why] To reduce indentation of dm_update_planes, and to make it operate on single plane instances. [How] Move iteration of plane states into atomic_check. No functional change is intended. Signed-off-by:
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shaoyunl authored
Add message print out and return -EINVAL when driver can not get valid hive from hive arrary on xgmi configuration Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
get_fw_type and prep_cmd_buf should be common interface instead of IP specific ones Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL was renamed to GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL in latest psp_gfx_if drop Signed-off-by:
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Gustavo A. R. Silva authored
Fix boolean expressions by using logical AND operator '&&' instead of bitwise operator '&'. This issue was detected with the help of Coccinelle. Fixes: 9a4b7d4c ("drm/amdgpu: Add vm context module param") Reviewed-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Emily Deng authored
When init fail, send rel init, req_fini and rel_fini to host for the finishing routine. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Gustavo A. R. Silva authored
Fix boolean expression by using logical AND operator '&&' instead of bitwise operator '&'. This issue was detected with the help of Coccinelle. Fixes: 6d04ee9d ("drm/amd/display: Restructuring and cleaning up DML") Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Christian König authored
Note if this is a retry fault or not and cleanup the message a bit. Signed-off-by:
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wentalou authored
distinguish ip_reinit_early_sriov and ip_reinit_late_sriov by different log RE-INIT-early and RE-INIT-late Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Hardware support for Delta Color Compression (DCC) decompression is available in DC for GFX9 but there's no way for userspace to enable the feature. Enabling the feature can provide improved GFX performance and power savings in many situations. [How] The GFX9 DCC parameters are passed to amdgpu_dm from AMDGPU via the amdgpu_bo tiling_flags. The plane capability is queried and the parameters are set accordingly. The DCC address is given via a 256 byte aligned offset on the framebuffer address. The DCC address is updated whenever the buffer address changes. Signed-off-by:
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Christian König authored
To distinct on which IH ring an IV was found. Signed-off-by:
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Christian König authored
When an ring buffer overflow happens the appropriate bit is set in the WPTR register which is also written back to memory. But clearing the bit in the WPTR doesn't trigger another memory writeback. So what can happen is that we end up processing the buffer overflow over and over again because the bit is never cleared. Resulting in a random system lockup because of an infinite loop in an interrupt handler. This is 100% reproducible on Vega10, but it's most likely an issue we have in the driver over all generations all the way back to radeon. v2: rebase Signed-off-by:
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Christian König authored
Calculate all the addresses and pointers in amdgpu_ih.c Signed-off-by:
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Christian König authored
Let's start to support multiple rings. v2: decode IV is needed as well Signed-off-by:
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Prike Liang authored
As the PG was setted by each IP block durinng IP early init thus remove the unused phm_enable_clock_power_gatings related funcs. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Shirish S authored
Initializing structures with { } is known to be problematic since it doesn't necessararily initialize all bytes, in case of padding, causing random failures when structures are memcmp(). This patch fixes the structure initialisation related compiler error by memset(). V2: rectified missing piece in coding Signed-off-by:Shirish S <shirish.s@amd.com> Reviewed-by:
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Ken Chalmers authored
[Why] 32-bit builds break when doing 64-bit division directly. [How] Use the div_u64() function instead to perform the division. Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-December/201008.htmlSigned-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Shirish S authored
Initializing structures with { } is known to be problematic since it doesn't necessararily initialize all bytes, in case of padding, causing random failures when structures are memcmp(). This patch fixes the structure initialisation related compiler error by memset. Signed-off-by: -
Ken Chalmers authored
[Why] For more informative debugging. [How] Add timing generator and PLL ids to output, to make it clear which pixel clock is being set. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Brajeswar Ghosh authored
Remove reg_helper.h which is included more than once Signed-off-by:
Brajeswar Ghosh <brajeswar.linux@gmail.com> Signed-off-by:
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Brajeswar Ghosh authored
Remove custom_float.h which is included more than once Signed-off-by:
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Brajeswar Ghosh authored
Remove custom_float.h which is included more than once Acked-by:
Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by:
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Colin Ian King authored
There are several variables that are defined and never used and hence can be removed. Remove them. Cleans up clang -Wunused-const-variable warnings: warning: ‘dvi_hdmi_dongle_signature_str’ defined but not used warning: ‘dce11_one_lpt_channel_max_resolution’ defined but not used warning: ‘ddc_hw_status_addr’ defined but not used Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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David Francis authored
[Why] The function dc_commit_updates_for_stream had a parameter called plane_states. It was never used. It was getting in the way of some cleanup work [How] Remove it Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
This will allow us to program dscclk to required value Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Fatemeh Darbehani authored
[Why] PPLib has impelemented the new pp_smu interface [How] Use the new functions if available instead of the old interface 'set_display_requirement' and 'dcn1_pplib_apply_display_requirements'. Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
Su Chung <Su.Chung@amd.com> Signed-off-by:
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Steven Chiu authored
Signed-off-by:
Steven Chiu <steven.chiu@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Leo Li authored
[Why] When XGMI is enabled, we need to adjust the dprefclk according to the WAFL link's spread spectrum info. This is for VG20 (DCE121) only. [How] dce_clk_mgr already stores SS info, currently being used by audio clock. Therefore, patch the clk_mgr's SS info with the xGMI SS info, if xGMI is enabled. For display clock, adjust it during dce12_update_clocks() before calling set_clock(). Since we rely on a mmhub register to reliably determine if xGMI is enabled, the patching step needs to happen after resource_construct() has initialized the hardware sequencer. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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