Commit dca00ef2 authored by Mark Florisson's avatar Mark Florisson

memslice support for cython.parallel

parent 55fa9f1f
......@@ -6174,9 +6174,9 @@ class ParallelStatNode(StatNode, ParallelNode):
# By default all variables should have the same values as if
# executed sequentially
lastprivate = True
self.propagate_var_privatization(entry, op, lastprivate)
self.propagate_var_privatization(entry, pos, op, lastprivate)
def propagate_var_privatization(self, entry, op, lastprivate):
def propagate_var_privatization(self, entry, pos, op, lastprivate):
"""
Propagate the sharing attributes of a variable. If the privatization is
determined by a parent scope, done propagate further.
......@@ -6230,6 +6230,11 @@ class ParallelStatNode(StatNode, ParallelNode):
# sum and j are undefined here
"""
self.privates[entry] = (op, lastprivate)
if entry.type.is_memoryviewslice:
error(pos, "Memoryview slices can only be shared in parallel sections")
return
if self.is_prange:
if not self.is_parallel and entry not in self.parent.assignments:
# Parent is a parallel with block
......@@ -6240,7 +6245,7 @@ class ParallelStatNode(StatNode, ParallelNode):
# We don't need to propagate privates, only reductions and
# lastprivates
if parent and (op or lastprivate):
parent.propagate_var_privatization(entry, op, lastprivate)
parent.propagate_var_privatization(entry, pos, op, lastprivate)
def _allocate_closure_temp(self, code, entry):
"""
......
......@@ -1037,7 +1037,8 @@ class ParallelRangeTransform(CythonTransform, SkipDeclarations):
directive = directive.rstrip('.')
cls = self.directive_to_node.get(directive)
if cls is None:
if cls is None and not (self.namenode_is_cython_module and
self.parallel_directive[0] != 'parallel'):
error(node.pos, "Invalid directive: %s" % directive)
self.namenode_is_cython_module = False
......
......@@ -515,6 +515,9 @@ class MemoryViewSliceType(PyrexType):
def specialization_suffix(self):
return "%s_%s" % (self.axes_to_name(), self.dtype_name)
def can_coerce_to_pyobject(self, env):
return True
#def global_init_code(self, entry, code):
# code.putln("%s.data = NULL;" % entry.cname)
# code.putln("%s.memview = NULL;" % entry.cname)
......
......@@ -126,6 +126,10 @@ with nogil, parallel.parallel():
for i in parallel.prange(10):
pass
cdef int[:] dst, src = object()
for i in prange(10, nogil=True):
dst = src
_ERRORS = u"""
e_cython_parallel.pyx:3:8: cython.parallel.parallel is not a module
e_cython_parallel.pyx:4:0: No such directive: cython.parallel.something
......@@ -156,4 +160,5 @@ e_cython_parallel.pyx:110:7: local variable 'i' referenced before assignment
e_cython_parallel.pyx:119:17: Cannot read reduction variable in loop body
e_cython_parallel.pyx:121:20: stop argument must be numeric
e_cython_parallel.pyx:121:19: prange() can only be used without the GIL
e_cython_parallel.pyx:131:8: Memoryview slices can only be shared in parallel sections
"""
......@@ -6,6 +6,9 @@ from __future__ import unicode_literals
cimport cython
from cython cimport view
from cython.parallel cimport prange
print cython.array
import sys
import re
......@@ -1366,8 +1369,7 @@ def test_nogil_oob1():
print e.args[0]
try:
# Enable when the nogil exception propagation fix is merged
#with nogil:
with nogil:
nogil_oob(a)
except IndexError, e:
print e.args[0]
......@@ -1426,3 +1428,32 @@ def test_convert_slicenode_to_indexnode():
a = a[2:4]
print a[0]
@testcase
@cython.boundscheck(False)
@cython.wraparound(False)
def test_memslice_prange(arg):
"""
>>> test_memslice_prange(IntMockBuffer("A", range(400), shape=(20, 4, 5)))
acquired A
released A
>>> test_memslice_prange(IntMockBuffer("A", range(200), shape=(100, 2, 1)))
acquired A
released A
"""
cdef int[:, :, :] src, dst
src = arg
dst = cython.array((<object> src).shape, sizeof(int), format="i")
cdef int i, j, k
for i in prange(src.shape[0], nogil=True):
for j in range(src.shape[1]):
for k in range(src.shape[2]):
dst[i, j, k] = src[i, j, k]
for i in range(src.shape[0]):
for j in range(src.shape[1]):
for k in range(src.shape[2]):
assert src[i, j, k] == dst[i, j, k], (src[i, j, k] == dst[i, j, k])
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