cmd/internal/obj/arm64: support logical instructions targeting RSP

Logical instructions can have RSP as its destination. Support it.

Note that the two-operand form, like "AND $1, RSP", which is
equivalent to the three-operand form "AND $1, RSP, RSP", is
invalid, because the source register is not allowed to be RSP.

Also note that instructions that set the conditional flags, like
ANDS, cannot target RSP. Because of this, we split out the optab
entries of AND et al. and ANDS et al.

Merge the optab entries of BIC et al. to AND et al., because they
are same.

Fixes #24332.

Change-Id: I3584d6f2e7cea98a659a1ed9fdf67c353e090637
Reviewed-on: https://go-review.googlesource.com/100217
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>

src/cmd/asm/internal/asm/testdata/arm64.s

@@ -101,6 +101,13 @@ TEXT	foo(SB), DUPOK|NOSPLIT, $-8
 	EOR	$(1<<63), R1   // EOR	$-9223372036854775808, R1 // 210041d2
 	EOR	$(1<<63-1), R1 // EOR	$9223372036854775807, R1  // 21f840d2
 
+	AND	$8, R0, RSP // 1f007d92
+	ORR	$8, R0, RSP // 1f007db2
+	EOR	$8, R0, RSP // 1f007dd2
+	BIC	$8, R0, RSP // 1ff87c92
+	ORN	$8, R0, RSP // 1ff87cb2
+	EON	$8, R0, RSP // 1ff87cd2
+
 //
 // CLS
 //

src/cmd/asm/internal/asm/testdata/arm64error.s

@@ -50,4 +50,7 @@ TEXT errors(SB),$0
 	VFMLS	V1.H4, V12.H4, V3.H4        // ERROR "invalid arrangement"
 	VFMLS	V1.H8, V12.H8, V3.H8        // ERROR "invalid arrangement"
 	VFMLS	V1.H4, V12.H4, V3.H4        // ERROR "invalid arrangement"
+
+	AND	$1, RSP                     // ERROR "illegal combination"
+	ANDS	$1, R0, RSP                 // ERROR "illegal combination"
 	RET

src/cmd/internal/obj/arm64/asm7.go

@@ -211,28 +211,28 @@ var optab = []Optab{
 	/* logical operations */
 	{AAND, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
 	{AAND, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
-	{ABIC, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
-	{ABIC, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
-	{AAND, C_MBCON, C_REG, C_REG, 53, 4, 0, 0, 0},
+	{AANDS, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
+	{AANDS, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
+	{AAND, C_MBCON, C_REG, C_RSP, 53, 4, 0, 0, 0},
 	{AAND, C_MBCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
-	{ABIC, C_MBCON, C_REG, C_REG, 53, 4, 0, 0, 0},
-	{ABIC, C_MBCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
-	{AAND, C_BITCON, C_REG, C_REG, 53, 4, 0, 0, 0},
+	{AANDS, C_MBCON, C_REG, C_REG, 53, 4, 0, 0, 0},
+	{AANDS, C_MBCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
+	{AAND, C_BITCON, C_REG, C_RSP, 53, 4, 0, 0, 0},
 	{AAND, C_BITCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
-	{ABIC, C_BITCON, C_REG, C_REG, 53, 4, 0, 0, 0},
-	{ABIC, C_BITCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
-	{AAND, C_MOVCON, C_REG, C_REG, 62, 8, 0, 0, 0},
+	{AANDS, C_BITCON, C_REG, C_REG, 53, 4, 0, 0, 0},
+	{AANDS, C_BITCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
+	{AAND, C_MOVCON, C_REG, C_RSP, 62, 8, 0, 0, 0},
 	{AAND, C_MOVCON, C_NONE, C_REG, 62, 8, 0, 0, 0},
-	{ABIC, C_MOVCON, C_REG, C_REG, 62, 8, 0, 0, 0},
-	{ABIC, C_MOVCON, C_NONE, C_REG, 62, 8, 0, 0, 0},
-	{AAND, C_VCON, C_REG, C_REG, 28, 8, 0, LFROM, 0},
+	{AANDS, C_MOVCON, C_REG, C_REG, 62, 8, 0, 0, 0},
+	{AANDS, C_MOVCON, C_NONE, C_REG, 62, 8, 0, 0, 0},
+	{AAND, C_VCON, C_REG, C_RSP, 28, 8, 0, LFROM, 0},
 	{AAND, C_VCON, C_NONE, C_REG, 28, 8, 0, LFROM, 0},
-	{ABIC, C_VCON, C_REG, C_REG, 28, 8, 0, LFROM, 0},
-	{ABIC, C_VCON, C_NONE, C_REG, 28, 8, 0, LFROM, 0},
+	{AANDS, C_VCON, C_REG, C_REG, 28, 8, 0, LFROM, 0},
+	{AANDS, C_VCON, C_NONE, C_REG, 28, 8, 0, LFROM, 0},
 	{AAND, C_SHIFT, C_REG, C_REG, 3, 4, 0, 0, 0},
 	{AAND, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
-	{ABIC, C_SHIFT, C_REG, C_REG, 3, 4, 0, 0, 0},
-	{ABIC, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
+	{AANDS, C_SHIFT, C_REG, C_REG, 3, 4, 0, 0, 0},
+	{AANDS, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
 	{AMOVD, C_RSP, C_NONE, C_RSP, 24, 4, 0, 0, 0},
 	{AMVN, C_REG, C_NONE, C_REG, 24, 4, 0, 0, 0},
 	{AMOVB, C_REG, C_NONE, C_REG, 45, 4, 0, 0, 0},
@@ -1729,25 +1729,23 @@ func buildop(ctxt *obj.Link) {
 			oprangeset(ASUBSW, t)
 
 		case AAND: /* logical immediate, logical shifted register */
-			oprangeset(AANDS, t)
-
-			oprangeset(AANDSW, t)
 			oprangeset(AANDW, t)
 			oprangeset(AEOR, t)
 			oprangeset(AEORW, t)
 			oprangeset(AORR, t)
 			oprangeset(AORRW, t)
-
-		case ABIC: /* only logical shifted register */
-			oprangeset(ABICS, t)
-
-			oprangeset(ABICSW, t)
+			oprangeset(ABIC, t)
 			oprangeset(ABICW, t)
 			oprangeset(AEON, t)
 			oprangeset(AEONW, t)
 			oprangeset(AORN, t)
 			oprangeset(AORNW, t)
 
+		case AANDS: /* logical immediate, logical shifted register, set flags, cannot target RSP */
+			oprangeset(AANDSW, t)
+			oprangeset(ABICS, t)
+			oprangeset(ABICSW, t)
+
 		case ANEG:
 			oprangeset(ANEGS, t)
 			oprangeset(ANEGSW, t)