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Commit 6f4a4585 authored by Dave Cheney's avatar Dave Cheney
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cmd/internal/obj/mips: standardize on sys.MIPS and sys.MIPS64 constants 

CL 38446 introduced the use of the sys.ArchFamily type into the
cmd/internal/obj/mips package and redefined the mips.Mips32 and
mips.Mips64 constants in terms of their sys.ArchFamily counterparts.
This CL removes these local declarations and consolidates on sys.MIPS
and sys.MIPS64 respectively.

Change-Id: Id7aab6c7fd0de42ff43dde605df6bd4c85a3d895
Reviewed-on: https://go-review.googlesource.com/38287Reviewed-by: default avatarCherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
parent e74c6cd3
Show whitespace changes
Inline Side-by-side
Showing with 142 additions and 148 deletions
src/cmd/internal/obj/mips/a.out.go
View file @ 6f4a4585
......@@ -31,7 +31,6 @@ package mips
import (
"cmd/internal/obj"
"cmd/internal/sys"
)
//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p mips
......@@ -220,11 +219,6 @@ const (
NSCHED = 20
)
const (
Mips32 = sys.MIPS
Mips64 = sys.MIPS64
)
const (
C_NONE = iota
C_REG
......
src/cmd/internal/obj/mips/asm0.go
View file @ 6f4a4585
......@@ -55,194 +55,194 @@ type Optab struct {
type_ int8
size int8
param int16
family sys.ArchFamily // 0 means both Mips32 and Mips64
family sys.ArchFamily // 0 means both sys.MIPS and sys.MIPS64
}
var optab = []Optab{
{obj.ATEXT, C_LEXT, C_NONE, C_TEXTSIZE, 0, 0, 0, Mips64},
{obj.ATEXT, C_LEXT, C_NONE, C_TEXTSIZE, 0, 0, 0, sys.MIPS64},
{obj.ATEXT, C_ADDR, C_NONE, C_TEXTSIZE, 0, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_REG, 1, 4, 0, 0},
{AMOVV, C_REG, C_NONE, C_REG, 1, 4, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_REG, 1, 4, 0, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_REG, 12, 8, 0, 0},
{AMOVBU, C_REG, C_NONE, C_REG, 13, 4, 0, 0},
{AMOVWU, C_REG, C_NONE, C_REG, 14, 8, 0, Mips64},
{AMOVWU, C_REG, C_NONE, C_REG, 14, 8, 0, sys.MIPS64},
{ASUB, C_REG, C_REG, C_REG, 2, 4, 0, 0},
{ASUBV, C_REG, C_REG, C_REG, 2, 4, 0, Mips64},
{ASUBV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64},
{AADD, C_REG, C_REG, C_REG, 2, 4, 0, 0},
{AADDV, C_REG, C_REG, C_REG, 2, 4, 0, Mips64},
{AADDV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64},
{AAND, C_REG, C_REG, C_REG, 2, 4, 0, 0},
{ASUB, C_REG, C_NONE, C_REG, 2, 4, 0, 0},
{ASUBV, C_REG, C_NONE, C_REG, 2, 4, 0, Mips64},
{ASUBV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64},
{AADD, C_REG, C_NONE, C_REG, 2, 4, 0, 0},
{AADDV, C_REG, C_NONE, C_REG, 2, 4, 0, Mips64},
{AADDV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64},
{AAND, C_REG, C_NONE, C_REG, 2, 4, 0, 0},
{ACMOVN, C_REG, C_REG, C_REG, 2, 4, 0, 0},
{ASLL, C_REG, C_NONE, C_REG, 9, 4, 0, 0},
{ASLL, C_REG, C_REG, C_REG, 9, 4, 0, 0},
{ASLLV, C_REG, C_NONE, C_REG, 9, 4, 0, Mips64},
{ASLLV, C_REG, C_REG, C_REG, 9, 4, 0, Mips64},
{ASLLV, C_REG, C_NONE, C_REG, 9, 4, 0, sys.MIPS64},
{ASLLV, C_REG, C_REG, C_REG, 9, 4, 0, sys.MIPS64},
{ACLO, C_REG, C_NONE, C_REG, 9, 4, 0, 0},
{AADDF, C_FREG, C_NONE, C_FREG, 32, 4, 0, 0},
{AADDF, C_FREG, C_REG, C_FREG, 32, 4, 0, 0},
{ACMPEQF, C_FREG, C_REG, C_NONE, 32, 4, 0, 0},
{AABSF, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0},
{AMOVVF, C_FREG, C_NONE, C_FREG, 33, 4, 0, Mips64},
{AMOVVF, C_FREG, C_NONE, C_FREG, 33, 4, 0, sys.MIPS64},
{AMOVF, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0},
{AMOVD, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0},
{AMOVW, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64},
{AMOVWU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64},
{AMOVV, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64},
{AMOVB, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64},
{AMOVBU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64},
{AMOVWL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64},
{AMOVVL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64},
{AMOVW, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
{AMOVWU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
{AMOVBU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
{AMOVWL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
{AMOVVL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
{AMOVWU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, Mips64},
{AMOVV, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, Mips64},
{AMOVWU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
{AMOVBU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
{AMOVWL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
{AMOVVL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, Mips64},
{AMOVVL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
{AMOVWU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, Mips64},
{AMOVV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, Mips64},
{AMOVWU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
{AMOVBU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
{AMOVWL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
{AMOVVL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, Mips64},
{AMOVVL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
{ASC, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
{AMOVW, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, Mips64},
{AMOVWU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, Mips64},
{AMOVV, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, Mips64},
{AMOVB, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, Mips64},
{AMOVBU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, Mips64},
{AMOVWL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, Mips64},
{AMOVVL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, Mips64},
{AMOVW, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
{AMOVWU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
{AMOVV, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
{AMOVB, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
{AMOVBU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
{AMOVWL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
{AMOVVL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
{AMOVW, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
{AMOVWU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, Mips64},
{AMOVV, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, Mips64},
{AMOVWU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64},
{AMOVV, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64},
{AMOVB, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
{AMOVBU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
{AMOVWL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
{AMOVVL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, Mips64},
{AMOVVL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64},
{AMOVW, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
{AMOVWU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, Mips64},
{AMOVV, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, Mips64},
{AMOVWU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64},
{AMOVV, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64},
{AMOVB, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
{AMOVBU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
{AMOVWL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
{AMOVVL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, Mips64},
{AMOVVL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64},
{ALL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
{AMOVW, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, Mips64},
{AMOVWU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, Mips64},
{AMOVV, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, Mips64},
{AMOVB, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, Mips64},
{AMOVBU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, Mips64},
{AMOVW, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
{AMOVWU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
{AMOVBU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0},
{AMOVWU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, Mips64},
{AMOVV, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, Mips64},
{AMOVWU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0},
{AMOVBU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0},
{AMOVW, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
{AMOVWU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, Mips64},
{AMOVV, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, Mips64},
{AMOVWU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
{AMOVBU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
{ASC, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
{AMOVW, C_REG, C_NONE, C_ADDR, 50, 8, 0, Mips32},
{AMOVW, C_REG, C_NONE, C_ADDR, 50, 12, 0, Mips64},
{AMOVWU, C_REG, C_NONE, C_ADDR, 50, 12, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_ADDR, 50, 12, 0, Mips64},
{AMOVB, C_REG, C_NONE, C_ADDR, 50, 8, 0, Mips32},
{AMOVB, C_REG, C_NONE, C_ADDR, 50, 12, 0, Mips64},
{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 8, 0, Mips32},
{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 12, 0, Mips64},
{AMOVW, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
{AMOVW, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
{AMOVWU, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
{AMOVB, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_TLS, 53, 8, 0, 0},
{AMOVWU, C_REG, C_NONE, C_TLS, 53, 8, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_TLS, 53, 8, 0, Mips64},
{AMOVWU, C_REG, C_NONE, C_TLS, 53, 8, 0, sys.MIPS64},
{AMOVV, C_REG, C_NONE, C_TLS, 53, 8, 0, sys.MIPS64},
{AMOVB, C_REG, C_NONE, C_TLS, 53, 8, 0, 0},
{AMOVBU, C_REG, C_NONE, C_TLS, 53, 8, 0, 0},
{AMOVW, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, Mips64},
{AMOVWU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, Mips64},
{AMOVV, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, Mips64},
{AMOVB, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, Mips64},
{AMOVBU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, Mips64},
{AMOVW, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
{AMOVWU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
{AMOVV, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
{AMOVB, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
{AMOVBU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
{AMOVW, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0},
{AMOVWU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, Mips64},
{AMOVV, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, Mips64},
{AMOVWU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, sys.MIPS64},
{AMOVV, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, sys.MIPS64},
{AMOVB, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0},
{AMOVBU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0},
{AMOVW, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0},
{AMOVWU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, Mips64},
{AMOVV, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, Mips64},
{AMOVWU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, sys.MIPS64},
{AMOVV, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, sys.MIPS64},
{AMOVB, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0},
{AMOVBU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0},
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 8, 0, Mips32},
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 12, 0, Mips64},
{AMOVWU, C_ADDR, C_NONE, C_REG, 51, 12, 0, Mips64},
{AMOVV, C_ADDR, C_NONE, C_REG, 51, 12, 0, Mips64},
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 8, 0, Mips32},
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 12, 0, Mips64},
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 8, 0, Mips32},
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 12, 0, Mips64},
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS},
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
{AMOVWU, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
{AMOVV, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS},
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS},
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
{AMOVW, C_TLS, C_NONE, C_REG, 54, 8, 0, 0},
{AMOVWU, C_TLS, C_NONE, C_REG, 54, 8, 0, Mips64},
{AMOVV, C_TLS, C_NONE, C_REG, 54, 8, 0, Mips64},
{AMOVWU, C_TLS, C_NONE, C_REG, 54, 8, 0, sys.MIPS64},
{AMOVV, C_TLS, C_NONE, C_REG, 54, 8, 0, sys.MIPS64},
{AMOVB, C_TLS, C_NONE, C_REG, 54, 8, 0, 0},
{AMOVBU, C_TLS, C_NONE, C_REG, 54, 8, 0, 0},
{AMOVW, C_SECON, C_NONE, C_REG, 3, 4, REGSB, Mips64},
{AMOVV, C_SECON, C_NONE, C_REG, 3, 4, REGSB, Mips64},
{AMOVW, C_SECON, C_NONE, C_REG, 3, 4, REGSB, sys.MIPS64},
{AMOVV, C_SECON, C_NONE, C_REG, 3, 4, REGSB, sys.MIPS64},
{AMOVW, C_SACON, C_NONE, C_REG, 3, 4, REGSP, 0},
{AMOVV, C_SACON, C_NONE, C_REG, 3, 4, REGSP, Mips64},
{AMOVW, C_LECON, C_NONE, C_REG, 52, 8, REGSB, Mips32},
{AMOVW, C_LECON, C_NONE, C_REG, 52, 12, REGSB, Mips64},
{AMOVV, C_LECON, C_NONE, C_REG, 52, 12, REGSB, Mips64},
{AMOVV, C_SACON, C_NONE, C_REG, 3, 4, REGSP, sys.MIPS64},
{AMOVW, C_LECON, C_NONE, C_REG, 52, 8, REGSB, sys.MIPS},
{AMOVW, C_LECON, C_NONE, C_REG, 52, 12, REGSB, sys.MIPS64},
{AMOVV, C_LECON, C_NONE, C_REG, 52, 12, REGSB, sys.MIPS64},
{AMOVW, C_LACON, C_NONE, C_REG, 26, 12, REGSP, 0},
{AMOVV, C_LACON, C_NONE, C_REG, 26, 12, REGSP, Mips64},
{AMOVV, C_LACON, C_NONE, C_REG, 26, 12, REGSP, sys.MIPS64},
{AMOVW, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO, 0},
{AMOVV, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO, Mips64},
{AMOVV, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO, sys.MIPS64},
{AMOVW, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO, 0},
{AMOVV, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO, Mips64},
{AMOVV, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO, sys.MIPS64},
{AMOVW, C_STCON, C_NONE, C_REG, 55, 8, 0, 0},
{AMOVV, C_STCON, C_NONE, C_REG, 55, 8, 0, Mips64},
{AMOVV, C_STCON, C_NONE, C_REG, 55, 8, 0, sys.MIPS64},
{AMOVW, C_UCON, C_NONE, C_REG, 24, 4, 0, 0},
{AMOVV, C_UCON, C_NONE, C_REG, 24, 4, 0, Mips64},
{AMOVV, C_UCON, C_NONE, C_REG, 24, 4, 0, sys.MIPS64},
{AMOVW, C_LCON, C_NONE, C_REG, 19, 8, 0, 0},
{AMOVV, C_LCON, C_NONE, C_REG, 19, 8, 0, Mips64},
{AMOVV, C_LCON, C_NONE, C_REG, 19, 8, 0, sys.MIPS64},
{AMOVW, C_HI, C_NONE, C_REG, 20, 4, 0, 0},
{AMOVV, C_HI, C_NONE, C_REG, 20, 4, 0, Mips64},
{AMOVV, C_HI, C_NONE, C_REG, 20, 4, 0, sys.MIPS64},
{AMOVW, C_LO, C_NONE, C_REG, 20, 4, 0, 0},
{AMOVV, C_LO, C_NONE, C_REG, 20, 4, 0, Mips64},
{AMOVV, C_LO, C_NONE, C_REG, 20, 4, 0, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_HI, 21, 4, 0, 0},
{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0, 0},
{AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0, sys.MIPS64},
{AMUL, C_REG, C_REG, C_NONE, 22, 4, 0, 0},
{AMUL, C_REG, C_REG, C_REG, 22, 4, 0, 0},
{AMULV, C_REG, C_REG, C_NONE, 22, 4, 0, Mips64},
{AMULV, C_REG, C_REG, C_NONE, 22, 4, 0, sys.MIPS64},
{AADD, C_ADD0CON, C_REG, C_REG, 4, 4, 0, 0},
{AADD, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, 0},
{AADD, C_ANDCON, C_REG, C_REG, 10, 8, 0, 0},
{AADD, C_ANDCON, C_NONE, C_REG, 10, 8, 0, 0},
{AADDV, C_ADD0CON, C_REG, C_REG, 4, 4, 0, Mips64},
{AADDV, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, Mips64},
{AADDV, C_ANDCON, C_REG, C_REG, 10, 8, 0, Mips64},
{AADDV, C_ANDCON, C_NONE, C_REG, 10, 8, 0, Mips64},
{AADDV, C_ADD0CON, C_REG, C_REG, 4, 4, 0, sys.MIPS64},
{AADDV, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, sys.MIPS64},
{AADDV, C_ANDCON, C_REG, C_REG, 10, 8, 0, sys.MIPS64},
{AADDV, C_ANDCON, C_NONE, C_REG, 10, 8, 0, sys.MIPS64},
{AAND, C_AND0CON, C_REG, C_REG, 4, 4, 0, 0},
{AAND, C_AND0CON, C_NONE, C_REG, 4, 4, 0, 0},
......@@ -251,23 +251,23 @@ var optab = []Optab{
{AADD, C_UCON, C_REG, C_REG, 25, 8, 0, 0},
{AADD, C_UCON, C_NONE, C_REG, 25, 8, 0, 0},
{AADDV, C_UCON, C_REG, C_REG, 25, 8, 0, Mips64},
{AADDV, C_UCON, C_NONE, C_REG, 25, 8, 0, Mips64},
{AADDV, C_UCON, C_REG, C_REG, 25, 8, 0, sys.MIPS64},
{AADDV, C_UCON, C_NONE, C_REG, 25, 8, 0, sys.MIPS64},
{AAND, C_UCON, C_REG, C_REG, 25, 8, 0, 0},
{AAND, C_UCON, C_NONE, C_REG, 25, 8, 0, 0},
{AADD, C_LCON, C_NONE, C_REG, 23, 12, 0, 0},
{AADDV, C_LCON, C_NONE, C_REG, 23, 12, 0, Mips64},
{AADDV, C_LCON, C_NONE, C_REG, 23, 12, 0, sys.MIPS64},
{AAND, C_LCON, C_NONE, C_REG, 23, 12, 0, 0},
{AADD, C_LCON, C_REG, C_REG, 23, 12, 0, 0},
{AADDV, C_LCON, C_REG, C_REG, 23, 12, 0, Mips64},
{AADDV, C_LCON, C_REG, C_REG, 23, 12, 0, sys.MIPS64},
{AAND, C_LCON, C_REG, C_REG, 23, 12, 0, 0},
{ASLL, C_SCON, C_REG, C_REG, 16, 4, 0, 0},
{ASLL, C_SCON, C_NONE, C_REG, 16, 4, 0, 0},
{ASLLV, C_SCON, C_REG, C_REG, 16, 4, 0, Mips64},
{ASLLV, C_SCON, C_NONE, C_REG, 16, 4, 0, Mips64},
{ASLLV, C_SCON, C_REG, C_REG, 16, 4, 0, sys.MIPS64},
{ASLLV, C_SCON, C_NONE, C_REG, 16, 4, 0, sys.MIPS64},
{ASYSCALL, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
......@@ -282,81 +282,81 @@ var optab = []Optab{
{AJMP, C_NONE, C_NONE, C_ZOREG, 18, 4, REGZERO, 0},
{AJAL, C_NONE, C_NONE, C_ZOREG, 18, 4, REGLINK, 0},
{AMOVW, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, Mips64},
{AMOVF, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, Mips64},
{AMOVD, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, Mips64},
{AMOVW, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, Mips64},
{AMOVW, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64},
{AMOVF, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64},
{AMOVD, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64},
{AMOVW, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, sys.MIPS64},
{AMOVF, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, 0},
{AMOVD, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, 0},
{AMOVW, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, Mips64},
{AMOVW, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, sys.MIPS64},
{AMOVF, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, 0},
{AMOVD, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, 0},
{AMOVW, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, Mips64},
{AMOVF, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, Mips64},
{AMOVD, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, Mips64},
{AMOVW, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, Mips64},
{AMOVW, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64},
{AMOVF, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64},
{AMOVD, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64},
{AMOVW, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, sys.MIPS64},
{AMOVF, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, 0},
{AMOVD, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, 0},
{AMOVW, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, Mips64},
{AMOVW, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, sys.MIPS64},
{AMOVF, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, 0},
{AMOVD, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, 0},
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 8, 0, Mips32},
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 12, 0, Mips64},
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 8, 0, Mips32},
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 12, 0, Mips64},
{AMOVW, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, Mips64},
{AMOVF, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, Mips64},
{AMOVD, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, Mips64},
{AMOVW, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, Mips64},
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 8, 0, sys.MIPS},
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 12, 0, sys.MIPS64},
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 8, 0, sys.MIPS},
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 12, 0, sys.MIPS64},
{AMOVW, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64},
{AMOVF, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64},
{AMOVD, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64},
{AMOVW, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, sys.MIPS64},
{AMOVF, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, 0},
{AMOVD, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, 0},
{AMOVW, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, Mips64},
{AMOVW, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, sys.MIPS64},
{AMOVF, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, 0},
{AMOVD, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, 0},
{AMOVW, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, Mips64},
{AMOVF, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, Mips64},
{AMOVD, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, Mips64},
{AMOVW, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, Mips64},
{AMOVW, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64},
{AMOVF, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64},
{AMOVD, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64},
{AMOVW, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, sys.MIPS64},
{AMOVF, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, 0},
{AMOVD, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, 0},
{AMOVW, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, Mips64},
{AMOVW, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, sys.MIPS64},
{AMOVF, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, 0},
{AMOVD, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, 0},
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 8, 0, Mips32},
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 12, 0, Mips64},
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 8, 0, Mips32},
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 12, 0, Mips64},
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_FREG, 30, 4, 0, 0},
{AMOVW, C_FREG, C_NONE, C_REG, 31, 4, 0, 0},
{AMOVV, C_REG, C_NONE, C_FREG, 47, 4, 0, Mips64},
{AMOVV, C_FREG, C_NONE, C_REG, 48, 4, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_FREG, 47, 4, 0, sys.MIPS64},
{AMOVV, C_FREG, C_NONE, C_REG, 48, 4, 0, sys.MIPS64},
{AMOVW, C_ADDCON, C_NONE, C_FREG, 34, 8, 0, Mips64},
{AMOVW, C_ANDCON, C_NONE, C_FREG, 34, 8, 0, Mips64},
{AMOVW, C_ADDCON, C_NONE, C_FREG, 34, 8, 0, sys.MIPS64},
{AMOVW, C_ANDCON, C_NONE, C_FREG, 34, 8, 0, sys.MIPS64},
{AMOVW, C_REG, C_NONE, C_MREG, 37, 4, 0, 0},
{AMOVV, C_REG, C_NONE, C_MREG, 37, 4, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_MREG, 37, 4, 0, sys.MIPS64},
{AMOVW, C_MREG, C_NONE, C_REG, 38, 4, 0, 0},
{AMOVV, C_MREG, C_NONE, C_REG, 38, 4, 0, Mips64},
{AMOVV, C_MREG, C_NONE, C_REG, 38, 4, 0, sys.MIPS64},
{AWORD, C_LCON, C_NONE, C_NONE, 40, 4, 0, 0},
{AMOVW, C_REG, C_NONE, C_FCREG, 41, 8, 0, 0},
{AMOVV, C_REG, C_NONE, C_FCREG, 41, 8, 0, Mips64},
{AMOVV, C_REG, C_NONE, C_FCREG, 41, 8, 0, sys.MIPS64},
{AMOVW, C_FCREG, C_NONE, C_REG, 42, 4, 0, 0},
{AMOVV, C_FCREG, C_NONE, C_REG, 42, 4, 0, Mips64},
{AMOVV, C_FCREG, C_NONE, C_REG, 42, 4, 0, sys.MIPS64},
{ATEQ, C_SCON, C_REG, C_REG, 15, 4, 0, 0},
{ATEQ, C_SCON, C_NONE, C_REG, 15, 4, 0, 0},
{ACMOVT, C_REG, C_NONE, C_REG, 17, 4, 0, 0},
{ABREAK, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, Mips64}, /* really CACHE instruction */
{ABREAK, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, Mips64},
{ABREAK, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, Mips64},
{ABREAK, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64}, /* really CACHE instruction */
{ABREAK, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
{ABREAK, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
{ABREAK, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
......
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