cmd/internal/obj: instructions and registers for RISC-V
Start implementing an assembler for RISC-V - this provides register definitions and instruction mnemonics as defined in the RISC-V Instruction Set Manual, along with instruction encoding. The instruction encoding is generated by the parse_opcodes script with the "opcodes" and "opcodes-pseudo" files from (`make inst.go`): https://github.com/riscv/riscv-opcodes This is based on the riscv-go port: https://github.com/riscv/riscv-go Contributors to the riscv-go port are: Amol Bhave <ammubhave@gmail.com> Benjamin Barenblat <bbaren@google.com> Josh Bleecher Snyder <josharian@gmail.com> Michael Pratt <michael@pratt.im> Michael Yenik <myenik@google.com> Ronald G. Minnich <rminnich@gmail.com> Stefan O'Rear <sorear2@gmail.com> This port has been updated to Go 1.13: https://github.com/4a6f656c/riscv-go Updates #27532 Change-Id: I257b6de87e9864df61a2b0ce9be15968c1227b49 Reviewed-on: https://go-review.googlesource.com/c/go/+/193677 Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by:Cherry Zhang <cherryyz@google.com>
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