Commit 91706c04 authored by Michael Munday's avatar Michael Munday

cmd/asm, cmd/internal/obj/s390x: delete unused instructions

Deletes the following s390x instructions:

 - ADDME
 - ADDZE
 - SUBME
 - SUBZE

They appear to be emulated PPC instructions left over from the
porting process and I don't think they will ever be useful.

Change-Id: I9b1ba78019dbd1218d0c8f8ea2903878802d1990
Reviewed-on: https://go-review.googlesource.com/30538
Run-TryBot: Michael Munday <munday@ca.ibm.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: default avatarBrad Fitzpatrick <bradfitz@golang.org>
parent d7507e9d
...@@ -80,11 +80,7 @@ func IsS390xCMP(op obj.As) bool { ...@@ -80,11 +80,7 @@ func IsS390xCMP(op obj.As) bool {
// one of the NEG-like instructions that require special handling. // one of the NEG-like instructions that require special handling.
func IsS390xNEG(op obj.As) bool { func IsS390xNEG(op obj.As) bool {
switch op { switch op {
case s390x.AADDME, case s390x.ANEG, s390x.ANEGW:
s390x.AADDZE,
s390x.ANEG,
s390x.ASUBME,
s390x.ASUBZE:
return true return true
} }
return false return false
......
...@@ -209,9 +209,7 @@ const ( ...@@ -209,9 +209,7 @@ const (
// integer arithmetic // integer arithmetic
AADD = obj.ABaseS390X + obj.A_ARCHSPECIFIC + iota AADD = obj.ABaseS390X + obj.A_ARCHSPECIFIC + iota
AADDC AADDC
AADDME
AADDE AADDE
AADDZE
AADDW AADDW
ADIVW ADIVW
ADIVWU ADIVWU
...@@ -227,10 +225,8 @@ const ( ...@@ -227,10 +225,8 @@ const (
AMULHDU AMULHDU
ASUB ASUB
ASUBC ASUBC
ASUBME
ASUBV ASUBV
ASUBE ASUBE
ASUBZE
ASUBW ASUBW
ANEG ANEG
ANEGW ANEGW
......
...@@ -8,9 +8,7 @@ import "cmd/internal/obj" ...@@ -8,9 +8,7 @@ import "cmd/internal/obj"
var Anames = []string{ var Anames = []string{
obj.A_ARCHSPECIFIC: "ADD", obj.A_ARCHSPECIFIC: "ADD",
"ADDC", "ADDC",
"ADDME",
"ADDE", "ADDE",
"ADDZE",
"ADDW", "ADDW",
"DIVW", "DIVW",
"DIVWU", "DIVWU",
...@@ -26,10 +24,8 @@ var Anames = []string{ ...@@ -26,10 +24,8 @@ var Anames = []string{
"MULHDU", "MULHDU",
"SUB", "SUB",
"SUBC", "SUBC",
"SUBME",
"SUBV", "SUBV",
"SUBE", "SUBE",
"SUBZE",
"SUBW", "SUBW",
"NEG", "NEG",
"NEGW", "NEGW",
......
...@@ -153,7 +153,6 @@ var optab = []Optab{ ...@@ -153,7 +153,6 @@ var optab = []Optab{
Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0},
Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0},
Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0},
Optab{AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 0},
Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0},
Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0},
...@@ -837,10 +836,6 @@ func buildop(ctxt *obj.Link) { ...@@ -837,10 +836,6 @@ func buildop(ctxt *obj.Link) {
opset(ASTMY, r) opset(ASTMY, r)
case ALMG: case ALMG:
opset(ALMY, r) opset(ALMY, r)
case AADDME:
opset(AADDZE, r)
opset(ASUBME, r)
opset(ASUBZE, r)
case ABEQ: case ABEQ:
opset(ABGE, r) opset(ABGE, r)
opset(ABGT, r) opset(ABGT, r)
...@@ -3232,49 +3227,15 @@ func asmout(ctxt *obj.Link, asm *[]byte) { ...@@ -3232,49 +3227,15 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
*asm = append(*asm, uint8(wd)) *asm = append(*asm, uint8(wd))
} }
case 47: // arithmetic op (carry) reg [reg] reg case 47: // negate [reg] reg
r := p.From.Reg
switch p.As {
default:
case AADDME:
if p.To.Reg == p.From.Reg {
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
r = REGTMP
}
zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1
zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm)
case AADDZE:
if p.To.Reg == p.From.Reg {
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
r = REGTMP
}
zRI(op_LGHI, uint32(p.To.Reg), 0, asm)
zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm)
case ASUBME:
if p.To.Reg == p.From.Reg {
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
r = REGTMP
}
zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1
zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm)
case ASUBZE:
if p.To.Reg == p.From.Reg {
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
r = REGTMP
}
zRI(op_LGHI, uint32(p.To.Reg), 0, asm)
zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm)
case ANEG:
r := p.From.Reg r := p.From.Reg
if r == 0 { if r == 0 {
r = p.To.Reg r = p.To.Reg
} }
switch p.As {
case ANEG:
zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
case ANEGW: case ANEGW:
r := p.From.Reg
if r == 0 {
r = p.To.Reg
}
zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
} }
......
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