[ARM] Ensure we preserve other CPSR bits when switching to SVC mode.

016e1577 · Russell King · 5a236669 · 016e1577
Commit 016e1577 authored Mar 06, 2003 by Russell King
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Showing with 4 additions and 2 deletions

arch/arm/kernel/entry-armv.S arch/arm/kernel/entry-armv.S +4 -2

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--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -1028,8 +1028,10 @@ vector_IRQ:	@
 		@
 		@ now branch to the relevant MODE handling routine
 		@
-		mov	r13, #PSR_I_BIT | MODE_SVC
+		mrs	r13, cpsr
-		msr	spsr_c, r13			@ switch to SVC_32 mode
+		bic	r13, r13, #MODE_MASK
+		orr	r13, r13, #MODE_SVC
+		msr	spsr, r13			@ switch to SVC_32 mode
 		and	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]