Skip to content

L
linux
Commit 03c7f70b authored by David S. Miller's avatar David S. Miller
Browse files
Options

Merge branch 'qed-roce-iscsi' 

Yuval Mintz says:

====================
qed: RocE & iSCSI infrastructure

We plan on sending 2 new protocol drivers in the imminent future -
both our RoCE [qedr] and iSCSI [qedi] drivers. As both submissions
would be rather massive and in order to avoid collisions between them,
the common infrastructure on the qed side was prepared as an independent
patch-series to be sent ahead of those 2 submissions.

This patch series introduces in QED 2 new 'ids' - one for iscsi and
one for roce. It then goes and adds logic required for configuring
said protocols in HW. Notice it *doesn't* actually add any client using
said ids, but rather only the infrastructure to allow their later usage.

What this patch doesn't contain is the slowpath protocol-configuration
toward the firmware. I.e., it contains register-setting logic, memory
allocations, etc., but not actual flow-related configuration specific
to the protocl. Those would be sent as part of the protocol driver
submissions.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 330348d9 dbb799c3
Hide whitespace changes
Inline Side-by-side
Showing with 7312 additions and 383 deletions
drivers/net/ethernet/qlogic/qed/qed.h
View file @ 03c7f70b
......@@ -127,6 +127,8 @@ struct qed_tunn_update_params {
*/
enum qed_pci_personality {
QED_PCI_ETH,
QED_PCI_ISCSI,
QED_PCI_ETH_ROCE,
QED_PCI_DEFAULT /* default in shmem */
};
......@@ -170,6 +172,8 @@ enum QED_PORT_MODE {
enum qed_dev_cap {
QED_DEV_CAP_ETH,
QED_DEV_CAP_ISCSI,
QED_DEV_CAP_ROCE,
};
struct qed_hw_info {
......@@ -183,6 +187,8 @@ struct qed_hw_info {
#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
RESC_NUM(_p_hwfn, resc))
#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
u8 num_tc;
......@@ -255,6 +261,7 @@ struct qed_qm_info {
u8 pure_lb_pq;
u8 offload_pq;
u8 pure_ack_pq;
u8 ooo_pq;
u8 vf_queues_offset;
u16 num_pqs;
u16 num_vf_pqs;
......@@ -267,6 +274,7 @@ struct qed_qm_info {
u8 pf_wfq;
u32 pf_rl;
struct qed_wfq_data *wfq_data;
u8 num_pf_rls;
};
struct storm_stats {
......@@ -312,6 +320,7 @@ struct qed_hwfn {
bool hw_init_done;
u8 num_funcs_on_engine;
u8 enabled_func_idx;
/* BAR access */
void __iomem *regview;
......@@ -350,6 +359,9 @@ struct qed_hwfn {
/* Protocol related */
struct qed_pf_params pf_params;
bool b_rdma_enabled_in_prs;
u32 rdma_prs_search_reg;
/* Array of sb_info of all status blocks */
struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
u16 num_sbs;
......@@ -555,6 +567,7 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
}
#define PURE_LB_TC 8
#define OOO_LB_TC 9
int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
......
drivers/net/ethernet/qlogic/qed/qed_cxt.c
View file @ 03c7f70b
......@@ -39,6 +39,14 @@
#define DQ_RANGE_SHIFT 4
#define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT)
/* Searcher constants */
#define SRC_MIN_NUM_ELEMS 256
/* Timers constants */
#define TM_SHIFT 7
#define TM_ALIGN BIT(TM_SHIFT)
#define TM_ELEM_SIZE 4
/* ILT constants */
#define ILT_DEFAULT_HW_P_SIZE 3
#define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
......@@ -56,26 +64,71 @@
union conn_context {
struct core_conn_context core_ctx;
struct eth_conn_context eth_ctx;
struct iscsi_conn_context iscsi_ctx;
struct roce_conn_context roce_ctx;
};
/* TYPE-0 task context - iSCSI */
union type0_task_context {
struct iscsi_task_context iscsi_ctx;
};
/* TYPE-1 task context - ROCE */
union type1_task_context {
struct rdma_task_context roce_ctx;
};
struct src_ent {
u8 opaque[56];
u64 next;
};
#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
#define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
#define CONN_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
#define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
#define TYPE0_TASK_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
/* Alignment is inherent to the type1_task_context structure */
#define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
/* PF per protocl configuration object */
#define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
#define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
struct qed_tid_seg {
u32 count;
u8 type;
bool has_fl_mem;
};
struct qed_conn_type_cfg {
u32 cid_count;
u32 cid_start;
u32 cids_per_vf;
struct qed_tid_seg tid_seg[TASK_SEGMENTS];
};
/* ILT Client configuration, Per connection type (protocol) resources. */
#define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
#define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
#define CDUC_BLK (0)
#define SRQ_BLK (0)
#define CDUT_SEG_BLK(n) (1 + (u8)(n))
#define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
enum ilt_clients {
ILT_CLI_CDUC,
ILT_CLI_CDUT,
ILT_CLI_QM,
ILT_CLI_TM,
ILT_CLI_SRC,
ILT_CLI_TSDM,
ILT_CLI_MAX
};
......@@ -88,6 +141,7 @@ struct qed_ilt_cli_blk {
u32 total_size; /* 0 means not active */
u32 real_size_in_page;
u32 start_line;
u32 dynamic_line_cnt;
};
struct qed_ilt_client_cfg {
......@@ -131,18 +185,44 @@ struct qed_cxt_mngr {
/* computed ILT structure */
struct qed_ilt_client_cfg clients[ILT_CLI_MAX];
/* Task type sizes */
u32 task_type_size[NUM_TASK_TYPES];
/* total number of VFs for this hwfn -
* ALL VFs are symmetric in terms of HW resources
*/
u32 vf_count;
/* total number of SRQ's for this hwfn */
u32 srq_count;
/* Acquired CIDs */
struct qed_cid_acquired_map acquired[MAX_CONN_TYPES];
/* ILT shadow table */
struct qed_dma_mem *ilt_shadow;
u32 pf_start_line;
/* Mutex for a dynamic ILT allocation */
struct mutex mutex;
/* SRC T2 */
struct qed_dma_mem *t2;
u32 t2_num_pages;
u64 first_free;
u64 last_free;
};
static bool src_proto(enum protocol_type type)
{
return type == PROTOCOLID_ISCSI ||
type == PROTOCOLID_ROCE;
}
static bool tm_cid_proto(enum protocol_type type)
{
return type == PROTOCOLID_ISCSI ||
type == PROTOCOLID_ROCE;
}
/* counts the iids for the CDU/CDUC ILT client configuration */
struct qed_cdu_iids {
......@@ -161,21 +241,120 @@ static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
}
}
/* counts the iids for the Searcher block configuration */
struct qed_src_iids {
u32 pf_cids;
u32 per_vf_cids;
};
static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
struct qed_src_iids *iids)
{
u32 i;
for (i = 0; i < MAX_CONN_TYPES; i++) {
if (!src_proto(i))
continue;
iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
}
}
/* counts the iids for the Timers block configuration */
struct qed_tm_iids {
u32 pf_cids;
u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
u32 pf_tids_total;
u32 per_vf_cids;
u32 per_vf_tids;
};
static void qed_cxt_tm_iids(struct qed_cxt_mngr *p_mngr,
struct qed_tm_iids *iids)
{
u32 i, j;
for (i = 0; i < MAX_CONN_TYPES; i++) {
struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
if (tm_cid_proto(i)) {
iids->pf_cids += p_cfg->cid_count;
iids->per_vf_cids += p_cfg->cids_per_vf;
}
}
iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
iids->pf_tids_total += iids->pf_tids[j];
}
}
static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
struct qed_qm_iids *iids)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
u32 vf_cids = 0, type;
struct qed_tid_seg *segs;
u32 vf_cids = 0, type, j;
u32 vf_tids = 0;
for (type = 0; type < MAX_CONN_TYPES; type++) {
iids->cids += p_mngr->conn_cfg[type].cid_count;
vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
segs = p_mngr->conn_cfg[type].tid_seg;
/* for each segment there is at most one
* protocol for which count is not 0.
*/
for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
iids->tids += segs[j].count;
/* The last array elelment is for the VFs. As for PF
* segments there can be only one protocol for
* which this value is not 0.
*/
vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
}
iids->vf_cids += vf_cids * p_mngr->vf_count;
iids->tids += vf_tids * p_mngr->vf_count;
DP_VERBOSE(p_hwfn, QED_MSG_ILT,
"iids: CIDS %08x vf_cids %08x\n",
iids->cids, iids->vf_cids);
"iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
iids->cids, iids->vf_cids, iids->tids, vf_tids);
}
static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
u32 seg)
{
struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
u32 i;
/* Find the protocol with tid count > 0 for this segment.
* Note: there can only be one and this is already validated.
*/
for (i = 0; i < MAX_CONN_TYPES; i++)
if (p_cfg->conn_cfg[i].tid_seg[seg].count)
return &p_cfg->conn_cfg[i].tid_seg[seg];
return NULL;
}
void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
{
struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
p_mgr->srq_count = num_srqs;
}
u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
{
struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
return p_mgr->srq_count;
}
/* set the iids count per protocol */
......@@ -188,6 +367,14 @@ static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
if (type == PROTOCOLID_ROCE) {
u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page);
}
}
u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
......@@ -200,6 +387,37 @@ u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
}
u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
enum protocol_type type)
{
return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
}
u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
enum protocol_type type)
{
u32 cnt = 0;
int i;
for (i = 0; i < TASK_SEGMENTS; i++)
cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
return cnt;
}
static void
qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
enum protocol_type proto,
u8 seg, u8 seg_type, u32 count, bool has_fl)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
p_seg->count = count;
p_seg->has_fl_mem = has_fl;
p_seg->type = seg_type;
}
static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
struct qed_ilt_cli_blk *p_blk,
u32 start_line, u32 total_size,
......@@ -241,17 +459,42 @@ static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
p_blk->real_size_in_page, p_blk->start_line);
}
static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
enum ilt_clients ilt_client)
{
u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
struct qed_ilt_client_cfg *p_cli;
u32 lines_to_skip = 0;
u32 cxts_per_p;
if (ilt_client == ILT_CLI_CDUC) {
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
(u32) CONN_CXT_SIZE(p_hwfn);
lines_to_skip = cid_count / cxts_per_p;
}
return lines_to_skip;
}
int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
u32 curr_line, total, i, task_size, line;
struct qed_ilt_client_cfg *p_cli;
struct qed_ilt_cli_blk *p_blk;
struct qed_cdu_iids cdu_iids;
struct qed_src_iids src_iids;
struct qed_qm_iids qm_iids;
u32 curr_line, total, i;
struct qed_tm_iids tm_iids;
struct qed_tid_seg *p_seg;
memset(&qm_iids, 0, sizeof(qm_iids));
memset(&cdu_iids, 0, sizeof(cdu_iids));
memset(&src_iids, 0, sizeof(src_iids));
memset(&tm_iids, 0, sizeof(tm_iids));
p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
......@@ -279,6 +522,9 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
ILT_CLI_CDUC);
/* CDUC VF */
p_blk = &p_cli->vf_blks[CDUC_BLK];
total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
......@@ -293,21 +539,128 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_CDUC);
/* CDUT PF */
p_cli = &p_mngr->clients[ILT_CLI_CDUT];
p_cli->first.val = curr_line;
/* first the 'working' task memory */
for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
if (!p_seg || p_seg->count == 0)
continue;
p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
total = p_seg->count * p_mngr->task_type_size[p_seg->type];
qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
p_mngr->task_type_size[p_seg->type]);
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_CDUT);
}
/* next the 'init' task memory (forced load memory) */
for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
if (!p_seg || p_seg->count == 0)
continue;
p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
if (!p_seg->has_fl_mem) {
/* The segment is active (total size pf 'working'
* memory is > 0) but has no FL (forced-load, Init)
* memory. Thus:
*
* 1. The total-size in the corrsponding FL block of
* the ILT client is set to 0 - No ILT line are
* provisioned and no ILT memory allocated.
*
* 2. The start-line of said block is set to the
* start line of the matching working memory
* block in the ILT client. This is later used to
* configure the CDU segment offset registers and
* results in an FL command for TIDs of this
* segement behaves as regular load commands
* (loading TIDs from the working memory).
*/
line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
continue;
}
total = p_seg->count * p_mngr->task_type_size[p_seg->type];
qed_ilt_cli_blk_fill(p_cli, p_blk,
curr_line, total,
p_mngr->task_type_size[p_seg->type]);
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_CDUT);
}
p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
/* CDUT VF */
p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
if (p_seg && p_seg->count) {
/* Stricly speaking we need to iterate over all VF
* task segment types, but a VF has only 1 segment
*/
/* 'working' memory */
total = p_seg->count * p_mngr->task_type_size[p_seg->type];
p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
qed_ilt_cli_blk_fill(p_cli, p_blk,
curr_line, total,
p_mngr->task_type_size[p_seg->type]);
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_CDUT);
/* 'init' memory */
p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
if (!p_seg->has_fl_mem) {
/* see comment above */
line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
} else {
task_size = p_mngr->task_type_size[p_seg->type];
qed_ilt_cli_blk_fill(p_cli, p_blk,
curr_line, total, task_size);
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_CDUT);
}
p_cli->vf_total_lines = curr_line -
p_cli->vf_blks[0].start_line;
/* Now for the rest of the VFs */
for (i = 1; i < p_mngr->vf_count; i++) {
p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_CDUT);
p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_CDUT);
}
}
/* QM */
p_cli = &p_mngr->clients[ILT_CLI_QM];
p_blk = &p_cli->pf_blks[0];
qed_cxt_qm_iids(p_hwfn, &qm_iids);
total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
qm_iids.vf_cids, 0,
qm_iids.vf_cids, qm_iids.tids,
p_hwfn->qm_info.num_pqs,
p_hwfn->qm_info.num_vf_pqs);
DP_VERBOSE(p_hwfn,
QED_MSG_ILT,
"QM ILT Info, (cids=%d, vf_cids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
"QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
qm_iids.cids,
qm_iids.vf_cids,
qm_iids.tids,
p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
qed_ilt_cli_blk_fill(p_cli, p_blk,
......@@ -317,6 +670,75 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
/* SRC */
p_cli = &p_mngr->clients[ILT_CLI_SRC];
qed_cxt_src_iids(p_mngr, &src_iids);
/* Both the PF and VFs searcher connections are stored in the per PF
* database. Thus sum the PF searcher cids and all the VFs searcher
* cids.
*/
total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
if (total) {
u32 local_max = max_t(u32, total,
SRC_MIN_NUM_ELEMS);
total = roundup_pow_of_two(local_max);
p_blk = &p_cli->pf_blks[0];
qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
total * sizeof(struct src_ent),
sizeof(struct src_ent));
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_SRC);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
}
/* TM PF */
p_cli = &p_mngr->clients[ILT_CLI_TM];
qed_cxt_tm_iids(p_mngr, &tm_iids);
total = tm_iids.pf_cids + tm_iids.pf_tids_total;
if (total) {
p_blk = &p_cli->pf_blks[0];
qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
total * TM_ELEM_SIZE, TM_ELEM_SIZE);
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_TM);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
}
/* TM VF */
total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
if (total) {
p_blk = &p_cli->vf_blks[0];
qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
total * TM_ELEM_SIZE, TM_ELEM_SIZE);
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_TM);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
for (i = 1; i < p_mngr->vf_count; i++)
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_TM);
}
/* TSDM (SRQ CONTEXT) */
total = qed_cxt_get_srq_count(p_hwfn);
if (total) {
p_cli = &p_mngr->clients[ILT_CLI_TSDM];
p_blk = &p_cli->pf_blks[SRQ_BLK];
qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_TSDM);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
}
if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
RESC_NUM(p_hwfn, QED_ILT)) {
DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
......@@ -327,8 +749,122 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
return 0;
}
static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
u32 i;
if (!p_mngr->t2)
return;
for (i = 0; i < p_mngr->t2_num_pages; i++)
if (p_mngr->t2[i].p_virt)
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
p_mngr->t2[i].size,
p_mngr->t2[i].p_virt,
p_mngr->t2[i].p_phys);
kfree(p_mngr->t2);
p_mngr->t2 = NULL;
}
static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
u32 conn_num, total_size, ent_per_page, psz, i;
struct qed_ilt_client_cfg *p_src;
struct qed_src_iids src_iids;
struct qed_dma_mem *p_t2;
int rc;
memset(&src_iids, 0, sizeof(src_iids));
/* if the SRC ILT client is inactive - there are no connection
* requiring the searcer, leave.
*/
p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
if (!p_src->active)
return 0;
qed_cxt_src_iids(p_mngr, &src_iids);
conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
total_size = conn_num * sizeof(struct src_ent);
/* use the same page size as the SRC ILT client */
psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
/* allocate t2 */
p_mngr->t2 = kzalloc(p_mngr->t2_num_pages * sizeof(struct qed_dma_mem),
GFP_KERNEL);
if (!p_mngr->t2) {
DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n");
rc = -ENOMEM;
goto t2_fail;
}
/* allocate t2 pages */
for (i = 0; i < p_mngr->t2_num_pages; i++) {
u32 size = min_t(u32, total_size, psz);
void **p_virt = &p_mngr->t2[i].p_virt;
*p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
size,
&p_mngr->t2[i].p_phys, GFP_KERNEL);
if (!p_mngr->t2[i].p_virt) {
rc = -ENOMEM;
goto t2_fail;
}
memset(*p_virt, 0, size);
p_mngr->t2[i].size = size;
total_size -= size;
}
/* Set the t2 pointers */
/* entries per page - must be a power of two */
ent_per_page = psz / sizeof(struct src_ent);
p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
p_mngr->last_free = (u64) p_t2->p_phys +
((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
for (i = 0; i < p_mngr->t2_num_pages; i++) {
u32 ent_num = min_t(u32,
ent_per_page,
conn_num);
struct src_ent *entries = p_mngr->t2[i].p_virt;
u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
u32 j;
for (j = 0; j < ent_num - 1; j++) {
val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
entries[j].next = cpu_to_be64(val);
}
if (i < p_mngr->t2_num_pages - 1)
val = (u64) p_mngr->t2[i + 1].p_phys;
else
val = 0;
entries[j].next = cpu_to_be64(val);
conn_num -= ent_per_page;
}
return 0;
t2_fail:
qed_cxt_src_t2_free(p_hwfn);
return rc;
}
#define for_each_ilt_valid_client(pos, clients) \
for (pos = 0; pos < ILT_CLI_MAX; pos++)
for (pos = 0; pos < ILT_CLI_MAX; pos++) \
if (!clients[pos].active) { \
continue; \
} else \
/* Total number of ILT lines used by this PF */
static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
......@@ -336,12 +872,8 @@ static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
u32 size = 0;
u32 i;
for_each_ilt_valid_client(i, ilt_clients) {
if (!ilt_clients[i].active)
continue;
size += (ilt_clients[i].last.val -
ilt_clients[i].first.val + 1);
}
for_each_ilt_valid_client(i, ilt_clients)
size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
return size;
}
......@@ -372,15 +904,22 @@ static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
u32 start_line_offset)
{
struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
u32 lines, line, sz_left;
u32 lines, line, sz_left, lines_to_skip = 0;
/* Special handling for RoCE that supports dynamic allocation */
if ((p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) &&
((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
return 0;
lines_to_skip = p_blk->dynamic_line_cnt;
if (!p_blk->total_size)
return 0;
sz_left = p_blk->total_size;
lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page);
lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
line = p_blk->start_line + start_line_offset -
p_hwfn->p_cxt_mngr->pf_start_line;
p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
for (; lines; lines--) {
dma_addr_t p_phys;
......@@ -434,8 +973,6 @@ static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
(u32)(size * sizeof(struct qed_dma_mem)));
for_each_ilt_valid_client(i, clients) {
if (!clients[i].active)
continue;
for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
p_blk = &clients[i].pf_blks[j];
rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
......@@ -514,6 +1051,7 @@ static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
{
struct qed_ilt_client_cfg *clients;
struct qed_cxt_mngr *p_mngr;
u32 i;
......@@ -524,20 +1062,42 @@ int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
}
/* Initialize ILT client registers */
p_mngr->clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
p_mngr->clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
p_mngr->clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
p_mngr->clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
p_mngr->clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
p_mngr->clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
clients = p_mngr->clients;
clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
/* default ILT page size for all clients is 32K */
for (i = 0; i < ILT_CLI_MAX; i++)
p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
/* Initialize task sizes */
p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
if (p_hwfn->cdev->p_iov_info)
p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
/* Initialize the dynamic ILT allocation mutex */
mutex_init(&p_mngr->mutex);
/* Set the cxt mangr pointer priori to further allocations */
p_hwfn->p_cxt_mngr = p_mngr;
......@@ -556,6 +1116,13 @@ int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
goto tables_alloc_fail;
}
/* Allocate the T2 table */
rc = qed_cxt_src_t2_alloc(p_hwfn);
if (rc) {
DP_NOTICE(p_hwfn, "Failed to allocate T2 memory\n");
goto tables_alloc_fail;
}
/* Allocate and initialize the acquired cids bitmaps */
rc = qed_cid_map_alloc(p_hwfn);
if (rc) {
......@@ -576,6 +1143,7 @@ void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
return;
qed_cid_map_free(p_hwfn);
qed_cxt_src_t2_free(p_hwfn);
qed_ilt_shadow_free(p_hwfn);
kfree(p_hwfn->p_cxt_mngr);
......@@ -620,6 +1188,48 @@ void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
#define CDUC_NCIB_MASK \
(CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
#define CDUT_TYPE0_CXT_SIZE_SHIFT \
CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
#define CDUT_TYPE0_CXT_SIZE_MASK \
(CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
CDUT_TYPE0_CXT_SIZE_SHIFT)
#define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
#define CDUT_TYPE0_BLOCK_WASTE_MASK \
(CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
CDUT_TYPE0_BLOCK_WASTE_SHIFT)
#define CDUT_TYPE0_NCIB_SHIFT \
CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
#define CDUT_TYPE0_NCIB_MASK \
(CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
CDUT_TYPE0_NCIB_SHIFT)
#define CDUT_TYPE1_CXT_SIZE_SHIFT \
CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
#define CDUT_TYPE1_CXT_SIZE_MASK \
(CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
CDUT_TYPE1_CXT_SIZE_SHIFT)
#define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
#define CDUT_TYPE1_BLOCK_WASTE_MASK \
(CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
CDUT_TYPE1_BLOCK_WASTE_SHIFT)
#define CDUT_TYPE1_NCIB_SHIFT \
CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
#define CDUT_TYPE1_NCIB_MASK \
(CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
CDUT_TYPE1_NCIB_SHIFT)
static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
{
u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
......@@ -634,6 +1244,92 @@ static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
/* CDUT - type-0 tasks configuration */
page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
/* cxt size and block-waste are multipes of 8 */
cdu_params = 0;
SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
/* CDUT - type-1 tasks configuration */
cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
/* cxt size and block-waste are multipes of 8 */
cdu_params = 0;
SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
}
/* CDU PF */
#define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
#define CDU_SEG_REG_TYPE_MASK 0x1
#define CDU_SEG_REG_OFFSET_SHIFT 0
#define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
{
struct qed_ilt_client_cfg *p_cli;
struct qed_tid_seg *p_seg;
u32 cdu_seg_params, offset;
int i;
static const u32 rt_type_offset_arr[] = {
CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
};
static const u32 rt_type_offset_fl_arr[] = {
CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
};
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
/* There are initializations only for CDUT during pf Phase */
for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
/* Segment 0 */
p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
if (!p_seg)
continue;
/* Note: start_line is already adjusted for the CDU
* segment register granularity, so we just need to
* divide. Adjustment is implicit as we assume ILT
* Page size is larger than 32K!
*/
offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
(p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
cdu_seg_params = 0;
SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
(p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
cdu_seg_params = 0;
SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
}
}
void qed_qm_init_pf(struct qed_hwfn *p_hwfn)
......@@ -742,14 +1438,11 @@ static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
ilt_clients = p_hwfn->p_cxt_mngr->clients;
for_each_ilt_valid_client(i, ilt_clients) {
if (!ilt_clients[i].active)
continue;
STORE_RT_REG(p_hwfn,
ilt_clients[i].first.reg,
ilt_clients[i].first.val);
STORE_RT_REG(p_hwfn,
ilt_clients[i].last.reg,
ilt_clients[i].last.val);
ilt_clients[i].last.reg, ilt_clients[i].last.val);
STORE_RT_REG(p_hwfn,
ilt_clients[i].p_size.reg,
ilt_clients[i].p_size.val);
......@@ -786,6 +1479,33 @@ static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
p_cli->vf_total_lines);
}
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
if (p_cli->active) {
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
blk_factor);
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
p_cli->pf_total_lines);
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
p_cli->vf_total_lines);
}
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
if (p_cli->active) {
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
p_cli->pf_total_lines);
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
p_cli->vf_total_lines);
}
}
/* ILT (PSWRQ2) PF */
......@@ -804,9 +1524,6 @@ static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
clients = p_hwfn->p_cxt_mngr->clients;
for_each_ilt_valid_client(i, clients) {
if (!clients[i].active)
continue;
/** Client's 1st val and RT array are absolute, ILT shadows'
* lines are relative.
*/
......@@ -837,6 +1554,137 @@ static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
}
}
/* SRC (Searcher) PF */
static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
u32 rounded_conn_num, conn_num, conn_max;
struct qed_src_iids src_iids;
memset(&src_iids, 0, sizeof(src_iids));
qed_cxt_src_iids(p_mngr, &src_iids);
conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
if (!conn_num)
return;
conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
rounded_conn_num = roundup_pow_of_two(conn_max);
STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
ilog2(rounded_conn_num));
STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
p_hwfn->p_cxt_mngr->first_free);
STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
p_hwfn->p_cxt_mngr->last_free);
}
/* Timers PF */
#define TM_CFG_NUM_IDS_SHIFT 0
#define TM_CFG_NUM_IDS_MASK 0xFFFFULL
#define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
#define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
#define TM_CFG_PARENT_PF_SHIFT 25
#define TM_CFG_PARENT_PF_MASK 0x7ULL
#define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
#define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
#define TM_CFG_TID_OFFSET_SHIFT 30
#define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
#define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
#define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
u32 active_seg_mask = 0, tm_offset, rt_reg;
struct qed_tm_iids tm_iids;
u64 cfg_word;
u8 i;
memset(&tm_iids, 0, sizeof(tm_iids));
qed_cxt_tm_iids(p_mngr, &tm_iids);
/* @@@TBD No pre-scan for now */
/* Note: We assume consecutive VFs for a PF */
for (i = 0; i < p_mngr->vf_count; i++) {
cfg_word = 0;
SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
(sizeof(cfg_word) / sizeof(u32)) *
(p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
}
cfg_word = 0;
SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
(sizeof(cfg_word) / sizeof(u32)) *
(NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
/* enale scan */
STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
tm_iids.pf_cids ? 0x1 : 0x0);
/* @@@TBD how to enable the scan for the VFs */
tm_offset = tm_iids.per_vf_cids;
/* Note: We assume consecutive VFs for a PF */
for (i = 0; i < p_mngr->vf_count; i++) {
cfg_word = 0;
SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
(sizeof(cfg_word) / sizeof(u32)) *
(p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
}
tm_offset = tm_iids.pf_cids;
for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
cfg_word = 0;
SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
(sizeof(cfg_word) / sizeof(u32)) *
(NUM_OF_VFS(p_hwfn->cdev) +
p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
tm_offset += tm_iids.pf_tids[i];
}
if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE)
active_seg_mask = 0;
STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
/* @@@TBD how to enable the scan for the VFs */
}
void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
{
qed_cdu_init_common(p_hwfn);
......@@ -847,7 +1695,10 @@ void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
qed_qm_init_pf(p_hwfn);
qed_cm_init_pf(p_hwfn);
qed_dq_init_pf(p_hwfn);
qed_cdu_init_pf(p_hwfn);
qed_ilt_init_pf(p_hwfn);
qed_src_init_pf(p_hwfn);
qed_tm_init_pf(p_hwfn);
}
int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
......@@ -968,17 +1819,439 @@ int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn,
return 0;
}
int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
struct qed_rdma_pf_params *p_params)
{
struct qed_eth_pf_params *p_params = &p_hwfn->pf_params.eth_pf_params;
u32 num_cons, num_tasks, num_qps, num_mrs, num_srqs;
enum protocol_type proto;
num_mrs = min_t(u32, RDMA_MAX_TIDS, p_params->num_mrs);
num_tasks = num_mrs; /* each mr uses a single task id */
num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
switch (p_hwfn->hw_info.personality) {
case QED_PCI_ETH_ROCE:
num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
num_cons = num_qps * 2; /* each QP requires two connections */
proto = PROTOCOLID_ROCE;
break;
default:
return;
}
if (num_cons && num_tasks) {
qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
/* Deliberatly passing ROCE for tasks id. This is because
* iWARP / RoCE share the task id.
*/
qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
QED_CXT_ROCE_TID_SEG, 1,
num_tasks, false);
qed_cxt_set_srq_count(p_hwfn, num_srqs);
} else {
DP_INFO(p_hwfn->cdev,
"RDMA personality used without setting params!\n");
}
}
int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
{
/* Set the number of required CORE connections */
u32 core_cids = 1; /* SPQ */
qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
p_params->num_cons, 1);
switch (p_hwfn->hw_info.personality) {
case QED_PCI_ETH_ROCE:
{
qed_rdma_set_pf_params(p_hwfn,
&p_hwfn->
pf_params.rdma_pf_params);
/* no need for break since RoCE coexist with Ethernet */
}
case QED_PCI_ETH:
{
struct qed_eth_pf_params *p_params =
&p_hwfn->pf_params.eth_pf_params;
qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
p_params->num_cons, 1);
break;
}
case QED_PCI_ISCSI:
{
struct qed_iscsi_pf_params *p_params;
p_params = &p_hwfn->pf_params.iscsi_pf_params;
if (p_params->num_cons && p_params->num_tasks) {
qed_cxt_set_proto_cid_count(p_hwfn,
PROTOCOLID_ISCSI,
p_params->num_cons,
0);
qed_cxt_set_proto_tid_count(p_hwfn,
PROTOCOLID_ISCSI,
QED_CXT_ISCSI_TID_SEG,
0,
p_params->num_tasks,
true);
} else {
DP_INFO(p_hwfn->cdev,
"Iscsi personality used without setting params!\n");
}
break;
}
default:
return -EINVAL;
}
return 0;
}
int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
struct qed_tid_mem *p_info)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
u32 proto, seg, total_lines, i, shadow_line;
struct qed_ilt_client_cfg *p_cli;
struct qed_ilt_cli_blk *p_fl_seg;
struct qed_tid_seg *p_seg_info;
/* Verify the personality */
switch (p_hwfn->hw_info.personality) {
case QED_PCI_ISCSI:
proto = PROTOCOLID_ISCSI;
seg = QED_CXT_ISCSI_TID_SEG;
break;
default:
return -EINVAL;
}
p_cli = &p_mngr->clients[ILT_CLI_CDUT];
if (!p_cli->active)
return -EINVAL;
p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
if (!p_seg_info->has_fl_mem)
return -EINVAL;
p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
p_fl_seg->real_size_in_page);
for (i = 0; i < total_lines; i++) {
shadow_line = i + p_fl_seg->start_line -
p_hwfn->p_cxt_mngr->pf_start_line;
p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
}
p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
p_fl_seg->real_size_in_page;
p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
p_info->tid_size;
return 0;
}
/* This function is very RoCE oriented, if another protocol in the future
* will want this feature we'll need to modify the function to be more generic
*/
int
qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
enum qed_cxt_elem_type elem_type, u32 iid)
{
u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
struct qed_ilt_client_cfg *p_cli;
struct qed_ilt_cli_blk *p_blk;
struct qed_ptt *p_ptt;
dma_addr_t p_phys;
u64 ilt_hw_entry;
void *p_virt;
int rc = 0;
switch (elem_type) {
case QED_ELEM_CXT:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
elem_size = CONN_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUC_BLK];
break;
case QED_ELEM_SRQ:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
elem_size = SRQ_CXT_SIZE;
p_blk = &p_cli->pf_blks[SRQ_BLK];
break;
case QED_ELEM_TASK:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
break;
default:
DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
return -EINVAL;
}
/* Calculate line in ilt */
hw_p_size = p_cli->p_size.val;
elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
line = p_blk->start_line + (iid / elems_per_p);
shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
/* If line is already allocated, do nothing, otherwise allocate it and
* write it to the PSWRQ2 registers.
* This section can be run in parallel from different contexts and thus
* a mutex protection is needed.
*/
mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
goto out0;
p_ptt = qed_ptt_acquire(p_hwfn);
if (!p_ptt) {
DP_NOTICE(p_hwfn,
"QED_TIME_OUT on ptt acquire - dynamic allocation");
rc = -EBUSY;
goto out0;
}
p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
p_blk->real_size_in_page,
&p_phys, GFP_KERNEL);
if (!p_virt) {
rc = -ENOMEM;
goto out1;
}
memset(p_virt, 0, p_blk->real_size_in_page);
/* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
* to compensate for a HW bug, but it is configured even if DIF is not
* enabled. This is harmless and allows us to avoid a dedicated API. We
* configure the field for all of the contexts on the newly allocated
* page.
*/
if (elem_type == QED_ELEM_TASK) {
u32 elem_i;
u8 *elem_start = (u8 *)p_virt;
union type1_task_context *elem;
for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
elem = (union type1_task_context *)elem_start;
SET_FIELD(elem->roce_ctx.tdif_context.flags1,
TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
}
}
p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
p_blk->real_size_in_page;
/* compute absolute offset */
reg_offset = PSWRQ2_REG_ILT_MEMORY +
(line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
ilt_hw_entry = 0;
SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
SET_FIELD(ilt_hw_entry,
ILT_ENTRY_PHY_ADDR,
(p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
if (elem_type == QED_ELEM_CXT) {
u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
elems_per_p;
/* Update the relevant register in the parser */
qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
last_cid_allocated - 1);
if (!p_hwfn->b_rdma_enabled_in_prs) {
/* Enable RoCE search */
qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
p_hwfn->b_rdma_enabled_in_prs = true;
}
}
out1:
qed_ptt_release(p_hwfn, p_ptt);
out0:
mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
return rc;
}
/* This function is very RoCE oriented, if another protocol in the future
* will want this feature we'll need to modify the function to be more generic
*/
static int
qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
enum qed_cxt_elem_type elem_type,
u32 start_iid, u32 count)
{
u32 start_line, end_line, shadow_start_line, shadow_end_line;
u32 reg_offset, elem_size, hw_p_size, elems_per_p;
struct qed_ilt_client_cfg *p_cli;
struct qed_ilt_cli_blk *p_blk;
u32 end_iid = start_iid + count;
struct qed_ptt *p_ptt;
u64 ilt_hw_entry = 0;
u32 i;
switch (elem_type) {
case QED_ELEM_CXT:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
elem_size = CONN_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUC_BLK];
break;
case QED_ELEM_SRQ:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
elem_size = SRQ_CXT_SIZE;
p_blk = &p_cli->pf_blks[SRQ_BLK];
break;
case QED_ELEM_TASK:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
break;
default:
DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
return -EINVAL;
}
/* Calculate line in ilt */
hw_p_size = p_cli->p_size.val;
elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
start_line = p_blk->start_line + (start_iid / elems_per_p);
end_line = p_blk->start_line + (end_iid / elems_per_p);
if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
end_line--;
shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
p_ptt = qed_ptt_acquire(p_hwfn);
if (!p_ptt) {
DP_NOTICE(p_hwfn,
"QED_TIME_OUT on ptt acquire - dynamic allocation");
return -EBUSY;
}
for (i = shadow_start_line; i < shadow_end_line; i++) {
if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
continue;
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
/* compute absolute offset */
reg_offset = PSWRQ2_REG_ILT_MEMORY +
((start_line++) * ILT_REG_SIZE_IN_BYTES *
ILT_ENTRY_IN_REGS);
/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
* wide-bus.
*/
qed_dmae_host2grc(p_hwfn, p_ptt,
(u64) (uintptr_t) &ilt_hw_entry,
reg_offset,
sizeof(ilt_hw_entry) / sizeof(u32),
0);
}
qed_ptt_release(p_hwfn, p_ptt);
return 0;
}
int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
{
int rc;
u32 cid;
/* Free Connection CXT */
rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
qed_cxt_get_proto_cid_start(p_hwfn,
proto),
qed_cxt_get_proto_cid_count(p_hwfn,
proto, &cid));
if (rc)
return rc;
/* Free Task CXT */
rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
qed_cxt_get_proto_tid_count(p_hwfn, proto));
if (rc)
return rc;
/* Free TSDM CXT */
rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
qed_cxt_get_srq_count(p_hwfn));
return rc;
}
int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
u32 tid, u8 ctx_type, void **pp_task_ctx)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
struct qed_ilt_client_cfg *p_cli;
struct qed_ilt_cli_blk *p_seg;
struct qed_tid_seg *p_seg_info;
u32 proto, seg;
u32 total_lines;
u32 tid_size, ilt_idx;
u32 num_tids_per_block;
/* Verify the personality */
switch (p_hwfn->hw_info.personality) {
case QED_PCI_ISCSI:
proto = PROTOCOLID_ISCSI;
seg = QED_CXT_ISCSI_TID_SEG;
break;
default:
return -EINVAL;
}
p_cli = &p_mngr->clients[ILT_CLI_CDUT];
if (!p_cli->active)
return -EINVAL;
p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
if (ctx_type == QED_CTX_WORKING_MEM) {
p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
} else if (ctx_type == QED_CTX_FL_MEM) {
if (!p_seg_info->has_fl_mem)
return -EINVAL;
p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
} else {
return -EINVAL;
}
total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
tid_size = p_mngr->task_type_size[p_seg_info->type];
num_tids_per_block = p_seg->real_size_in_page / tid_size;
if (total_lines < tid / num_tids_per_block)
return -EINVAL;
ilt_idx = tid / num_tids_per_block + p_seg->start_line -
p_mngr->pf_start_line;
*pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
(tid % num_tids_per_block) * tid_size;
return 0;
}
drivers/net/ethernet/qlogic/qed/qed_cxt.h
View file @ 03c7f70b
......@@ -21,6 +21,14 @@ struct qed_cxt_info {
enum protocol_type type;
};
#define MAX_TID_BLOCKS 512
struct qed_tid_mem {
u32 tid_size;
u32 num_tids_per_block;
u32 waste;
u8 *blocks[MAX_TID_BLOCKS]; /* 4K */
};
/**
* @brief qed_cxt_acquire - Acquire a new cid of a specific protocol type
*
......@@ -46,8 +54,22 @@ int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn,
struct qed_cxt_info *p_info);
/**
* @brief qed_cxt_get_tid_mem_info
*
* @param p_hwfn
* @param p_info
*
* @return int
*/
int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
struct qed_tid_mem *p_info);
#define QED_CXT_ISCSI_TID_SEG PROTOCOLID_ISCSI
#define QED_CXT_ROCE_TID_SEG PROTOCOLID_ROCE
enum qed_cxt_elem_type {
QED_ELEM_CXT,
QED_ELEM_SRQ,
QED_ELEM_TASK
};
......@@ -149,4 +171,6 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
void qed_cxt_release_cid(struct qed_hwfn *p_hwfn,
u32 cid);
#define QED_CTX_WORKING_MEM 0
#define QED_CTX_FL_MEM 1
#endif
drivers/net/ethernet/qlogic/qed/qed_dev.c
View file @ 03c7f70b
......@@ -17,6 +17,7 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/vmalloc.h>
#include <linux/etherdevice.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_if.h>
......@@ -160,9 +161,13 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
struct qed_qm_info *qm_info = &p_hwfn->qm_info;
struct init_qm_port_params *p_qm_port;
bool init_rdma_offload_pq = false;
bool init_pure_ack_pq = false;
bool init_ooo_pq = false;
u16 num_pqs, multi_cos_tcs = 1;
u8 pf_wfq = qm_info->pf_wfq;
u32 pf_rl = qm_info->pf_rl;
u16 num_pf_rls = 0;
u16 num_vfs = 0;
#ifdef CONFIG_QED_SRIOV
......@@ -174,6 +179,25 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
num_pqs++; /* for RoCE queue */
init_rdma_offload_pq = true;
/* we subtract num_vfs because each require a rate limiter,
* and one default rate limiter
*/
if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
num_pqs += num_pf_rls;
qm_info->num_pf_rls = (u8) num_pf_rls;
}
if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
init_pure_ack_pq = true;
init_ooo_pq = true;
}
/* Sanity checking that setup requires legal number of resources */
if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
DP_ERR(p_hwfn,
......@@ -211,12 +235,22 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
/* First init rate limited queues */
for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
qm_info->qm_pq_params[curr_queue].tc_id =
p_hwfn->hw_info.non_offload_tc;
qm_info->qm_pq_params[curr_queue].wrr_group = 1;
qm_info->qm_pq_params[curr_queue].rl_valid = 1;
}
/* First init per-TC PQs */
for (i = 0; i < multi_cos_tcs; i++) {
struct init_qm_pq_params *params =
&qm_info->qm_pq_params[curr_queue++];
if (p_hwfn->hw_info.personality == QED_PCI_ETH) {
if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
p_hwfn->hw_info.personality == QED_PCI_ETH) {
params->vport_id = vport_id;
params->tc_id = p_hwfn->hw_info.non_offload_tc;
params->wrr_group = 1;
......@@ -236,6 +270,32 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
curr_queue++;
qm_info->offload_pq = 0;
if (init_rdma_offload_pq) {
qm_info->offload_pq = curr_queue;
qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
qm_info->qm_pq_params[curr_queue].tc_id =
p_hwfn->hw_info.offload_tc;
qm_info->qm_pq_params[curr_queue].wrr_group = 1;
curr_queue++;
}
if (init_pure_ack_pq) {
qm_info->pure_ack_pq = curr_queue;
qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
qm_info->qm_pq_params[curr_queue].tc_id =
p_hwfn->hw_info.offload_tc;
qm_info->qm_pq_params[curr_queue].wrr_group = 1;
curr_queue++;
}
if (init_ooo_pq) {
qm_info->ooo_pq = curr_queue;
qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
qm_info->qm_pq_params[curr_queue].wrr_group = 1;
curr_queue++;
}
/* Then init per-VF PQs */
vf_offset = curr_queue;
for (i = 0; i < num_vfs; i++) {
......@@ -370,21 +430,20 @@ int qed_resc_alloc(struct qed_dev *cdev)
if (!p_hwfn->p_tx_cids) {
DP_NOTICE(p_hwfn,
"Failed to allocate memory for Tx Cids\n");
rc = -ENOMEM;
goto alloc_err;
goto alloc_no_mem;
}
p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
if (!p_hwfn->p_rx_cids) {
DP_NOTICE(p_hwfn,
"Failed to allocate memory for Rx Cids\n");
rc = -ENOMEM;
goto alloc_err;
goto alloc_no_mem;
}
}
for_each_hwfn(cdev, i) {
struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
u32 n_eqes, num_cons;
/* First allocate the context manager structure */
rc = qed_cxt_mngr_alloc(p_hwfn);
......@@ -433,18 +492,34 @@ int qed_resc_alloc(struct qed_dev *cdev)
goto alloc_err;
/* EQ */
p_eq = qed_eq_alloc(p_hwfn, 256);
if (!p_eq) {
rc = -ENOMEM;
n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
PROTOCOLID_ROCE,
0) * 2;
n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
} else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
num_cons =
qed_cxt_get_proto_cid_count(p_hwfn,
PROTOCOLID_ISCSI, 0);
n_eqes += 2 * num_cons;
}
if (n_eqes > 0xFFFF) {
DP_ERR(p_hwfn,
"Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
n_eqes, 0xFFFF);
goto alloc_err;
}
p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
if (!p_eq)
goto alloc_no_mem;
p_hwfn->p_eq = p_eq;
p_consq = qed_consq_alloc(p_hwfn);
if (!p_consq) {
rc = -ENOMEM;
goto alloc_err;
}
if (!p_consq)
goto alloc_no_mem;
p_hwfn->p_consq = p_consq;
/* DMA info initialization */
......@@ -473,6 +548,8 @@ int qed_resc_alloc(struct qed_dev *cdev)
return 0;
alloc_no_mem:
rc = -ENOMEM;
alloc_err:
qed_resc_free(cdev);
return rc;
......@@ -638,6 +715,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
struct qed_qm_info *qm_info = &p_hwfn->qm_info;
struct qed_qm_common_rt_init_params params;
struct qed_dev *cdev = p_hwfn->cdev;
u16 num_pfs, pf_id;
u32 concrete_fid;
int rc = 0;
u8 vf_id;
......@@ -686,9 +764,16 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
/* Disable relaxed ordering in the PCI config space */
qed_wr(p_hwfn, p_ptt, 0x20b4,
qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
if (QED_IS_BB(p_hwfn->cdev)) {
num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
for (pf_id = 0; pf_id < num_pfs; pf_id++) {
qed_fid_pretend(p_hwfn, p_ptt, pf_id);
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
}
/* pretend to original PF */
qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
}
for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
......@@ -778,7 +863,8 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
}
/* Protocl Configuration */
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
(p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
......@@ -1255,8 +1341,9 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
num_features);
}
static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
{
u8 enabled_func_idx = p_hwfn->enabled_func_idx;
u32 *resc_start = p_hwfn->hw_info.resc_start;
u8 num_funcs = p_hwfn->num_funcs_on_engine;
u32 *resc_num = p_hwfn->hw_info.resc_num;
......@@ -1280,14 +1367,22 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
resc_num[QED_RL] = 8;
resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
num_funcs;
resc_num[QED_ILT] = 950;
resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
for (i = 0; i < QED_MAX_RESC; i++)
resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
resc_start[i] = resc_num[i] * enabled_func_idx;
/* Sanity for ILT */
if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
RESC_START(p_hwfn, QED_ILT),
RESC_END(p_hwfn, QED_ILT) - 1);
return -EINVAL;
}
qed_hw_set_feat(p_hwfn);
......@@ -1317,6 +1412,8 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
p_hwfn->hw_info.resc_start[QED_VLAN],
p_hwfn->hw_info.resc_num[QED_ILT],
p_hwfn->hw_info.resc_start[QED_ILT]);
return 0;
}
static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
......@@ -1471,14 +1568,20 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
__set_bit(QED_DEV_CAP_ETH,
&p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
__set_bit(QED_DEV_CAP_ISCSI,
&p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
__set_bit(QED_DEV_CAP_ROCE,
&p_hwfn->hw_info.device_capabilities);
return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
}
static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
u32 reg_function_hide, tmp, eng_mask;
u8 num_funcs;
u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
num_funcs = MAX_NUM_PFS_BB;
......@@ -1508,9 +1611,19 @@ static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
num_funcs++;
tmp >>= 0x1;
}
/* Get the PF index within the enabled functions */
low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
tmp = reg_function_hide & eng_mask & low_pfs_mask;
while (tmp) {
if (tmp & 0x1)
enabled_func_idx--;
tmp >>= 0x1;
}
}
p_hwfn->num_funcs_on_engine = num_funcs;
p_hwfn->enabled_func_idx = enabled_func_idx;
DP_VERBOSE(p_hwfn,
NETIF_MSG_PROBE,
......@@ -1580,9 +1693,7 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
qed_get_num_funcs(p_hwfn, p_ptt);
qed_hw_get_resc(p_hwfn);
return rc;
return qed_hw_get_resc(p_hwfn);
}
static int qed_get_dev_info(struct qed_dev *cdev)
......@@ -1779,92 +1890,285 @@ void qed_hw_remove(struct qed_dev *cdev)
qed_iov_free_hw_info(cdev);
}
int qed_chain_alloc(struct qed_dev *cdev,
enum qed_chain_use_mode intended_use,
enum qed_chain_mode mode,
u16 num_elems,
size_t elem_size,
struct qed_chain *p_chain)
static void qed_chain_free_next_ptr(struct qed_dev *cdev,
struct qed_chain *p_chain)
{
void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
struct qed_chain_next *p_next;
u32 size, i;
if (!p_virt)
return;
size = p_chain->elem_size * p_chain->usable_per_page;
for (i = 0; i < p_chain->page_cnt; i++) {
if (!p_virt)
break;
p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
p_virt_next = p_next->next_virt;
p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
dma_free_coherent(&cdev->pdev->dev,
QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
p_virt = p_virt_next;
p_phys = p_phys_next;
}
}
static void qed_chain_free_single(struct qed_dev *cdev,
struct qed_chain *p_chain)
{
if (!p_chain->p_virt_addr)
return;
dma_free_coherent(&cdev->pdev->dev,
QED_CHAIN_PAGE_SIZE,
p_chain->p_virt_addr, p_chain->p_phys_addr);
}
static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
{
void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
u32 page_cnt = p_chain->page_cnt, i, pbl_size;
u8 *p_pbl_virt = p_chain->pbl.p_virt_table;
if (!pp_virt_addr_tbl)
return;
if (!p_chain->pbl.p_virt_table)
goto out;
for (i = 0; i < page_cnt; i++) {
if (!pp_virt_addr_tbl[i])
break;
dma_free_coherent(&cdev->pdev->dev,
QED_CHAIN_PAGE_SIZE,
pp_virt_addr_tbl[i],
*(dma_addr_t *)p_pbl_virt);
p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
}
pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
dma_free_coherent(&cdev->pdev->dev,
pbl_size,
p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table);
out:
vfree(p_chain->pbl.pp_virt_addr_tbl);
}
void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
{
switch (p_chain->mode) {
case QED_CHAIN_MODE_NEXT_PTR:
qed_chain_free_next_ptr(cdev, p_chain);
break;
case QED_CHAIN_MODE_SINGLE:
qed_chain_free_single(cdev, p_chain);
break;
case QED_CHAIN_MODE_PBL:
qed_chain_free_pbl(cdev, p_chain);
break;
}
}
static int
qed_chain_alloc_sanity_check(struct qed_dev *cdev,
enum qed_chain_cnt_type cnt_type,
size_t elem_size, u32 page_cnt)
{
u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
/* The actual chain size can be larger than the maximal possible value
* after rounding up the requested elements number to pages, and after
* taking into acount the unusuable elements (next-ptr elements).
* The size of a "u16" chain can be (U16_MAX + 1) since the chain
* size/capacity fields are of a u32 type.
*/
if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
chain_size > 0x10000) ||
(cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
chain_size > 0x100000000ULL)) {
DP_NOTICE(cdev,
"The actual chain size (0x%llx) is larger than the maximal possible value\n",
chain_size);
return -EINVAL;
}
return 0;
}
static int
qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
{
dma_addr_t p_pbl_phys = 0;
void *p_pbl_virt = NULL;
void *p_virt = NULL, *p_virt_prev = NULL;
dma_addr_t p_phys = 0;
void *p_virt = NULL;
u16 page_cnt = 0;
size_t size;
u32 i;
if (mode == QED_CHAIN_MODE_SINGLE)
page_cnt = 1;
else
page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
for (i = 0; i < p_chain->page_cnt; i++) {
p_virt = dma_alloc_coherent(&cdev->pdev->dev,
QED_CHAIN_PAGE_SIZE,
&p_phys, GFP_KERNEL);
if (!p_virt) {
DP_NOTICE(cdev, "Failed to allocate chain memory\n");
return -ENOMEM;
}
if (i == 0) {
qed_chain_init_mem(p_chain, p_virt, p_phys);
qed_chain_reset(p_chain);
} else {
qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
p_virt, p_phys);
}
p_virt_prev = p_virt;
}
/* Last page's next element should point to the beginning of the
* chain.
*/
qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
p_chain->p_virt_addr,
p_chain->p_phys_addr);
return 0;
}
static int
qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
{
dma_addr_t p_phys = 0;
void *p_virt = NULL;
size = page_cnt * QED_CHAIN_PAGE_SIZE;
p_virt = dma_alloc_coherent(&cdev->pdev->dev,
size, &p_phys, GFP_KERNEL);
QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
if (!p_virt) {
DP_NOTICE(cdev, "Failed to allocate chain mem\n");
goto nomem;
DP_NOTICE(cdev, "Failed to allocate chain memory\n");
return -ENOMEM;
}
if (mode == QED_CHAIN_MODE_PBL) {
size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
size, &p_pbl_phys,
GFP_KERNEL);
if (!p_pbl_virt) {
DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n");
goto nomem;
}
qed_chain_init_mem(p_chain, p_virt, p_phys);
qed_chain_reset(p_chain);
qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt,
(u8)elem_size, intended_use,
p_pbl_phys, p_pbl_virt);
} else {
qed_chain_init(p_chain, p_virt, p_phys, page_cnt,
(u8)elem_size, intended_use, mode);
return 0;
}
static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
{
u32 page_cnt = p_chain->page_cnt, size, i;
dma_addr_t p_phys = 0, p_pbl_phys = 0;
void **pp_virt_addr_tbl = NULL;
u8 *p_pbl_virt = NULL;
void *p_virt = NULL;
size = page_cnt * sizeof(*pp_virt_addr_tbl);
pp_virt_addr_tbl = vmalloc(size);
if (!pp_virt_addr_tbl) {
DP_NOTICE(cdev,
"Failed to allocate memory for the chain virtual addresses table\n");
return -ENOMEM;
}
memset(pp_virt_addr_tbl, 0, size);
return 0;
/* The allocation of the PBL table is done with its full size, since it
* is expected to be successive.
* qed_chain_init_pbl_mem() is called even in a case of an allocation
* failure, since pp_virt_addr_tbl was previously allocated, and it
* should be saved to allow its freeing during the error flow.
*/
size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
size, &p_pbl_phys, GFP_KERNEL);
qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
pp_virt_addr_tbl);
if (!p_pbl_virt) {
DP_NOTICE(cdev, "Failed to allocate chain pbl memory\n");
return -ENOMEM;
}
nomem:
dma_free_coherent(&cdev->pdev->dev,
page_cnt * QED_CHAIN_PAGE_SIZE,
p_virt, p_phys);
dma_free_coherent(&cdev->pdev->dev,
page_cnt * QED_CHAIN_PBL_ENTRY_SIZE,
p_pbl_virt, p_pbl_phys);
for (i = 0; i < page_cnt; i++) {
p_virt = dma_alloc_coherent(&cdev->pdev->dev,
QED_CHAIN_PAGE_SIZE,
&p_phys, GFP_KERNEL);
if (!p_virt) {
DP_NOTICE(cdev, "Failed to allocate chain memory\n");
return -ENOMEM;
}
return -ENOMEM;
if (i == 0) {
qed_chain_init_mem(p_chain, p_virt, p_phys);
qed_chain_reset(p_chain);
}
/* Fill the PBL table with the physical address of the page */
*(dma_addr_t *)p_pbl_virt = p_phys;
/* Keep the virtual address of the page */
p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
}
return 0;
}
void qed_chain_free(struct qed_dev *cdev,
struct qed_chain *p_chain)
int qed_chain_alloc(struct qed_dev *cdev,
enum qed_chain_use_mode intended_use,
enum qed_chain_mode mode,
enum qed_chain_cnt_type cnt_type,
u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
{
size_t size;
u32 page_cnt;
int rc = 0;
if (!p_chain->p_virt_addr)
return;
if (mode == QED_CHAIN_MODE_SINGLE)
page_cnt = 1;
else
page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
if (rc) {
DP_NOTICE(cdev,
"Cannot allocate a chain with the given arguments:\n"
"[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
intended_use, mode, cnt_type, num_elems, elem_size);
return rc;
}
qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
mode, cnt_type);
if (p_chain->mode == QED_CHAIN_MODE_PBL) {
size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
dma_free_coherent(&cdev->pdev->dev, size,
p_chain->pbl.p_virt_table,
p_chain->pbl.p_phys_table);
switch (mode) {
case QED_CHAIN_MODE_NEXT_PTR:
rc = qed_chain_alloc_next_ptr(cdev, p_chain);
break;
case QED_CHAIN_MODE_SINGLE:
rc = qed_chain_alloc_single(cdev, p_chain);
break;
case QED_CHAIN_MODE_PBL:
rc = qed_chain_alloc_pbl(cdev, p_chain);
break;
}
if (rc)
goto nomem;
return 0;
size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE;
dma_free_coherent(&cdev->pdev->dev, size,
p_chain->p_virt_addr,
p_chain->p_phys_addr);
nomem:
qed_chain_free(cdev, p_chain);
return rc;
}
int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
u16 src_id, u16 *dst_id)
int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
{
if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
u16 min, max;
min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
DP_NOTICE(p_hwfn,
"l2_queue id [%d] is not valid, available indices [%d - %d]\n",
......
drivers/net/ethernet/qlogic/qed/qed_dev_api.h
View file @ 03c7f70b
......@@ -245,9 +245,8 @@ int
qed_chain_alloc(struct qed_dev *cdev,
enum qed_chain_use_mode intended_use,
enum qed_chain_mode mode,
u16 num_elems,
size_t elem_size,
struct qed_chain *p_chain);
enum qed_chain_cnt_type cnt_type,
u32 num_elems, size_t elem_size, struct qed_chain *p_chain);
/**
* @brief qed_chain_free - Free chain DMA memory
......@@ -255,8 +254,7 @@ qed_chain_alloc(struct qed_dev *cdev,
* @param p_hwfn
* @param p_chain
*/
void qed_chain_free(struct qed_dev *cdev,
struct qed_chain *p_chain);
void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain);
/**
* @@brief qed_fw_l2_queue - Get absolute L2 queue ID
......
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View file @ 03c7f70b
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/net/ethernet/qlogic/qed/qed_hw.c
View file @ 03c7f70b
......@@ -791,16 +791,16 @@ qed_dmae_host2host(struct qed_hwfn *p_hwfn,
}
u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
enum protocol_type proto,
union qed_qm_pq_params *p_params)
enum protocol_type proto, union qed_qm_pq_params *p_params)
{
u16 pq_id = 0;
if ((proto == PROTOCOLID_CORE || proto == PROTOCOLID_ETH) &&
!p_params) {
if ((proto == PROTOCOLID_CORE ||
proto == PROTOCOLID_ETH ||
proto == PROTOCOLID_ISCSI ||
proto == PROTOCOLID_ROCE) && !p_params) {
DP_NOTICE(p_hwfn,
"Protocol %d received NULL PQ params\n",
proto);
"Protocol %d received NULL PQ params\n", proto);
return 0;
}
......@@ -808,6 +808,8 @@ u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
case PROTOCOLID_CORE:
if (p_params->core.tc == LB_TC)
pq_id = p_hwfn->qm_info.pure_lb_pq;
else if (p_params->core.tc == OOO_LB_TC)
pq_id = p_hwfn->qm_info.ooo_pq;
else
pq_id = p_hwfn->qm_info.offload_pq;
break;
......@@ -817,6 +819,18 @@ u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
pq_id += p_hwfn->qm_info.vf_queues_offset +
p_params->eth.vf_id;
break;
case PROTOCOLID_ISCSI:
if (p_params->iscsi.q_idx == 1)
pq_id = p_hwfn->qm_info.pure_ack_pq;
break;
case PROTOCOLID_ROCE:
if (p_params->roce.dcqcn)
pq_id = p_params->roce.qpid;
else
pq_id = p_hwfn->qm_info.offload_pq;
if (pq_id > p_hwfn->qm_info.num_pf_rls)
pq_id = p_hwfn->qm_info.offload_pq;
break;
default:
pq_id = 0;
}
......
drivers/net/ethernet/qlogic/qed/qed_hw.h
View file @ 03c7f70b
......@@ -253,6 +253,10 @@ int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn);
void qed_dmae_info_free(struct qed_hwfn *p_hwfn);
union qed_qm_pq_params {
struct {
u8 q_idx;
} iscsi;
struct {
u8 tc;
} core;
......@@ -262,11 +266,15 @@ union qed_qm_pq_params {
u8 vf_id;
u8 tc;
} eth;
struct {
u8 dcqcn;
u8 qpid; /* roce relative */
} roce;
};
u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
enum protocol_type proto,
union qed_qm_pq_params *params);
enum protocol_type proto, union qed_qm_pq_params *params);
int qed_init_fw_data(struct qed_dev *cdev,
const u8 *fw_data);
......
drivers/net/ethernet/qlogic/qed/qed_main.c
View file @ 03c7f70b
......@@ -207,6 +207,8 @@ int qed_fill_dev_info(struct qed_dev *cdev,
dev_info->pci_mem_start = cdev->pci_params.mem_start;
dev_info->pci_mem_end = cdev->pci_params.mem_end;
dev_info->pci_irq = cdev->pci_params.irq;
dev_info->rdma_supported =
(cdev->hwfns[0].hw_info.personality == QED_PCI_ETH_ROCE);
dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
......@@ -901,7 +903,8 @@ static int qed_slowpath_stop(struct qed_dev *cdev)
if (IS_PF(cdev)) {
qed_free_stream_mem(cdev);
qed_sriov_disable(cdev, true);
if (IS_QED_ETH_IF(cdev))
qed_sriov_disable(cdev, true);
qed_nic_stop(cdev);
qed_slowpath_irq_free(cdev);
......
drivers/net/ethernet/qlogic/qed/qed_mcp.c
View file @ 03c7f70b
......@@ -977,7 +977,18 @@ qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
case FUNC_MF_CFG_PROTOCOL_ETHERNET:
*p_proto = QED_PCI_ETH;
if (test_bit(QED_DEV_CAP_ROCE,
&p_hwfn->hw_info.device_capabilities))
*p_proto = QED_PCI_ETH_ROCE;
else
*p_proto = QED_PCI_ETH;
break;
case FUNC_MF_CFG_PROTOCOL_ISCSI:
*p_proto = QED_PCI_ISCSI;
break;
case FUNC_MF_CFG_PROTOCOL_ROCE:
DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
rc = -EINVAL;
break;
default:
rc = -EINVAL;
......
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
View file @ 03c7f70b
......@@ -27,6 +27,35 @@
#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
0xff << 24)
#define CDU_REG_SEGMENT0_PARAMS \
0x580904UL
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
(0xfff << 0)
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
0
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
(0xff << 16)
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
16
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
(0xff << 24)
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
24
#define CDU_REG_SEGMENT1_PARAMS \
0x580908UL
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
(0xfff << 0)
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
0
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
(0xff << 16)
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
16
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
(0xff << 24)
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
24
#define XSDM_REG_OPERATION_GEN \
0xf80408UL
#define NIG_REG_RX_BRB_OUT_EN \
......@@ -225,6 +254,8 @@
0x1f0000UL
#define PRS_REG_MSG_INFO \
0x1f0a1cUL
#define PRS_REG_ROCE_DEST_QP_MAX_PF \
0x1f0430UL
#define PSDM_REG_ENABLE_IN1 \
0xfa0004UL
#define PSEM_REG_ENABLE_IN \
......@@ -233,6 +264,8 @@
0x280020UL
#define PSWRQ2_REG_CDUT_P_SIZE \
0x24000cUL
#define PSWRQ2_REG_ILT_MEMORY \
0x260000UL
#define PSWHST_REG_DISCARD_INTERNAL_WRITES \
0x2a0040UL
#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
......
drivers/net/ethernet/qlogic/qed/qed_sp.h
View file @ 03c7f70b
......@@ -63,6 +63,32 @@ union ramrod_data {
struct vport_update_ramrod_data vport_update;
struct vport_filter_update_ramrod_data vport_filter_update;
struct rdma_init_func_ramrod_data rdma_init_func;
struct rdma_close_func_ramrod_data rdma_close_func;
struct rdma_register_tid_ramrod_data rdma_register_tid;
struct rdma_deregister_tid_ramrod_data rdma_deregister_tid;
struct roce_create_qp_resp_ramrod_data roce_create_qp_resp;
struct roce_create_qp_req_ramrod_data roce_create_qp_req;
struct roce_modify_qp_resp_ramrod_data roce_modify_qp_resp;
struct roce_modify_qp_req_ramrod_data roce_modify_qp_req;
struct roce_query_qp_resp_ramrod_data roce_query_qp_resp;
struct roce_query_qp_req_ramrod_data roce_query_qp_req;
struct roce_destroy_qp_resp_ramrod_data roce_destroy_qp_resp;
struct roce_destroy_qp_req_ramrod_data roce_destroy_qp_req;
struct rdma_create_cq_ramrod_data rdma_create_cq;
struct rdma_resize_cq_ramrod_data rdma_resize_cq;
struct rdma_destroy_cq_ramrod_data rdma_destroy_cq;
struct rdma_srq_create_ramrod_data rdma_create_srq;
struct rdma_srq_destroy_ramrod_data rdma_destroy_srq;
struct rdma_srq_modify_ramrod_data rdma_modify_srq;
struct iscsi_slow_path_hdr iscsi_empty;
struct iscsi_init_ramrod_params iscsi_init;
struct iscsi_spe_func_dstry iscsi_destroy;
struct iscsi_spe_conn_offload iscsi_conn_offload;
struct iscsi_conn_update_ramrod_params iscsi_conn_update;
struct iscsi_spe_conn_termination iscsi_conn_terminate;
struct vf_start_ramrod_data vf_start;
struct vf_stop_ramrod_data vf_stop;
};
......
drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
View file @ 03c7f70b
......@@ -308,6 +308,7 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
int rc = -EINVAL;
u8 page_cnt;
/* update initial eq producer */
qed_eq_prod_update(p_hwfn,
......@@ -350,18 +351,33 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
/* Place EQ address in RAMROD */
DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
p_hwfn->p_eq->chain.pbl.p_phys_table);
p_ramrod->event_ring_num_pages = (u8)p_hwfn->p_eq->chain.page_cnt;
page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
p_ramrod->event_ring_num_pages = page_cnt;
DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
p_hwfn->p_consq->chain.pbl.p_phys_table);
qed_tunn_set_pf_start_params(p_hwfn, p_tunn,
&p_ramrod->tunnel_config);
p_hwfn->hw_info.personality = PERSONALITY_ETH;
if (IS_MF_SI(p_hwfn))
p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
switch (p_hwfn->hw_info.personality) {
case QED_PCI_ETH:
p_ramrod->personality = PERSONALITY_ETH;
break;
case QED_PCI_ISCSI:
p_ramrod->personality = PERSONALITY_ISCSI;
break;
case QED_PCI_ETH_ROCE:
p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
break;
default:
DP_NOTICE(p_hwfn, "Unkown personality %d\n",
p_hwfn->hw_info.personality);
p_ramrod->personality = PERSONALITY_ETH;
}
if (p_hwfn->cdev->p_iov_info) {
struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
......
drivers/net/ethernet/qlogic/qed/qed_spq.c
View file @ 03c7f70b
......@@ -343,6 +343,7 @@ struct qed_eq *qed_eq_alloc(struct qed_hwfn *p_hwfn,
if (qed_chain_alloc(p_hwfn->cdev,
QED_CHAIN_USE_TO_PRODUCE,
QED_CHAIN_MODE_PBL,
QED_CHAIN_CNT_TYPE_U16,
num_elem,
sizeof(union event_ring_element),
&p_eq->chain)) {
......@@ -416,10 +417,10 @@ int qed_eth_cqe_completion(struct qed_hwfn *p_hwfn,
***************************************************************************/
void qed_spq_setup(struct qed_hwfn *p_hwfn)
{
struct qed_spq *p_spq = p_hwfn->p_spq;
struct qed_spq_entry *p_virt = NULL;
dma_addr_t p_phys = 0;
unsigned int i = 0;
struct qed_spq *p_spq = p_hwfn->p_spq;
struct qed_spq_entry *p_virt = NULL;
dma_addr_t p_phys = 0;
u32 i, capacity;
INIT_LIST_HEAD(&p_spq->pending);
INIT_LIST_HEAD(&p_spq->completion_pending);
......@@ -431,7 +432,8 @@ void qed_spq_setup(struct qed_hwfn *p_hwfn)
p_phys = p_spq->p_phys + offsetof(struct qed_spq_entry, ramrod);
p_virt = p_spq->p_virt;
for (i = 0; i < p_spq->chain.capacity; i++) {
capacity = qed_chain_get_capacity(&p_spq->chain);
for (i = 0; i < capacity; i++) {
DMA_REGPAIR_LE(p_virt->elem.data_ptr, p_phys);
list_add_tail(&p_virt->list, &p_spq->free_pool);
......@@ -459,9 +461,10 @@ void qed_spq_setup(struct qed_hwfn *p_hwfn)
int qed_spq_alloc(struct qed_hwfn *p_hwfn)
{
struct qed_spq *p_spq = NULL;
dma_addr_t p_phys = 0;
struct qed_spq_entry *p_virt = NULL;
struct qed_spq_entry *p_virt = NULL;
struct qed_spq *p_spq = NULL;
dma_addr_t p_phys = 0;
u32 capacity;
/* SPQ struct */
p_spq =
......@@ -475,6 +478,7 @@ int qed_spq_alloc(struct qed_hwfn *p_hwfn)
if (qed_chain_alloc(p_hwfn->cdev,
QED_CHAIN_USE_TO_PRODUCE,
QED_CHAIN_MODE_SINGLE,
QED_CHAIN_CNT_TYPE_U16,
0, /* N/A when the mode is SINGLE */
sizeof(struct slow_path_element),
&p_spq->chain)) {
......@@ -483,11 +487,11 @@ int qed_spq_alloc(struct qed_hwfn *p_hwfn)
}
/* allocate and fill the SPQ elements (incl. ramrod data list) */
capacity = qed_chain_get_capacity(&p_spq->chain);
p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
p_spq->chain.capacity *
capacity *
sizeof(struct qed_spq_entry),
&p_phys,
GFP_KERNEL);
&p_phys, GFP_KERNEL);
if (!p_virt)
goto spq_allocate_fail;
......@@ -507,16 +511,18 @@ int qed_spq_alloc(struct qed_hwfn *p_hwfn)
void qed_spq_free(struct qed_hwfn *p_hwfn)
{
struct qed_spq *p_spq = p_hwfn->p_spq;
u32 capacity;
if (!p_spq)
return;
if (p_spq->p_virt)
if (p_spq->p_virt) {
capacity = qed_chain_get_capacity(&p_spq->chain);
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
p_spq->chain.capacity *
capacity *
sizeof(struct qed_spq_entry),
p_spq->p_virt,
p_spq->p_phys);
p_spq->p_virt, p_spq->p_phys);
}
qed_chain_free(p_hwfn->cdev, &p_spq->chain);
;
......@@ -871,9 +877,9 @@ struct qed_consq *qed_consq_alloc(struct qed_hwfn *p_hwfn)
if (qed_chain_alloc(p_hwfn->cdev,
QED_CHAIN_USE_TO_PRODUCE,
QED_CHAIN_MODE_PBL,
QED_CHAIN_CNT_TYPE_U16,
QED_CHAIN_PAGE_SIZE / 0x80,
0x80,
&p_consq->chain)) {
0x80, &p_consq->chain)) {
DP_NOTICE(p_hwfn, "Failed to allocate consq chain");
goto consq_allocate_fail;
}
......
drivers/net/ethernet/qlogic/qede/qede_main.c
View file @ 03c7f70b
......@@ -2817,6 +2817,7 @@ static int qede_alloc_mem_rxq(struct qede_dev *edev,
rc = edev->ops->common->chain_alloc(edev->cdev,
QED_CHAIN_USE_TO_CONSUME_PRODUCE,
QED_CHAIN_MODE_NEXT_PTR,
QED_CHAIN_CNT_TYPE_U16,
RX_RING_SIZE,
sizeof(struct eth_rx_bd),
&rxq->rx_bd_ring);
......@@ -2828,6 +2829,7 @@ static int qede_alloc_mem_rxq(struct qede_dev *edev,
rc = edev->ops->common->chain_alloc(edev->cdev,
QED_CHAIN_USE_TO_CONSUME,
QED_CHAIN_MODE_PBL,
QED_CHAIN_CNT_TYPE_U16,
RX_RING_SIZE,
sizeof(union eth_rx_cqe),
&rxq->rx_comp_ring);
......@@ -2879,9 +2881,9 @@ static int qede_alloc_mem_txq(struct qede_dev *edev,
rc = edev->ops->common->chain_alloc(edev->cdev,
QED_CHAIN_USE_TO_CONSUME_PRODUCE,
QED_CHAIN_MODE_PBL,
QED_CHAIN_CNT_TYPE_U16,
NUM_TX_BDS_MAX,
sizeof(*p_virt),
&txq->tx_pbl);
sizeof(*p_virt), &txq->tx_pbl);
if (rc)
goto err;
......
include/linux/qed/common_hsi.h
View file @ 03c7f70b
......@@ -12,6 +12,7 @@
#define CORE_SPQE_PAGE_SIZE_BYTES 4096
#define X_FINAL_CLEANUP_AGG_INT 1
#define NUM_OF_GLOBAL_QUEUES 128
/* Queue Zone sizes in bytes */
#define TSTORM_QZONE_SIZE 8
......@@ -516,9 +517,9 @@ enum mf_mode {
/* Per-protocol connection types */
enum protocol_type {
PROTOCOLID_RESERVED1,
PROTOCOLID_ISCSI,
PROTOCOLID_RESERVED2,
PROTOCOLID_RESERVED3,
PROTOCOLID_ROCE,
PROTOCOLID_CORE,
PROTOCOLID_ETH,
PROTOCOLID_RESERVED4,
......@@ -694,7 +695,10 @@ struct parsing_and_err_flags {
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
};
/* Concrete Function ID. */
struct pb_context {
__le32 crc[4];
};
struct pxp_concrete_fid {
__le16 fid;
#define PXP_CONCRETE_FID_PFID_MASK 0xF
......@@ -761,6 +765,72 @@ struct pxp_ptt_entry {
};
/* RSS hash type */
struct rdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
u8 flags0;
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
u8 partial_dif_data[7];
__le16 partial_crc_value;
__le16 partial_checksum_value;
__le32 offset_in_io;
__le16 flags1;
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
__le16 state;
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
__le32 reserved2;
};
enum rss_hash_type {
RSS_HASH_TYPE_DEFAULT = 0,
RSS_HASH_TYPE_IPV4 = 1,
......@@ -789,4 +859,122 @@ struct status_block {
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
};
struct tdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
__le16 partial_crc_valueB;
__le16 partial_checksum_valueB;
__le16 stateB;
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
u8 reserved1;
u8 flags0;
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
__le32 flags1;
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
__le32 offset_in_iob;
__le16 partial_crc_value_a;
__le16 partial_checksum_valuea_;
__le32 offset_in_ioa;
u8 partial_dif_data_a[8];
u8 partial_dif_data_b[8];
};
struct timers_context {
__le32 logical_client0;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
#define TIMERS_CONTEXT_RESERVED0_MASK 0x3
#define TIMERS_CONTEXT_RESERVED0_SHIFT 30
__le32 logical_client1;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
__le32 logical_client2;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
#define TIMERS_CONTEXT_RESERVED2_MASK 0x3
#define TIMERS_CONTEXT_RESERVED2_SHIFT 30
__le32 host_expiration_fields;
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
#define TIMERS_CONTEXT_RESERVED3_MASK 0x7
#define TIMERS_CONTEXT_RESERVED3_SHIFT 29
};
#endif /* __COMMON_HSI__ */
include/linux/qed/iscsi_common.h 0 → 100644
View file @ 03c7f70b
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef __ISCSI_COMMON__
#define __ISCSI_COMMON__
/**********************/
/* ISCSI FW CONSTANTS */
/**********************/
/* iSCSI HSI constants */
#define ISCSI_DEFAULT_MTU (1500)
/* Current iSCSI HSI version number composed of two fields (16 bit) */
#define ISCSI_HSI_MAJOR_VERSION (0)
#define ISCSI_HSI_MINOR_VERSION (0)
/* KWQ (kernel work queue) layer codes */
#define ISCSI_SLOW_PATH_LAYER_CODE (6)
/* CQE completion status */
#define ISCSI_EQE_COMPLETION_SUCCESS (0x0)
#define ISCSI_EQE_RST_CONN_RCVD (0x1)
/* iSCSI parameter defaults */
#define ISCSI_DEFAULT_HEADER_DIGEST (0)
#define ISCSI_DEFAULT_DATA_DIGEST (0)
#define ISCSI_DEFAULT_INITIAL_R2T (1)
#define ISCSI_DEFAULT_IMMEDIATE_DATA (1)
#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
/* iSCSI parameter limits */
#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
#define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1)
#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
/* iSCSI reserved params */
#define ISCSI_ITT_ALL_ONES (0xffffffff)
#define ISCSI_TTT_ALL_ONES (0xffffffff)
#define ISCSI_OPTION_1_OFF_CHIP_TCP 1
#define ISCSI_OPTION_2_ON_CHIP_TCP 2
#define ISCSI_INITIATOR_MODE 0
#define ISCSI_TARGET_MODE 1
/* iSCSI request op codes */
#define ISCSI_OPCODE_NOP_OUT_NO_IMM (0)
#define ISCSI_OPCODE_NOP_OUT ( \
ISCSI_OPCODE_NOP_OUT_NO_IMM | 0x40)
#define ISCSI_OPCODE_SCSI_CMD_NO_IMM (1)
#define ISCSI_OPCODE_SCSI_CMD ( \
ISCSI_OPCODE_SCSI_CMD_NO_IMM | 0x40)
#define ISCSI_OPCODE_TMF_REQUEST_NO_IMM (2)
#define ISCSI_OPCODE_TMF_REQUEST ( \
ISCSI_OPCODE_TMF_REQUEST_NO_IMM | 0x40)
#define ISCSI_OPCODE_LOGIN_REQUEST_NO_IMM (3)
#define ISCSI_OPCODE_LOGIN_REQUEST ( \
ISCSI_OPCODE_LOGIN_REQUEST_NO_IMM | 0x40)
#define ISCSI_OPCODE_TEXT_REQUEST_NO_IMM (4)
#define ISCSI_OPCODE_TEXT_REQUEST ( \
ISCSI_OPCODE_TEXT_REQUEST_NO_IMM | 0x40)
#define ISCSI_OPCODE_DATA_OUT (5)
#define ISCSI_OPCODE_LOGOUT_REQUEST_NO_IMM (6)
#define ISCSI_OPCODE_LOGOUT_REQUEST ( \
ISCSI_OPCODE_LOGOUT_REQUEST_NO_IMM | 0x40)
/* iSCSI response/messages op codes */
#define ISCSI_OPCODE_NOP_IN (0x20)
#define ISCSI_OPCODE_SCSI_RESPONSE (0x21)
#define ISCSI_OPCODE_TMF_RESPONSE (0x22)
#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23)
#define ISCSI_OPCODE_TEXT_RESPONSE (0x24)
#define ISCSI_OPCODE_DATA_IN (0x25)
#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26)
#define ISCSI_OPCODE_R2T (0x31)
#define ISCSI_OPCODE_ASYNC_MSG (0x32)
#define ISCSI_OPCODE_REJECT (0x3f)
/* iSCSI stages */
#define ISCSI_STAGE_SECURITY_NEGOTIATION (0)
#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1)
#define ISCSI_STAGE_FULL_FEATURE_PHASE (3)
/* iSCSI CQE errors */
#define CQE_ERROR_BITMAP_DATA_DIGEST (0x08)
#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN (0x10)
#define CQE_ERROR_BITMAP_DATA_TRUNCATED (0x20)
struct cqe_error_bitmap {
u8 cqe_error_status_bits;
#define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7
#define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0
#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1
#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3
#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1
#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4
#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_MASK 0x1
#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_SHIFT 5
#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_MASK 0x1
#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_SHIFT 6
#define CQE_ERROR_BITMAP_RESERVED2_MASK 0x1
#define CQE_ERROR_BITMAP_RESERVED2_SHIFT 7
};
union cqe_error_status {
u8 error_status;
struct cqe_error_bitmap error_bits;
};
struct data_hdr {
__le32 data[12];
};
struct iscsi_async_msg_hdr {
__le16 reserved0;
u8 flags_attr;
#define ISCSI_ASYNC_MSG_HDR_RSRV_MASK 0x7F
#define ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT 0
#define ISCSI_ASYNC_MSG_HDR_CONST1_MASK 0x1
#define ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 all_ones;
__le32 reserved1;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le16 param1_rsrv;
u8 async_vcode;
u8 async_event;
__le16 param3_rsrv;
__le16 param2_rsrv;
__le32 reserved7;
};
struct iscsi_sge {
struct regpair sge_addr;
__le16 sge_len;
__le16 reserved0;
__le32 reserved1;
};
struct iscsi_cached_sge_ctx {
struct iscsi_sge sge;
struct regpair reserved;
__le32 dsgl_curr_offset[2];
};
struct iscsi_cmd_hdr {
__le16 reserved1;
u8 flags_attr;
#define ISCSI_CMD_HDR_ATTR_MASK 0x7
#define ISCSI_CMD_HDR_ATTR_SHIFT 0
#define ISCSI_CMD_HDR_RSRV_MASK 0x3
#define ISCSI_CMD_HDR_RSRV_SHIFT 3
#define ISCSI_CMD_HDR_WRITE_MASK 0x1
#define ISCSI_CMD_HDR_WRITE_SHIFT 5
#define ISCSI_CMD_HDR_READ_MASK 0x1
#define ISCSI_CMD_HDR_READ_SHIFT 6
#define ISCSI_CMD_HDR_FINAL_MASK 0x1
#define ISCSI_CMD_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 expected_transfer_length;
__le32 cmd_sn;
__le32 exp_stat_sn;
__le32 cdb[4];
};
struct iscsi_common_hdr {
u8 hdr_status;
u8 hdr_response;
u8 hdr_flags;
u8 hdr_first_byte;
#define ISCSI_COMMON_HDR_OPCODE_MASK 0x3F
#define ISCSI_COMMON_HDR_OPCODE_SHIFT 0
#define ISCSI_COMMON_HDR_IMM_MASK 0x1
#define ISCSI_COMMON_HDR_IMM_SHIFT 6
#define ISCSI_COMMON_HDR_RSRV_MASK 0x1
#define ISCSI_COMMON_HDR_RSRV_SHIFT 7
__le32 hdr_second_dword;
#define ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 lun_reserved[4];
__le32 data[6];
};
struct iscsi_conn_offload_params {
struct regpair sq_pbl_addr;
struct regpair r2tq_pbl_addr;
struct regpair xhq_pbl_addr;
struct regpair uhq_pbl_addr;
__le32 initial_ack;
__le16 physical_q0;
__le16 physical_q1;
u8 flags;
#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1
#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x3F
#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 2
u8 pbl_page_size_log;
u8 pbe_page_size_log;
u8 default_cq;
__le32 stat_sn;
};
struct iscsi_slow_path_hdr {
u8 op_code;
u8 flags;
#define ISCSI_SLOW_PATH_HDR_RESERVED0_MASK 0xF
#define ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT 0
#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK 0x7
#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT 4
#define ISCSI_SLOW_PATH_HDR_RESERVED1_MASK 0x1
#define ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT 7
};
struct iscsi_conn_update_ramrod_params {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
__le32 fw_cid;
u8 flags;
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK 0x1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0xF
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 4
u8 reserved0[3];
__le32 max_seq_size;
__le32 max_send_pdu_length;
__le32 max_recv_pdu_length;
__le32 first_seq_length;
__le32 exp_stat_sn;
};
struct iscsi_ext_cdb_cmd_hdr {
__le16 reserved1;
u8 flags_attr;
#define ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK 0x7
#define ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT 0
#define ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK 0x3
#define ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT 3
#define ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK 0x1
#define ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT 5
#define ISCSI_EXT_CDB_CMD_HDR_READ_MASK 0x1
#define ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT 6
#define ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK 0x1
#define ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK 0xFF
#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 expected_transfer_length;
__le32 cmd_sn;
__le32 exp_stat_sn;
struct iscsi_sge cdb_sge;
};
struct iscsi_login_req_hdr {
u8 version_min;
u8 version_max;
u8 flags_attr;
#define ISCSI_LOGIN_REQ_HDR_NSG_MASK 0x3
#define ISCSI_LOGIN_REQ_HDR_NSG_SHIFT 0
#define ISCSI_LOGIN_REQ_HDR_CSG_MASK 0x3
#define ISCSI_LOGIN_REQ_HDR_CSG_SHIFT 2
#define ISCSI_LOGIN_REQ_HDR_RSRV_MASK 0x3
#define ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT 4
#define ISCSI_LOGIN_REQ_HDR_C_MASK 0x1
#define ISCSI_LOGIN_REQ_HDR_C_SHIFT 6
#define ISCSI_LOGIN_REQ_HDR_T_MASK 0x1
#define ISCSI_LOGIN_REQ_HDR_T_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_TABC;
__le16 tsih;
__le16 isid_d;
__le32 itt;
__le16 reserved1;
__le16 cid;
__le32 cmd_sn;
__le32 exp_stat_sn;
__le32 reserved2[4];
};
struct iscsi_logout_req_hdr {
__le16 reserved0;
u8 reason_code;
u8 opcode;
__le32 reserved1;
__le32 reserved2[2];
__le32 itt;
__le16 reserved3;
__le16 cid;
__le32 cmd_sn;
__le32 exp_stat_sn;
__le32 reserved4[4];
};
struct iscsi_data_out_hdr {
__le16 reserved1;
u8 flags_attr;
#define ISCSI_DATA_OUT_HDR_RSRV_MASK 0x7F
#define ISCSI_DATA_OUT_HDR_RSRV_SHIFT 0
#define ISCSI_DATA_OUT_HDR_FINAL_MASK 0x1
#define ISCSI_DATA_OUT_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
__le32 itt;
__le32 ttt;
__le32 reserved3;
__le32 exp_stat_sn;
__le32 reserved4;
__le32 data_sn;
__le32 buffer_offset;
__le32 reserved5;
};
struct iscsi_data_in_hdr {
u8 status_rsvd;
u8 reserved1;
u8 flags;
#define ISCSI_DATA_IN_HDR_STATUS_MASK 0x1
#define ISCSI_DATA_IN_HDR_STATUS_SHIFT 0
#define ISCSI_DATA_IN_HDR_UNDERFLOW_MASK 0x1
#define ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT 1
#define ISCSI_DATA_IN_HDR_OVERFLOW_MASK 0x1
#define ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT 2
#define ISCSI_DATA_IN_HDR_RSRV_MASK 0x7
#define ISCSI_DATA_IN_HDR_RSRV_SHIFT 3
#define ISCSI_DATA_IN_HDR_ACK_MASK 0x1
#define ISCSI_DATA_IN_HDR_ACK_SHIFT 6
#define ISCSI_DATA_IN_HDR_FINAL_MASK 0x1
#define ISCSI_DATA_IN_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
__le32 itt;
__le32 ttt;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 data_sn;
__le32 buffer_offset;
__le32 residual_count;
};
struct iscsi_r2t_hdr {
u8 reserved0[3];
u8 opcode;
__le32 reserved2;
struct regpair lun;
__le32 itt;
__le32 ttt;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 r2t_sn;
__le32 buffer_offset;
__le32 desired_data_trns_len;
};
struct iscsi_nop_out_hdr {
__le16 reserved1;
u8 flags_attr;
#define ISCSI_NOP_OUT_HDR_RSRV_MASK 0x7F
#define ISCSI_NOP_OUT_HDR_RSRV_SHIFT 0
#define ISCSI_NOP_OUT_HDR_CONST1_MASK 0x1
#define ISCSI_NOP_OUT_HDR_CONST1_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
__le32 itt;
__le32 ttt;
__le32 cmd_sn;
__le32 exp_stat_sn;
__le32 reserved3;
__le32 reserved4;
__le32 reserved5;
__le32 reserved6;
};
struct iscsi_nop_in_hdr {
__le16 reserved0;
u8 flags_attr;
#define ISCSI_NOP_IN_HDR_RSRV_MASK 0x7F
#define ISCSI_NOP_IN_HDR_RSRV_SHIFT 0
#define ISCSI_NOP_IN_HDR_CONST1_MASK 0x1
#define ISCSI_NOP_IN_HDR_CONST1_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 reserved5;
__le32 reserved6;
__le32 reserved7;
};
struct iscsi_login_response_hdr {
u8 version_active;
u8 version_max;
u8 flags_attr;
#define ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK 0x3
#define ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT 0
#define ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK 0x3
#define ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT 2
#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK 0x3
#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT 4
#define ISCSI_LOGIN_RESPONSE_HDR_C_MASK 0x1
#define ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT 6
#define ISCSI_LOGIN_RESPONSE_HDR_T_MASK 0x1
#define ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_TABC;
__le16 tsih;
__le16 isid_d;
__le32 itt;
__le32 reserved1;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le16 reserved2;
u8 status_detail;
u8 status_class;
__le32 reserved4[2];
};
struct iscsi_logout_response_hdr {
u8 reserved1;
u8 response;
u8 flags;
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 reserved2[2];
__le32 itt;
__le32 reserved3;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 reserved4;
__le16 time2retain;
__le16 time2wait;
__le32 reserved5[1];
};
struct iscsi_text_request_hdr {
__le16 reserved0;
u8 flags_attr;
#define ISCSI_TEXT_REQUEST_HDR_RSRV_MASK 0x3F
#define ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT 0
#define ISCSI_TEXT_REQUEST_HDR_C_MASK 0x1
#define ISCSI_TEXT_REQUEST_HDR_C_SHIFT 6
#define ISCSI_TEXT_REQUEST_HDR_F_MASK 0x1
#define ISCSI_TEXT_REQUEST_HDR_F_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
__le32 cmd_sn;
__le32 exp_stat_sn;
__le32 reserved4[4];
};
struct iscsi_text_response_hdr {
__le16 reserved1;
u8 flags;
#define ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK 0x3F
#define ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT 0
#define ISCSI_TEXT_RESPONSE_HDR_C_MASK 0x1
#define ISCSI_TEXT_RESPONSE_HDR_C_SHIFT 6
#define ISCSI_TEXT_RESPONSE_HDR_F_MASK 0x1
#define ISCSI_TEXT_RESPONSE_HDR_F_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 reserved4[3];
};
struct iscsi_tmf_request_hdr {
__le16 reserved0;
u8 function;
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 rtt;
__le32 cmd_sn;
__le32 exp_stat_sn;
__le32 ref_cmd_sn;
__le32 exp_data_sn;
__le32 reserved4[2];
};
struct iscsi_tmf_response_hdr {
u8 reserved2;
u8 hdr_response;
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 itt;
__le32 rtt;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 reserved4[3];
};
struct iscsi_response_hdr {
u8 hdr_status;
u8 hdr_response;
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 snack_tag;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 exp_data_sn;
__le32 bi_residual_count;
__le32 residual_count;
};
struct iscsi_reject_hdr {
u8 reserved4;
u8 hdr_reason;
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
#define ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 reserved1;
__le32 reserved2;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 data_sn;
__le32 reserved3[2];
};
union iscsi_task_hdr {
struct iscsi_common_hdr common;
struct data_hdr data;
struct iscsi_cmd_hdr cmd;
struct iscsi_ext_cdb_cmd_hdr ext_cdb_cmd;
struct iscsi_login_req_hdr login_req;
struct iscsi_logout_req_hdr logout_req;
struct iscsi_data_out_hdr data_out;
struct iscsi_data_in_hdr data_in;
struct iscsi_r2t_hdr r2t;
struct iscsi_nop_out_hdr nop_out;
struct iscsi_nop_in_hdr nop_in;
struct iscsi_login_response_hdr login_response;
struct iscsi_logout_response_hdr logout_response;
struct iscsi_text_request_hdr text_request;
struct iscsi_text_response_hdr text_response;
struct iscsi_tmf_request_hdr tmf_request;
struct iscsi_tmf_response_hdr tmf_response;
struct iscsi_response_hdr response;
struct iscsi_reject_hdr reject;
struct iscsi_async_msg_hdr async_msg;
};
struct iscsi_cqe_common {
__le16 conn_id;
u8 cqe_type;
union cqe_error_status error_bitmap;
__le32 reserved[3];
union iscsi_task_hdr iscsi_hdr;
};
struct iscsi_cqe_solicited {
__le16 conn_id;
u8 cqe_type;
union cqe_error_status error_bitmap;
__le16 itid;
u8 task_type;
u8 fw_dbg_field;
__le32 reserved1[2];
union iscsi_task_hdr iscsi_hdr;
};
struct iscsi_cqe_unsolicited {
__le16 conn_id;
u8 cqe_type;
union cqe_error_status error_bitmap;
__le16 reserved0;
u8 reserved1;
u8 unsol_cqe_type;
struct regpair rqe_opaque;
union iscsi_task_hdr iscsi_hdr;
};
union iscsi_cqe {
struct iscsi_cqe_common cqe_common;
struct iscsi_cqe_solicited cqe_solicited;
struct iscsi_cqe_unsolicited cqe_unsolicited;
};
enum iscsi_cqes_type {
ISCSI_CQE_TYPE_SOLICITED = 1,
ISCSI_CQE_TYPE_UNSOLICITED,
ISCSI_CQE_TYPE_SOLICITED_WITH_SENSE
,
ISCSI_CQE_TYPE_TASK_CLEANUP,
ISCSI_CQE_TYPE_DUMMY,
MAX_ISCSI_CQES_TYPE
};
enum iscsi_cqe_unsolicited_type {
ISCSI_CQE_UNSOLICITED_NONE,
ISCSI_CQE_UNSOLICITED_SINGLE,
ISCSI_CQE_UNSOLICITED_FIRST,
ISCSI_CQE_UNSOLICITED_MIDDLE,
ISCSI_CQE_UNSOLICITED_LAST,
MAX_ISCSI_CQE_UNSOLICITED_TYPE
};
struct iscsi_virt_sgl_ctx {
struct regpair sgl_base;
struct regpair dsgl_base;
__le32 sgl_initial_offset;
__le32 dsgl_initial_offset;
__le32 dsgl_curr_offset[2];
};
struct iscsi_sgl_var_params {
u8 sgl_ptr;
u8 dsgl_ptr;
__le16 sge_offset;
__le16 dsge_offset;
};
struct iscsi_phys_sgl_ctx {
struct regpair sgl_base;
struct regpair dsgl_base;
u8 sgl_size;
u8 dsgl_size;
__le16 reserved;
struct iscsi_sgl_var_params var_params[2];
};
union iscsi_data_desc_ctx {
struct iscsi_virt_sgl_ctx virt_sgl;
struct iscsi_phys_sgl_ctx phys_sgl;
struct iscsi_cached_sge_ctx cached_sge;
};
struct iscsi_debug_modes {
u8 flags;
#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT 0
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT 1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT 2
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT 3
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5
#define ISCSI_DEBUG_MODES_RESERVED0_MASK 0x3
#define ISCSI_DEBUG_MODES_RESERVED0_SHIFT 6
};
struct iscsi_dif_flags {
u8 flags;
#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
#define ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK 0x1
#define ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT 4
#define ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK 0x7
#define ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT 5
};
enum iscsi_eqe_opcode {
ISCSI_EVENT_TYPE_INIT_FUNC = 0,
ISCSI_EVENT_TYPE_DESTROY_FUNC,
ISCSI_EVENT_TYPE_OFFLOAD_CONN,
ISCSI_EVENT_TYPE_UPDATE_CONN,
ISCSI_EVENT_TYPE_CLEAR_SQ,
ISCSI_EVENT_TYPE_TERMINATE_CONN,
ISCSI_EVENT_TYPE_ASYN_CONNECT_COMPLETE,
ISCSI_EVENT_TYPE_ASYN_TERMINATE_DONE,
RESERVED8,
RESERVED9,
ISCSI_EVENT_TYPE_START_OF_ERROR_TYPES = 10,
ISCSI_EVENT_TYPE_ASYN_ABORT_RCVD,
ISCSI_EVENT_TYPE_ASYN_CLOSE_RCVD,
ISCSI_EVENT_TYPE_ASYN_SYN_RCVD,
ISCSI_EVENT_TYPE_ASYN_MAX_RT_TIME,
ISCSI_EVENT_TYPE_ASYN_MAX_RT_CNT,
ISCSI_EVENT_TYPE_ASYN_MAX_KA_PROBES_CNT,
ISCSI_EVENT_TYPE_ASYN_FIN_WAIT2,
ISCSI_EVENT_TYPE_ISCSI_CONN_ERROR,
ISCSI_EVENT_TYPE_TCP_CONN_ERROR,
ISCSI_EVENT_TYPE_ASYN_DELETE_OOO_ISLES,
MAX_ISCSI_EQE_OPCODE
};
enum iscsi_error_types {
ISCSI_STATUS_NONE = 0,
ISCSI_CQE_ERROR_UNSOLICITED_RCV_ON_INVALID_CONN = 1,
ISCSI_CONN_ERROR_TASK_CID_MISMATCH,
ISCSI_CONN_ERROR_TASK_NOT_VALID,
ISCSI_CONN_ERROR_RQ_RING_IS_FULL,
ISCSI_CONN_ERROR_CMDQ_RING_IS_FULL,
ISCSI_CONN_ERROR_HQE_CACHING_FAILED,
ISCSI_CONN_ERROR_HEADER_DIGEST_ERROR,
ISCSI_CONN_ERROR_LOCAL_COMPLETION_ERROR,
ISCSI_CONN_ERROR_DATA_OVERRUN,
ISCSI_CONN_ERROR_OUT_OF_SGES_ERROR,
ISCSI_CONN_ERROR_TCP_SEG_PROC_URG_ERROR,
ISCSI_CONN_ERROR_TCP_SEG_PROC_IP_OPTIONS_ERROR,
ISCSI_CONN_ERROR_TCP_SEG_PROC_CONNECT_INVALID_WS_OPTION,
ISCSI_CONN_ERROR_TCP_IP_FRAGMENT_ERROR,
ISCSI_CONN_ERROR_PROTOCOL_ERR_AHS_LEN,
ISCSI_CONN_ERROR_PROTOCOL_ERR_AHS_TYPE,
ISCSI_CONN_ERROR_PROTOCOL_ERR_ITT_OUT_OF_RANGE,
ISCSI_CONN_ERROR_PROTOCOL_ERR_TTT_OUT_OF_RANGE,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_SEG_LEN_EXCEEDS_PDU_SIZE,
ISCSI_CONN_ERROR_PROTOCOL_ERR_INVALID_OPCODE,
ISCSI_CONN_ERROR_PROTOCOL_ERR_INVALID_OPCODE_BEFORE_UPDATE,
ISCSI_CONN_ERROR_UNVALID_NOPIN_DSL,
ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_CARRIES_NO_DATA,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_SN,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_IN_TTT,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_OUT_ITT,
ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_TTT,
ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_BUFFER_OFFSET,
ISCSI_CONN_ERROR_PROTOCOL_ERR_BUFFER_OFFSET_OOO,
ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_SN,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_0,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_1,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_2,
ISCSI_CONN_ERROR_PROTOCOL_ERR_LUN,
ISCSI_CONN_ERROR_PROTOCOL_ERR_F_BIT_ZERO,
ISCSI_CONN_ERROR_PROTOCOL_ERR_F_BIT_ZERO_S_BIT_ONE,
ISCSI_CONN_ERROR_PROTOCOL_ERR_EXP_STAT_SN,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DSL_NOT_ZERO,
ISCSI_CONN_ERROR_PROTOCOL_ERR_INVALID_DSL,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_SEG_LEN_TOO_BIG,
ISCSI_CONN_ERROR_PROTOCOL_ERR_OUTSTANDING_R2T_COUNT,
ISCSI_CONN_ERROR_PROTOCOL_ERR_DIF_TX,
ISCSI_CONN_ERROR_SENSE_DATA_LENGTH,
ISCSI_CONN_ERROR_DATA_PLACEMENT_ERROR,
ISCSI_ERROR_UNKNOWN,
MAX_ISCSI_ERROR_TYPES
};
struct iscsi_mflags {
u8 mflags;
#define ISCSI_MFLAGS_SLOW_IO_MASK 0x1
#define ISCSI_MFLAGS_SLOW_IO_SHIFT 0
#define ISCSI_MFLAGS_SINGLE_SGE_MASK 0x1
#define ISCSI_MFLAGS_SINGLE_SGE_SHIFT 1
#define ISCSI_MFLAGS_RESERVED_MASK 0x3F
#define ISCSI_MFLAGS_RESERVED_SHIFT 2
};
struct iscsi_sgl {
struct regpair sgl_addr;
__le16 updated_sge_size;
__le16 updated_sge_offset;
__le32 byte_offset;
};
union iscsi_mstorm_sgl {
struct iscsi_sgl sgl_struct;
struct iscsi_sge single_sge;
};
enum iscsi_ramrod_cmd_id {
ISCSI_RAMROD_CMD_ID_UNUSED = 0,
ISCSI_RAMROD_CMD_ID_INIT_FUNC = 1,
ISCSI_RAMROD_CMD_ID_DESTROY_FUNC = 2,
ISCSI_RAMROD_CMD_ID_OFFLOAD_CONN = 3,
ISCSI_RAMROD_CMD_ID_UPDATE_CONN = 4,
ISCSI_RAMROD_CMD_ID_TERMINATION_CONN = 5,
ISCSI_RAMROD_CMD_ID_CLEAR_SQ = 6,
MAX_ISCSI_RAMROD_CMD_ID
};
struct iscsi_reg1 {
__le32 reg1_map;
#define ISCSI_REG1_NUM_FAST_SGES_MASK 0x7
#define ISCSI_REG1_NUM_FAST_SGES_SHIFT 0
#define ISCSI_REG1_RESERVED1_MASK 0x1FFFFFFF
#define ISCSI_REG1_RESERVED1_SHIFT 3
};
union iscsi_seq_num {
__le16 data_sn;
__le16 r2t_sn;
};
struct iscsi_spe_conn_offload {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
__le32 fw_cid;
struct iscsi_conn_offload_params iscsi;
struct tcp_offload_params tcp;
};
struct iscsi_spe_conn_offload_option2 {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
__le32 fw_cid;
struct iscsi_conn_offload_params iscsi;
struct tcp_offload_params_opt2 tcp;
};
struct iscsi_spe_conn_termination {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
__le32 fw_cid;
u8 abortive;
u8 reserved0[7];
struct regpair queue_cnts_addr;
struct regpair query_params_addr;
};
struct iscsi_spe_func_dstry {
struct iscsi_slow_path_hdr hdr;
__le16 reserved0;
__le32 reserved1;
};
struct iscsi_spe_func_init {
struct iscsi_slow_path_hdr hdr;
__le16 half_way_close_timeout;
u8 num_sq_pages_in_ring;
u8 num_r2tq_pages_in_ring;
u8 num_uhq_pages_in_ring;
u8 ll2_rx_queue_id;
u8 ooo_enable;
struct iscsi_debug_modes debug_mode;
__le16 reserved1;
__le32 reserved2;
__le32 reserved3;
__le32 reserved4;
struct scsi_init_func_params func_params;
struct scsi_init_func_queues q_params;
};
struct ystorm_iscsi_task_state {
union iscsi_data_desc_ctx sgl_ctx_union;
__le32 buffer_offset[2];
__le16 bytes_nxt_dif;
__le16 rxmit_bytes_nxt_dif;
union iscsi_seq_num seq_num_union;
u8 dif_bytes_leftover;
u8 rxmit_dif_bytes_leftover;
__le16 reuse_count;
struct iscsi_dif_flags dif_flags;
u8 local_comp;
__le32 exp_r2t_sn;
__le32 sgl_offset[2];
};
struct ystorm_iscsi_task_st_ctx {
struct ystorm_iscsi_task_state state;
union iscsi_task_hdr pdu_hdr;
};
struct ystorm_iscsi_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 word0;
u8 flags0;
#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 TTT;
u8 byte3;
u8 byte4;
__le16 word1;
};
struct mstorm_iscsi_task_ag_ctx {
u8 cdu_validation;
u8 byte1;
__le16 task_cid;
u8 flags0;
#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
u8 flags1;
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
u8 byte4;
__le16 word1;
};
struct ustorm_iscsi_task_ag_ctx {
u8 reserved;
u8 state;
__le16 icid;
u8 flags0;
#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
u8 flags1;
#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
u8 flags3;
#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 rcv_cont_len;
__le32 exp_cont_len;
__le32 total_data_acked;
__le32 exp_data_acked;
u8 next_tid_valid;
u8 byte3;
__le16 word1;
__le16 next_tid;
__le16 word3;
__le32 hdr_residual_count;
__le32 exp_r2t_sn;
};
struct mstorm_iscsi_task_st_ctx {
union iscsi_mstorm_sgl sgl_union;
struct iscsi_dif_flags dif_flags;
struct iscsi_mflags flags;
u8 sgl_size;
u8 host_sge_index;
__le16 dix_cur_sge_offset;
__le16 dix_cur_sge_size;
__le32 data_offset_rtid;
u8 dif_offset;
u8 dix_sgl_size;
u8 dix_sge_index;
u8 task_type;
struct regpair sense_db;
struct regpair dix_sgl_cur_sge;
__le32 rem_task_size;
__le16 reuse_count;
__le16 dif_data_residue;
u8 reserved0[4];
__le32 reserved1[1];
};
struct ustorm_iscsi_task_st_ctx {
__le32 rem_rcv_len;
__le32 exp_data_transfer_len;
__le32 exp_data_sn;
struct regpair lun;
struct iscsi_reg1 reg1;
u8 flags2;
#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
u8 reserved2;
__le16 reserved3;
__le32 reserved4;
__le32 reserved5;
__le32 reserved6;
__le32 reserved7;
u8 task_type;
u8 error_flags;
#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK 0x1F
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT 3
u8 flags;
#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK 0x3
#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT 0
#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
#define USTORM_ISCSI_TASK_ST_CTX_TOTALDATAACKED_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_TOTALDATAACKED_DONE_SHIFT 4
#define USTORM_ISCSI_TASK_ST_CTX_HQSCANNED_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_HQSCANNED_DONE_SHIFT 5
#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT 7
u8 cq_rss_number;
};
struct iscsi_task_context {
struct ystorm_iscsi_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
struct regpair ystorm_ag_padding[2];
struct tdif_task_context tdif_context;
struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
struct regpair mstorm_ag_padding[2];
struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
struct mstorm_iscsi_task_st_ctx mstorm_st_context;
struct ustorm_iscsi_task_st_ctx ustorm_st_context;
struct rdif_task_context rdif_context;
};
enum iscsi_task_type {
ISCSI_TASK_TYPE_INITIATOR_WRITE,
ISCSI_TASK_TYPE_INITIATOR_READ,
ISCSI_TASK_TYPE_MIDPATH,
ISCSI_TASK_TYPE_UNSOLIC,
ISCSI_TASK_TYPE_EXCHCLEANUP,
ISCSI_TASK_TYPE_IRRELEVANT,
ISCSI_TASK_TYPE_TARGET_WRITE,
ISCSI_TASK_TYPE_TARGET_READ,
ISCSI_TASK_TYPE_TARGET_RESPONSE,
ISCSI_TASK_TYPE_LOGIN_RESPONSE,
MAX_ISCSI_TASK_TYPE
};
union iscsi_ttt_txlen_union {
__le32 desired_tx_len;
__le32 ttt;
};
struct iscsi_uhqe {
__le32 reg1;
#define ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK 0xFFFFF
#define ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT 0
#define ISCSI_UHQE_LOCAL_COMP_MASK 0x1
#define ISCSI_UHQE_LOCAL_COMP_SHIFT 20
#define ISCSI_UHQE_TOGGLE_BIT_MASK 0x1
#define ISCSI_UHQE_TOGGLE_BIT_SHIFT 21
#define ISCSI_UHQE_PURE_PAYLOAD_MASK 0x1
#define ISCSI_UHQE_PURE_PAYLOAD_SHIFT 22
#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK 0x1
#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT 23
#define ISCSI_UHQE_TASK_ID_HI_MASK 0xFF
#define ISCSI_UHQE_TASK_ID_HI_SHIFT 24
__le32 reg2;
#define ISCSI_UHQE_BUFFER_OFFSET_MASK 0xFFFFFF
#define ISCSI_UHQE_BUFFER_OFFSET_SHIFT 0
#define ISCSI_UHQE_TASK_ID_LO_MASK 0xFF
#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24
};
struct iscsi_wqe_field {
__le32 contlen_cdbsize_field;
#define ISCSI_WQE_FIELD_CONT_LEN_MASK 0xFFFFFF
#define ISCSI_WQE_FIELD_CONT_LEN_SHIFT 0
#define ISCSI_WQE_FIELD_CDB_SIZE_MASK 0xFF
#define ISCSI_WQE_FIELD_CDB_SIZE_SHIFT 24
};
union iscsi_wqe_field_union {
struct iscsi_wqe_field cont_field;
__le32 prev_tid;
};
struct iscsi_wqe {
__le16 task_id;
u8 flags;
#define ISCSI_WQE_WQE_TYPE_MASK 0x7
#define ISCSI_WQE_WQE_TYPE_SHIFT 0
#define ISCSI_WQE_NUM_FAST_SGES_MASK 0x7
#define ISCSI_WQE_NUM_FAST_SGES_SHIFT 3
#define ISCSI_WQE_PTU_INVALIDATE_MASK 0x1
#define ISCSI_WQE_PTU_INVALIDATE_SHIFT 6
#define ISCSI_WQE_RESPONSE_MASK 0x1
#define ISCSI_WQE_RESPONSE_SHIFT 7
struct iscsi_dif_flags prot_flags;
union iscsi_wqe_field_union cont_prevtid_union;
};
enum iscsi_wqe_type {
ISCSI_WQE_TYPE_NORMAL,
ISCSI_WQE_TYPE_TASK_CLEANUP,
ISCSI_WQE_TYPE_MIDDLE_PATH,
ISCSI_WQE_TYPE_LOGIN,
ISCSI_WQE_TYPE_FIRST_R2T_CONT,
ISCSI_WQE_TYPE_NONFIRST_R2T_CONT,
ISCSI_WQE_TYPE_RESPONSE,
MAX_ISCSI_WQE_TYPE
};
struct iscsi_xhqe {
union iscsi_ttt_txlen_union ttt_or_txlen;
__le32 exp_stat_sn;
struct iscsi_dif_flags prot_flags;
u8 total_ahs_length;
u8 opcode;
u8 flags;
#define ISCSI_XHQE_NUM_FAST_SGES_MASK 0x7
#define ISCSI_XHQE_NUM_FAST_SGES_SHIFT 0
#define ISCSI_XHQE_FINAL_MASK 0x1
#define ISCSI_XHQE_FINAL_SHIFT 3
#define ISCSI_XHQE_SUPER_IO_MASK 0x1
#define ISCSI_XHQE_SUPER_IO_SHIFT 4
#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
#define ISCSI_XHQE_STATUS_BIT_SHIFT 5
#define ISCSI_XHQE_RESERVED_MASK 0x3
#define ISCSI_XHQE_RESERVED_SHIFT 6
union iscsi_seq_num seq_num_union;
__le16 reserved1;
};
struct mstorm_iscsi_stats_drv {
struct regpair iscsi_rx_dropped_pdus_task_not_valid;
};
struct ooo_opaque {
__le32 cid;
u8 drop_isle;
u8 drop_size;
u8 ooo_opcode;
u8 ooo_isle;
};
struct pstorm_iscsi_stats_drv {
struct regpair iscsi_tx_bytes_cnt;
struct regpair iscsi_tx_packet_cnt;
};
struct tstorm_iscsi_stats_drv {
struct regpair iscsi_rx_bytes_cnt;
struct regpair iscsi_rx_packet_cnt;
struct regpair iscsi_rx_new_ooo_isle_events_cnt;
__le32 iscsi_cmdq_threshold_cnt;
__le32 iscsi_rq_threshold_cnt;
__le32 iscsi_immq_threshold_cnt;
};
struct ustorm_iscsi_stats_drv {
struct regpair iscsi_rx_data_pdu_cnt;
struct regpair iscsi_rx_r2t_pdu_cnt;
struct regpair iscsi_rx_total_pdu_cnt;
};
struct xstorm_iscsi_stats_drv {
struct regpair iscsi_tx_go_to_slow_start_event_cnt;
struct regpair iscsi_tx_fast_retransmit_event_cnt;
};
struct ystorm_iscsi_stats_drv {
struct regpair iscsi_tx_data_pdu_cnt;
struct regpair iscsi_tx_r2t_pdu_cnt;
struct regpair iscsi_tx_total_pdu_cnt;
};
struct iscsi_db_data {
u8 params;
#define ISCSI_DB_DATA_DEST_MASK 0x3
#define ISCSI_DB_DATA_DEST_SHIFT 0
#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
#define ISCSI_DB_DATA_RESERVED_MASK 0x1
#define ISCSI_DB_DATA_RESERVED_SHIFT 5
#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
struct tstorm_iscsi_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;
u8 byte3;
u8 byte4;
__le16 word2;
__le16 word3;
__le16 word4;
__le32 reg1;
__le32 reg2;
};
#endif /* __ISCSI_COMMON__ */
include/linux/qed/qed_chain.h
View file @ 03c7f70b
......@@ -47,16 +47,56 @@ enum qed_chain_use_mode {
QED_CHAIN_USE_TO_CONSUME_PRODUCE, /* Chain starts empty */
};
enum qed_chain_cnt_type {
/* The chain's size/prod/cons are kept in 16-bit variables */
QED_CHAIN_CNT_TYPE_U16,
/* The chain's size/prod/cons are kept in 32-bit variables */
QED_CHAIN_CNT_TYPE_U32,
};
struct qed_chain_next {
struct regpair next_phys;
void *next_virt;
};
struct qed_chain_pbl_u16 {
u16 prod_page_idx;
u16 cons_page_idx;
};
struct qed_chain_pbl_u32 {
u32 prod_page_idx;
u32 cons_page_idx;
};
struct qed_chain_pbl {
/* Base address of a pre-allocated buffer for pbl */
dma_addr_t p_phys_table;
void *p_virt_table;
u16 prod_page_idx;
u16 cons_page_idx;
/* Table for keeping the virtual addresses of the chain pages,
* respectively to the physical addresses in the pbl table.
*/
void **pp_virt_addr_tbl;
/* Index to current used page by producer/consumer */
union {
struct qed_chain_pbl_u16 pbl16;
struct qed_chain_pbl_u32 pbl32;
} u;
};
struct qed_chain_u16 {
/* Cyclic index of next element to produce/consme */
u16 prod_idx;
u16 cons_idx;
};
struct qed_chain_u32 {
/* Cyclic index of next element to produce/consme */
u32 prod_idx;
u32 cons_idx;
};
struct qed_chain {
......@@ -64,13 +104,25 @@ struct qed_chain {
dma_addr_t p_phys_addr;
void *p_prod_elem;
void *p_cons_elem;
u16 page_cnt;
enum qed_chain_mode mode;
enum qed_chain_use_mode intended_use; /* used to produce/consume */
u16 capacity; /*< number of _usable_ elements */
u16 size; /* number of elements */
u16 prod_idx;
u16 cons_idx;
enum qed_chain_cnt_type cnt_type;
union {
struct qed_chain_u16 chain16;
struct qed_chain_u32 chain32;
} u;
u32 page_cnt;
/* Number of elements - capacity is for usable elements only,
* while size will contain total number of elements [for entire chain].
*/
u32 capacity;
u32 size;
/* Elements information for fast calculations */
u16 elem_per_page;
u16 elem_per_page_mask;
u16 elem_unusable;
......@@ -96,66 +148,69 @@ struct qed_chain {
#define QED_CHAIN_PAGE_CNT(elem_cnt, elem_size, mode) \
DIV_ROUND_UP(elem_cnt, USABLE_ELEMS_PER_PAGE(elem_size, mode))
#define is_chain_u16(p) ((p)->cnt_type == QED_CHAIN_CNT_TYPE_U16)
#define is_chain_u32(p) ((p)->cnt_type == QED_CHAIN_CNT_TYPE_U32)
/* Accessors */
static inline u16 qed_chain_get_prod_idx(struct qed_chain *p_chain)
{
return p_chain->prod_idx;
return p_chain->u.chain16.prod_idx;
}
static inline u16 qed_chain_get_cons_idx(struct qed_chain *p_chain)
{
return p_chain->cons_idx;
return p_chain->u.chain16.cons_idx;
}
static inline u32 qed_chain_get_cons_idx_u32(struct qed_chain *p_chain)
{
return p_chain->u.chain32.cons_idx;
}
static inline u16 qed_chain_get_elem_left(struct qed_chain *p_chain)
{
u16 used;
/* we don't need to trancate upon assignmet, as we assign u32->u16 */
used = ((u32)0x10000u + (u32)(p_chain->prod_idx)) -
(u32)p_chain->cons_idx;
used = (u16) (((u32)0x10000 +
(u32)p_chain->u.chain16.prod_idx) -
(u32)p_chain->u.chain16.cons_idx);
if (p_chain->mode == QED_CHAIN_MODE_NEXT_PTR)
used -= p_chain->prod_idx / p_chain->elem_per_page -
p_chain->cons_idx / p_chain->elem_per_page;
used -= p_chain->u.chain16.prod_idx / p_chain->elem_per_page -
p_chain->u.chain16.cons_idx / p_chain->elem_per_page;
return p_chain->capacity - used;
return (u16)(p_chain->capacity - used);
}
static inline u8 qed_chain_is_full(struct qed_chain *p_chain)
static inline u32 qed_chain_get_elem_left_u32(struct qed_chain *p_chain)
{
return qed_chain_get_elem_left(p_chain) == p_chain->capacity;
}
u32 used;
static inline u8 qed_chain_is_empty(struct qed_chain *p_chain)
{
return qed_chain_get_elem_left(p_chain) == 0;
}
used = (u32) (((u64)0x100000000ULL +
(u64)p_chain->u.chain32.prod_idx) -
(u64)p_chain->u.chain32.cons_idx);
if (p_chain->mode == QED_CHAIN_MODE_NEXT_PTR)
used -= p_chain->u.chain32.prod_idx / p_chain->elem_per_page -
p_chain->u.chain32.cons_idx / p_chain->elem_per_page;
static inline u16 qed_chain_get_elem_per_page(
struct qed_chain *p_chain)
{
return p_chain->elem_per_page;
return p_chain->capacity - used;
}
static inline u16 qed_chain_get_usable_per_page(
struct qed_chain *p_chain)
static inline u16 qed_chain_get_usable_per_page(struct qed_chain *p_chain)
{
return p_chain->usable_per_page;
}
static inline u16 qed_chain_get_unusable_per_page(
struct qed_chain *p_chain)
static inline u16 qed_chain_get_unusable_per_page(struct qed_chain *p_chain)
{
return p_chain->elem_unusable;
}
static inline u16 qed_chain_get_size(struct qed_chain *p_chain)
static inline u32 qed_chain_get_page_cnt(struct qed_chain *p_chain)
{
return p_chain->size;
return p_chain->page_cnt;
}
static inline dma_addr_t
qed_chain_get_pbl_phys(struct qed_chain *p_chain)
static inline dma_addr_t qed_chain_get_pbl_phys(struct qed_chain *p_chain)
{
return p_chain->pbl.p_phys_table;
}
......@@ -172,64 +227,62 @@ qed_chain_get_pbl_phys(struct qed_chain *p_chain)
*/
static inline void
qed_chain_advance_page(struct qed_chain *p_chain,
void **p_next_elem,
u16 *idx_to_inc,
u16 *page_to_inc)
void **p_next_elem, void *idx_to_inc, void *page_to_inc)
{
struct qed_chain_next *p_next = NULL;
u32 page_index = 0;
switch (p_chain->mode) {
case QED_CHAIN_MODE_NEXT_PTR:
{
struct qed_chain_next *p_next = *p_next_elem;
p_next = *p_next_elem;
*p_next_elem = p_next->next_virt;
*idx_to_inc += p_chain->elem_unusable;
if (is_chain_u16(p_chain))
*(u16 *)idx_to_inc += p_chain->elem_unusable;
else
*(u32 *)idx_to_inc += p_chain->elem_unusable;
break;
}
case QED_CHAIN_MODE_SINGLE:
*p_next_elem = p_chain->p_virt_addr;
break;
case QED_CHAIN_MODE_PBL:
/* It is assumed pages are sequential, next element needs
* to change only when passing going back to first from last.
*/
if (++(*page_to_inc) == p_chain->page_cnt) {
*page_to_inc = 0;
*p_next_elem = p_chain->p_virt_addr;
if (is_chain_u16(p_chain)) {
if (++(*(u16 *)page_to_inc) == p_chain->page_cnt)
*(u16 *)page_to_inc = 0;
page_index = *(u16 *)page_to_inc;
} else {
if (++(*(u32 *)page_to_inc) == p_chain->page_cnt)
*(u32 *)page_to_inc = 0;
page_index = *(u32 *)page_to_inc;
}
*p_next_elem = p_chain->pbl.pp_virt_addr_tbl[page_index];
}
}
#define is_unusable_idx(p, idx) \
(((p)->idx & (p)->elem_per_page_mask) == (p)->usable_per_page)
(((p)->u.chain16.idx & (p)->elem_per_page_mask) == (p)->usable_per_page)
#define is_unusable_idx_u32(p, idx) \
(((p)->u.chain32.idx & (p)->elem_per_page_mask) == (p)->usable_per_page)
#define is_unusable_next_idx(p, idx) \
((((p)->u.chain16.idx + 1) & (p)->elem_per_page_mask) == \
(p)->usable_per_page)
#define is_unusable_next_idx(p, idx) \
((((p)->idx + 1) & (p)->elem_per_page_mask) == (p)->usable_per_page)
#define is_unusable_next_idx_u32(p, idx) \
((((p)->u.chain32.idx + 1) & (p)->elem_per_page_mask) == \
(p)->usable_per_page)
#define test_ans_skip(p, idx) \
#define test_and_skip(p, idx) \
do { \
if (is_unusable_idx(p, idx)) { \
(p)->idx += (p)->elem_unusable; \
if (is_chain_u16(p)) { \
if (is_unusable_idx(p, idx)) \
(p)->u.chain16.idx += (p)->elem_unusable; \
} else { \
if (is_unusable_idx_u32(p, idx)) \
(p)->u.chain32.idx += (p)->elem_unusable; \
} \
} while (0)
/**
* @brief qed_chain_return_multi_produced -
*
* A chain in which the driver "Produces" elements should use this API
* to indicate previous produced elements are now consumed.
*
* @param p_chain
* @param num
*/
static inline void
qed_chain_return_multi_produced(struct qed_chain *p_chain,
u16 num)
{
p_chain->cons_idx += num;
test_ans_skip(p_chain, cons_idx);
}
/**
* @brief qed_chain_return_produced -
*
......@@ -240,8 +293,11 @@ qed_chain_return_multi_produced(struct qed_chain *p_chain,
*/
static inline void qed_chain_return_produced(struct qed_chain *p_chain)
{
p_chain->cons_idx++;
test_ans_skip(p_chain, cons_idx);
if (is_chain_u16(p_chain))
p_chain->u.chain16.cons_idx++;
else
p_chain->u.chain32.cons_idx++;
test_and_skip(p_chain, cons_idx);
}
/**
......@@ -257,21 +313,33 @@ static inline void qed_chain_return_produced(struct qed_chain *p_chain)
*/
static inline void *qed_chain_produce(struct qed_chain *p_chain)
{
void *ret = NULL;
if ((p_chain->prod_idx & p_chain->elem_per_page_mask) ==
p_chain->next_page_mask) {
qed_chain_advance_page(p_chain, &p_chain->p_prod_elem,
&p_chain->prod_idx,
&p_chain->pbl.prod_page_idx);
void *p_ret = NULL, *p_prod_idx, *p_prod_page_idx;
if (is_chain_u16(p_chain)) {
if ((p_chain->u.chain16.prod_idx &
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
p_prod_idx = &p_chain->u.chain16.prod_idx;
p_prod_page_idx = &p_chain->pbl.u.pbl16.prod_page_idx;
qed_chain_advance_page(p_chain, &p_chain->p_prod_elem,
p_prod_idx, p_prod_page_idx);
}
p_chain->u.chain16.prod_idx++;
} else {
if ((p_chain->u.chain32.prod_idx &
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
p_prod_idx = &p_chain->u.chain32.prod_idx;
p_prod_page_idx = &p_chain->pbl.u.pbl32.prod_page_idx;
qed_chain_advance_page(p_chain, &p_chain->p_prod_elem,
p_prod_idx, p_prod_page_idx);
}
p_chain->u.chain32.prod_idx++;
}
ret = p_chain->p_prod_elem;
p_chain->prod_idx++;
p_ret = p_chain->p_prod_elem;
p_chain->p_prod_elem = (void *)(((u8 *)p_chain->p_prod_elem) +
p_chain->elem_size);
return ret;
return p_ret;
}
/**
......@@ -282,9 +350,9 @@ static inline void *qed_chain_produce(struct qed_chain *p_chain)
* @param p_chain
* @param num
*
* @return u16, number of unusable BDs
* @return number of unusable BDs
*/
static inline u16 qed_chain_get_capacity(struct qed_chain *p_chain)
static inline u32 qed_chain_get_capacity(struct qed_chain *p_chain)
{
return p_chain->capacity;
}
......@@ -297,11 +365,13 @@ static inline u16 qed_chain_get_capacity(struct qed_chain *p_chain)
*
* @param p_chain
*/
static inline void
qed_chain_recycle_consumed(struct qed_chain *p_chain)
static inline void qed_chain_recycle_consumed(struct qed_chain *p_chain)
{
test_ans_skip(p_chain, prod_idx);
p_chain->prod_idx++;
test_and_skip(p_chain, prod_idx);
if (is_chain_u16(p_chain))
p_chain->u.chain16.prod_idx++;
else
p_chain->u.chain32.prod_idx++;
}
/**
......@@ -316,21 +386,33 @@ qed_chain_recycle_consumed(struct qed_chain *p_chain)
*/
static inline void *qed_chain_consume(struct qed_chain *p_chain)
{
void *ret = NULL;
if ((p_chain->cons_idx & p_chain->elem_per_page_mask) ==
p_chain->next_page_mask) {
void *p_ret = NULL, *p_cons_idx, *p_cons_page_idx;
if (is_chain_u16(p_chain)) {
if ((p_chain->u.chain16.cons_idx &
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
p_cons_idx = &p_chain->u.chain16.cons_idx;
p_cons_page_idx = &p_chain->pbl.u.pbl16.cons_page_idx;
qed_chain_advance_page(p_chain, &p_chain->p_cons_elem,
p_cons_idx, p_cons_page_idx);
}
p_chain->u.chain16.cons_idx++;
} else {
if ((p_chain->u.chain32.cons_idx &
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
p_cons_idx = &p_chain->u.chain32.cons_idx;
p_cons_page_idx = &p_chain->pbl.u.pbl32.cons_page_idx;
qed_chain_advance_page(p_chain, &p_chain->p_cons_elem,
&p_chain->cons_idx,
&p_chain->pbl.cons_page_idx);
p_cons_idx, p_cons_page_idx);
}
p_chain->u.chain32.cons_idx++;
}
ret = p_chain->p_cons_elem;
p_chain->cons_idx++;
p_ret = p_chain->p_cons_elem;
p_chain->p_cons_elem = (void *)(((u8 *)p_chain->p_cons_elem) +
p_chain->elem_size);
return ret;
return p_ret;
}
/**
......@@ -340,16 +422,33 @@ static inline void *qed_chain_consume(struct qed_chain *p_chain)
*/
static inline void qed_chain_reset(struct qed_chain *p_chain)
{
int i;
p_chain->prod_idx = 0;
p_chain->cons_idx = 0;
p_chain->p_cons_elem = p_chain->p_virt_addr;
p_chain->p_prod_elem = p_chain->p_virt_addr;
u32 i;
if (is_chain_u16(p_chain)) {
p_chain->u.chain16.prod_idx = 0;
p_chain->u.chain16.cons_idx = 0;
} else {
p_chain->u.chain32.prod_idx = 0;
p_chain->u.chain32.cons_idx = 0;
}
p_chain->p_cons_elem = p_chain->p_virt_addr;
p_chain->p_prod_elem = p_chain->p_virt_addr;
if (p_chain->mode == QED_CHAIN_MODE_PBL) {
p_chain->pbl.prod_page_idx = p_chain->page_cnt - 1;
p_chain->pbl.cons_page_idx = p_chain->page_cnt - 1;
/* Use (page_cnt - 1) as a reset value for the prod/cons page's
* indices, to avoid unnecessary page advancing on the first
* call to qed_chain_produce/consume. Instead, the indices
* will be advanced to page_cnt and then will be wrapped to 0.
*/
u32 reset_val = p_chain->page_cnt - 1;
if (is_chain_u16(p_chain)) {
p_chain->pbl.u.pbl16.prod_page_idx = (u16)reset_val;
p_chain->pbl.u.pbl16.cons_page_idx = (u16)reset_val;
} else {
p_chain->pbl.u.pbl32.prod_page_idx = reset_val;
p_chain->pbl.u.pbl32.cons_page_idx = reset_val;
}
}
switch (p_chain->intended_use) {
......@@ -377,168 +476,184 @@ static inline void qed_chain_reset(struct qed_chain *p_chain)
* @param intended_use
* @param mode
*/
static inline void qed_chain_init(struct qed_chain *p_chain,
void *p_virt_addr,
dma_addr_t p_phys_addr,
u16 page_cnt,
u8 elem_size,
enum qed_chain_use_mode intended_use,
enum qed_chain_mode mode)
static inline void qed_chain_init_params(struct qed_chain *p_chain,
u32 page_cnt,
u8 elem_size,
enum qed_chain_use_mode intended_use,
enum qed_chain_mode mode,
enum qed_chain_cnt_type cnt_type)
{
/* chain fixed parameters */
p_chain->p_virt_addr = p_virt_addr;
p_chain->p_phys_addr = p_phys_addr;
p_chain->p_virt_addr = NULL;
p_chain->p_phys_addr = 0;
p_chain->elem_size = elem_size;
p_chain->page_cnt = page_cnt;
p_chain->intended_use = intended_use;
p_chain->mode = mode;
p_chain->cnt_type = cnt_type;
p_chain->intended_use = intended_use;
p_chain->elem_per_page = ELEMS_PER_PAGE(elem_size);
p_chain->usable_per_page =
USABLE_ELEMS_PER_PAGE(elem_size, mode);
p_chain->capacity = p_chain->usable_per_page * page_cnt;
p_chain->size = p_chain->elem_per_page * page_cnt;
p_chain->usable_per_page = USABLE_ELEMS_PER_PAGE(elem_size, mode);
p_chain->elem_per_page_mask = p_chain->elem_per_page - 1;
p_chain->elem_unusable = UNUSABLE_ELEMS_PER_PAGE(elem_size, mode);
p_chain->next_page_mask = (p_chain->usable_per_page &
p_chain->elem_per_page_mask);
if (mode == QED_CHAIN_MODE_NEXT_PTR) {
struct qed_chain_next *p_next;
u16 i;
for (i = 0; i < page_cnt - 1; i++) {
/* Increment mem_phy to the next page. */
p_phys_addr += QED_CHAIN_PAGE_SIZE;
/* Initialize the physical address of the next page. */
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr +
elem_size *
p_chain->
usable_per_page);
p_next->next_phys.lo = DMA_LO_LE(p_phys_addr);
p_next->next_phys.hi = DMA_HI_LE(p_phys_addr);
/* Initialize the virtual address of the next page. */
p_next->next_virt = (void *)((u8 *)p_virt_addr +
QED_CHAIN_PAGE_SIZE);
/* Move to the next page. */
p_virt_addr = p_next->next_virt;
}
/* Last page's next should point to beginning of the chain */
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr +
elem_size *
p_chain->usable_per_page);
p_chain->page_cnt = page_cnt;
p_chain->capacity = p_chain->usable_per_page * page_cnt;
p_chain->size = p_chain->elem_per_page * page_cnt;
p_next->next_phys.lo = DMA_LO_LE(p_chain->p_phys_addr);
p_next->next_phys.hi = DMA_HI_LE(p_chain->p_phys_addr);
p_next->next_virt = p_chain->p_virt_addr;
}
qed_chain_reset(p_chain);
p_chain->pbl.p_phys_table = 0;
p_chain->pbl.p_virt_table = NULL;
p_chain->pbl.pp_virt_addr_tbl = NULL;
}
/**
* @brief qed_chain_pbl_init - Initalizes a basic pbl chain
* struct
* @brief qed_chain_init_mem -
*
* Initalizes a basic chain struct with its chain buffers
*
* @param p_chain
* @param p_virt_addr virtual address of allocated buffer's beginning
* @param p_phys_addr physical address of allocated buffer's beginning
* @param page_cnt number of pages in the allocated buffer
* @param elem_size size of each element in the chain
* @param use_mode
* @param p_phys_pbl pointer to a pre-allocated side table
* which will hold physical page addresses.
* @param p_virt_pbl pointer to a pre allocated side table
* which will hold virtual page addresses.
*
*/
static inline void
qed_chain_pbl_init(struct qed_chain *p_chain,
void *p_virt_addr,
dma_addr_t p_phys_addr,
u16 page_cnt,
u8 elem_size,
enum qed_chain_use_mode use_mode,
dma_addr_t p_phys_pbl,
dma_addr_t *p_virt_pbl)
static inline void qed_chain_init_mem(struct qed_chain *p_chain,
void *p_virt_addr, dma_addr_t p_phys_addr)
{
dma_addr_t *p_pbl_dma = p_virt_pbl;
int i;
qed_chain_init(p_chain, p_virt_addr, p_phys_addr, page_cnt,
elem_size, use_mode, QED_CHAIN_MODE_PBL);
p_chain->p_virt_addr = p_virt_addr;
p_chain->p_phys_addr = p_phys_addr;
}
/**
* @brief qed_chain_init_pbl_mem -
*
* Initalizes a basic chain struct with its pbl buffers
*
* @param p_chain
* @param p_virt_pbl pointer to a pre allocated side table which will hold
* virtual page addresses.
* @param p_phys_pbl pointer to a pre-allocated side table which will hold
* physical page addresses.
* @param pp_virt_addr_tbl
* pointer to a pre-allocated side table which will hold
* the virtual addresses of the chain pages.
*
*/
static inline void qed_chain_init_pbl_mem(struct qed_chain *p_chain,
void *p_virt_pbl,
dma_addr_t p_phys_pbl,
void **pp_virt_addr_tbl)
{
p_chain->pbl.p_phys_table = p_phys_pbl;
p_chain->pbl.p_virt_table = p_virt_pbl;
/* Fill the PBL with physical addresses*/
for (i = 0; i < page_cnt; i++) {
*p_pbl_dma = p_phys_addr;
p_phys_addr += QED_CHAIN_PAGE_SIZE;
p_pbl_dma++;
}
p_chain->pbl.pp_virt_addr_tbl = pp_virt_addr_tbl;
}
/**
* @brief qed_chain_set_prod - sets the prod to the given
* value
* @brief qed_chain_init_next_ptr_elem -
*
* Initalizes a next pointer element
*
* @param p_chain
* @param p_virt_curr virtual address of a chain page of which the next
* pointer element is initialized
* @param p_virt_next virtual address of the next chain page
* @param p_phys_next physical address of the next chain page
*
* @param prod_idx
* @param p_prod_elem
*/
static inline void qed_chain_set_prod(struct qed_chain *p_chain,
u16 prod_idx,
void *p_prod_elem)
static inline void
qed_chain_init_next_ptr_elem(struct qed_chain *p_chain,
void *p_virt_curr,
void *p_virt_next, dma_addr_t p_phys_next)
{
p_chain->prod_idx = prod_idx;
p_chain->p_prod_elem = p_prod_elem;
struct qed_chain_next *p_next;
u32 size;
size = p_chain->elem_size * p_chain->usable_per_page;
p_next = (struct qed_chain_next *)((u8 *)p_virt_curr + size);
DMA_REGPAIR_LE(p_next->next_phys, p_phys_next);
p_next->next_virt = p_virt_next;
}
/**
* @brief qed_chain_get_elem -
* @brief qed_chain_get_last_elem -
*
* get a pointer to an element represented by absolute idx
* Returns a pointer to the last element of the chain
*
* @param p_chain
* @assumption p_chain->size is a power of 2
*
* @return void*, a pointer to next element
* @return void*
*/
static inline void *qed_chain_sge_get_elem(struct qed_chain *p_chain,
u16 idx)
static inline void *qed_chain_get_last_elem(struct qed_chain *p_chain)
{
void *ret = NULL;
if (idx >= p_chain->size)
return NULL;
struct qed_chain_next *p_next = NULL;
void *p_virt_addr = NULL;
u32 size, last_page_idx;
ret = (u8 *)p_chain->p_virt_addr + p_chain->elem_size * idx;
if (!p_chain->p_virt_addr)
goto out;
return ret;
switch (p_chain->mode) {
case QED_CHAIN_MODE_NEXT_PTR:
size = p_chain->elem_size * p_chain->usable_per_page;
p_virt_addr = p_chain->p_virt_addr;
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr + size);
while (p_next->next_virt != p_chain->p_virt_addr) {
p_virt_addr = p_next->next_virt;
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr +
size);
}
break;
case QED_CHAIN_MODE_SINGLE:
p_virt_addr = p_chain->p_virt_addr;
break;
case QED_CHAIN_MODE_PBL:
last_page_idx = p_chain->page_cnt - 1;
p_virt_addr = p_chain->pbl.pp_virt_addr_tbl[last_page_idx];
break;
}
/* p_virt_addr points at this stage to the last page of the chain */
size = p_chain->elem_size * (p_chain->usable_per_page - 1);
p_virt_addr = (u8 *)p_virt_addr + size;
out:
return p_virt_addr;
}
/**
* @brief qed_chain_sge_inc_cons_prod
* @brief qed_chain_set_prod - sets the prod to the given value
*
* for sge chains, producer isn't increased serially, the ring
* is expected to be full at all times. Once elements are
* consumed, they are immediately produced.
* @param prod_idx
* @param p_prod_elem
*/
static inline void qed_chain_set_prod(struct qed_chain *p_chain,
u32 prod_idx, void *p_prod_elem)
{
if (is_chain_u16(p_chain))
p_chain->u.chain16.prod_idx = (u16) prod_idx;
else
p_chain->u.chain32.prod_idx = prod_idx;
p_chain->p_prod_elem = p_prod_elem;
}
/**
* @brief qed_chain_pbl_zero_mem - set chain memory to 0
*
* @param p_chain
* @param cnt
*
* @return inline void
*/
static inline void
qed_chain_sge_inc_cons_prod(struct qed_chain *p_chain,
u16 cnt)
static inline void qed_chain_pbl_zero_mem(struct qed_chain *p_chain)
{
p_chain->prod_idx += cnt;
p_chain->cons_idx += cnt;
u32 i, page_cnt;
if (p_chain->mode != QED_CHAIN_MODE_PBL)
return;
page_cnt = qed_chain_get_page_cnt(p_chain);
for (i = 0; i < page_cnt; i++)
memset(p_chain->pbl.pp_virt_addr_tbl[i], 0,
QED_CHAIN_PAGE_SIZE);
}
#endif
include/linux/qed/qed_if.h
View file @ 03c7f70b
......@@ -58,8 +58,70 @@ struct qed_eth_pf_params {
u16 num_cons;
};
/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
struct qed_iscsi_pf_params {
u64 glbl_q_params_addr;
u64 bdq_pbl_base_addr[2];
u32 max_cwnd;
u16 cq_num_entries;
u16 cmdq_num_entries;
u16 dup_ack_threshold;
u16 tx_sws_timer;
u16 min_rto;
u16 min_rto_rt;
u16 max_rto;
/* The following parameters are used during HW-init
* and these parameters need to be passed as arguments
* to update_pf_params routine invoked before slowpath start
*/
u16 num_cons;
u16 num_tasks;
/* The following parameters are used during protocol-init */
u16 half_way_close_timeout;
u16 bdq_xoff_threshold[2];
u16 bdq_xon_threshold[2];
u16 cmdq_xoff_threshold;
u16 cmdq_xon_threshold;
u16 rq_buffer_size;
u8 num_sq_pages_in_ring;
u8 num_r2tq_pages_in_ring;
u8 num_uhq_pages_in_ring;
u8 num_queues;
u8 log_page_size;
u8 rqe_log_size;
u8 max_fin_rt;
u8 gl_rq_pi;
u8 gl_cmd_pi;
u8 debug_mode;
u8 ll2_ooo_queue_id;
u8 ooo_enable;
u8 is_target;
u8 bdq_pbl_num_entries[2];
};
struct qed_rdma_pf_params {
/* Supplied to QED during resource allocation (may affect the ILT and
* the doorbell BAR).
*/
u32 min_dpis; /* number of requested DPIs */
u32 num_mrs; /* number of requested memory regions */
u32 num_qps; /* number of requested Queue Pairs */
u32 num_srqs; /* number of requested SRQ */
u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
u8 gl_pi; /* protocol index */
/* Will allocate rate limiters to be used with QPs */
u8 enable_dcqcn;
};
struct qed_pf_params {
struct qed_eth_pf_params eth_pf_params;
struct qed_iscsi_pf_params iscsi_pf_params;
struct qed_rdma_pf_params rdma_pf_params;
};
enum qed_int_mode {
......@@ -100,6 +162,8 @@ struct qed_dev_info {
/* MFW version */
u32 mfw_rev;
bool rdma_supported;
u32 flash_size;
u8 mf_mode;
bool tx_switching;
......@@ -111,6 +175,7 @@ enum qed_sb_type {
enum qed_protocol {
QED_PROTOCOL_ETH,
QED_PROTOCOL_ISCSI,
};
struct qed_link_params {
......@@ -325,7 +390,8 @@ struct qed_common_ops {
int (*chain_alloc)(struct qed_dev *cdev,
enum qed_chain_use_mode intended_use,
enum qed_chain_mode mode,
u16 num_elems,
enum qed_chain_cnt_type cnt_type,
u32 num_elems,
size_t elem_size,
struct qed_chain *p_chain);
......
include/linux/qed/rdma_common.h 0 → 100644
View file @ 03c7f70b
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef __RDMA_COMMON__
#define __RDMA_COMMON__
/************************/
/* RDMA FW CONSTANTS */
/************************/
#define RDMA_RESERVED_LKEY (0)
#define RDMA_RING_PAGE_SIZE (0x1000)
#define RDMA_MAX_SGE_PER_SQ_WQE (4)
#define RDMA_MAX_SGE_PER_RQ_WQE (4)
#define RDMA_MAX_DATA_SIZE_IN_WQE (0x7FFFFFFF)
#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
#define RDMA_MAX_CQS (64 * 1024)
#define RDMA_MAX_TIDS (128 * 1024 - 1)
#define RDMA_MAX_PDS (64 * 1024)
#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
#define RDMA_TASK_TYPE (PROTOCOLID_ROCE)
struct rdma_srq_id {
__le16 srq_idx;
__le16 opaque_fid;
};
struct rdma_srq_producers {
__le32 sge_prod;
__le32 wqe_prod;
};
#endif /* __RDMA_COMMON__ */
include/linux/qed/roce_common.h 0 → 100644
View file @ 03c7f70b
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef __ROCE_COMMON__
#define __ROCE_COMMON__
#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
#define ROCE_MAX_QPS (32 * 1024)
#endif /* __ROCE_COMMON__ */
include/linux/qed/storage_common.h 0 → 100644
View file @ 03c7f70b
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef __STORAGE_COMMON__
#define __STORAGE_COMMON__
#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2)
#define BDQ_NUM_RESOURCES (4)
#define BDQ_ID_RQ (0)
#define BDQ_ID_IMM_DATA (1)
#define BDQ_NUM_IDS (2)
#define BDQ_MAX_EXTERNAL_RING_SIZE (1 << 15)
struct scsi_bd {
struct regpair address;
struct regpair opaque;
};
struct scsi_bdq_ram_drv_data {
__le16 external_producer;
__le16 reserved0[3];
};
struct scsi_drv_cmdq {
__le16 cmdq_cons;
__le16 reserved0;
__le32 reserved1;
};
struct scsi_init_func_params {
__le16 num_tasks;
u8 log_page_size;
u8 debug_mode;
u8 reserved2[12];
};
struct scsi_init_func_queues {
struct regpair glbl_q_params_addr;
__le16 rq_buffer_size;
__le16 cq_num_entries;
__le16 cmdq_num_entries;
u8 bdq_resource_id;
u8 q_validity;
#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0
#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1
#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2
#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_MASK 0x1F
#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_SHIFT 3
u8 num_queues;
u8 queue_relative_offset;
u8 cq_sb_pi;
u8 cmdq_sb_pi;
__le16 cq_cmdq_sb_num_arr[NUM_OF_CMDQS_CQS];
__le16 reserved0;
u8 bdq_pbl_num_entries[BDQ_NUM_IDS];
struct regpair bdq_pbl_base_address[BDQ_NUM_IDS];
__le16 bdq_xoff_threshold[BDQ_NUM_IDS];
__le16 bdq_xon_threshold[BDQ_NUM_IDS];
__le16 cmdq_xoff_threshold;
__le16 cmdq_xon_threshold;
__le32 reserved1;
};
struct scsi_ram_per_bdq_resource_drv_data {
struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS];
};
struct scsi_sge {
struct regpair sge_addr;
__le16 sge_len;
__le16 reserved0;
__le32 reserved1;
};
struct scsi_terminate_extra_params {
__le16 unsolicited_cq_count;
__le16 cmdq_count;
u8 reserved[4];
};
#endif /* __STORAGE_COMMON__ */
include/linux/qed/tcp_common.h 0 → 100644
View file @ 03c7f70b
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef __TCP_COMMON__
#define __TCP_COMMON__
#define TCP_INVALID_TIMEOUT_VAL -1
enum tcp_connect_mode {
TCP_CONNECT_ACTIVE,
TCP_CONNECT_PASSIVE,
MAX_TCP_CONNECT_MODE
};
struct tcp_init_params {
__le32 max_cwnd;
__le16 dup_ack_threshold;
__le16 tx_sws_timer;
__le16 min_rto;
__le16 min_rto_rt;
__le16 max_rto;
u8 maxfinrt;
u8 reserved[1];
};
enum tcp_ip_version {
TCP_IPV4,
TCP_IPV6,
MAX_TCP_IP_VERSION
};
struct tcp_offload_params {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
__le16 local_mac_addr_hi;
__le16 remote_mac_addr_lo;
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
__le16 vlan_id;
u8 flags;
#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0
#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1
#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2
#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 3
#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 4
#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1
#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 5
#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1
#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 6
#define TCP_OFFLOAD_PARAMS_RESERVED0_MASK 0x1
#define TCP_OFFLOAD_PARAMS_RESERVED0_SHIFT 7
u8 ip_version;
__le32 remote_ip[4];
__le32 local_ip[4];
__le32 flow_label;
u8 ttl;
u8 tos_or_tc;
__le16 remote_port;
__le16 local_port;
__le16 mss;
u8 rcv_wnd_scale;
u8 connect_mode;
__le16 srtt;
__le32 cwnd;
__le32 ss_thresh;
__le16 reserved1;
u8 ka_max_probe_cnt;
u8 dup_ack_theshold;
__le32 rcv_next;
__le32 snd_una;
__le32 snd_next;
__le32 snd_max;
__le32 snd_wnd;
__le32 rcv_wnd;
__le32 snd_wl1;
__le32 ts_time;
__le32 ts_recent;
__le32 ts_recent_age;
__le32 total_rt;
__le32 ka_timeout_delta;
__le32 rt_timeout_delta;
u8 dup_ack_cnt;
u8 snd_wnd_probe_cnt;
u8 ka_probe_cnt;
u8 rt_cnt;
__le16 rtt_var;
__le16 reserved2;
__le32 ka_timeout;
__le32 ka_interval;
__le32 max_rt_time;
__le32 initial_rcv_wnd;
u8 snd_wnd_scale;
u8 ack_frequency;
__le16 da_timeout_value;
__le32 ts_ticks_per_second;
};
struct tcp_offload_params_opt2 {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
__le16 local_mac_addr_hi;
__le16 remote_mac_addr_lo;
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
__le16 vlan_id;
u8 flags;
#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0
#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1
#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1
#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2
#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0x1F
#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 3
u8 ip_version;
__le32 remote_ip[4];
__le32 local_ip[4];
__le32 flow_label;
u8 ttl;
u8 tos_or_tc;
__le16 remote_port;
__le16 local_port;
__le16 mss;
u8 rcv_wnd_scale;
u8 connect_mode;
__le16 syn_ip_payload_length;
__le32 syn_phy_addr_lo;
__le32 syn_phy_addr_hi;
__le32 reserved1[22];
};
enum tcp_seg_placement_event {
TCP_EVENT_ADD_PEN,
TCP_EVENT_ADD_NEW_ISLE,
TCP_EVENT_ADD_ISLE_RIGHT,
TCP_EVENT_ADD_ISLE_LEFT,
TCP_EVENT_JOIN,
TCP_EVENT_NOP,
MAX_TCP_SEG_PLACEMENT_EVENT
};
struct tcp_update_params {
__le16 flags;
#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0
#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1
#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2
#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3
#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4
#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5
#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6
#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7
#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8
#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9
#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10
#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1
#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11
#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1
#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12
#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1
#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13
#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1
#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14
#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1
#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15
__le16 remote_mac_addr_lo;
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
__le16 mss;
u8 ttl;
u8 tos_or_tc;
__le32 ka_timeout;
__le32 ka_interval;
__le32 max_rt_time;
__le32 flow_label;
__le32 initial_rcv_wnd;
u8 ka_max_probe_cnt;
u8 reserved1[7];
};
struct tcp_upload_params {
__le32 rcv_next;
__le32 snd_una;
__le32 snd_next;
__le32 snd_max;
__le32 snd_wnd;
__le32 rcv_wnd;
__le32 snd_wl1;
__le32 cwnd;
__le32 ss_thresh;
__le16 srtt;
__le16 rtt_var;
__le32 ts_time;
__le32 ts_recent;
__le32 ts_recent_age;
__le32 total_rt;
__le32 ka_timeout_delta;
__le32 rt_timeout_delta;
u8 dup_ack_cnt;
u8 snd_wnd_probe_cnt;
u8 ka_probe_cnt;
u8 rt_cnt;
__le32 reserved;
};
#endif /* __TCP_COMMON__ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7