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Commit 05aa0eb3 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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arm64: dts: qcom: sdm660: Make the DTS an overlay on top of 630 

There is SO MUCH common code between these two SoCs that it makes
no sense to keep what is essentially a duplicate of 630.dtsi. Instead,
it's better to just change the things that differ.
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210728222542.54269-25-konrad.dybcio@somainline.orgSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 4bf09754
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arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
View file @ 05aa0eb3
...@@ -37,8 +37,6 @@ ramoops@a0000000 { ...@@ -37,8 +37,6 @@ ramoops@a0000000 {
&blsp1_uart2 { &blsp1_uart2 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart_console_active>;
}; };
&tlmm { &tlmm {
......
arch/arm64/boot/dts/qcom/sdm660.dtsi
View file @ 05aa0eb3
...@@ -2,371 +2,157 @@ ...@@ -2,371 +2,157 @@
/* /*
* Copyright (c) 2018, Craig Tatlor. * Copyright (c) 2018, Craig Tatlor.
* Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com> * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
* Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
* Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
* Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
*/ */
#include <dt-bindings/interrupt-controller/arm-gic.h> #include "sdm630.dtsi"
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
/ { &adreno_gpu {
interrupt-parent = <&intc>; compatible = "qcom,adreno-512.0", "qcom,adreno";
operating-points-v2 = <&gpu_sdm660_opp_table>;
#address-cells = <2>; gpu_sdm660_opp_table: opp-table {
#size-cells = <2>; compatible = "operating-points-v2";
chosen { }; /*
* 775MHz is only available on the highest speed bin
* Though it cannot be used for now due to interconnect
* framework not supporting multiple frequencies
* at the same opp-level
clocks { opp-750000000 {
xo_board: xo_board { opp-hz = /bits/ 64 <750000000>;
compatible = "fixed-clock"; opp-level = <RPM_SMD_LEVEL_TURBO>;
#clock-cells = <0>; opp-peak-kBps = <5412000>;
clock-frequency = <19200000>; opp-supported-hw = <0xCHECKME>;
clock-output-names = "xo_board";
}; };
sleep_clk: sleep_clk { * These OPPs are correct, but we are lacking support for the
compatible = "fixed-clock"; * GPU regulator. Hence, disable them for now to prevent the
#clock-cells = <0>; * platform from hanging on high graphics loads.
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@100 { opp-700000000 {
device_type = "cpu"; opp-hz = /bits/ 64 <700000000>;
compatible = "qcom,kryo260"; opp-level = <RPM_SMD_LEVEL_TURBO>;
reg = <0x0 0x100>; opp-peak-kBps = <5184000>;
enable-method = "psci"; opp-supported-hw = <0xFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
L1_I_100: l1-icache {
compatible = "cache";
};
L1_D_100: l1-dcache {
compatible = "cache";
};
}; };
CPU1: cpu@101 { opp-647000000 {
device_type = "cpu"; opp-hz = /bits/ 64 <647000000>;
compatible = "qcom,kryo260"; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
reg = <0x0 0x101>; opp-peak-kBps = <4068000>;
enable-method = "psci"; opp-supported-hw = <0xFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
compatible = "cache";
};
L1_D_101: l1-dcache {
compatible = "cache";
};
}; };
CPU2: cpu@102 { opp-588000000 {
device_type = "cpu"; opp-hz = /bits/ 64 <588000000>;
compatible = "qcom,kryo260"; opp-level = <RPM_SMD_LEVEL_NOM>;
reg = <0x0 0x102>; opp-peak-kBps = <3072000>;
enable-method = "psci"; opp-supported-hw = <0xFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
compatible = "cache";
};
L1_D_102: l1-dcache {
compatible = "cache";
};
}; };
CPU3: cpu@103 { opp-465000000 {
device_type = "cpu"; opp-hz = /bits/ 64 <465000000>;
compatible = "qcom,kryo260"; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
reg = <0x0 0x103>; opp-peak-kBps = <2724000>;
enable-method = "psci"; opp-supported-hw = <0xFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
compatible = "cache";
};
L1_D_103: l1-dcache {
compatible = "cache";
};
}; };
CPU4: cpu@0 { opp-370000000 {
device_type = "cpu"; opp-hz = /bits/ 64 <370000000>;
compatible = "qcom,kryo260"; opp-level = <RPM_SMD_LEVEL_SVS>;
reg = <0x0 0x0>; opp-peak-kBps = <2188000>;
enable-method = "psci"; opp-supported-hw = <0xFF>;
capacity-dmips-mhz = <640>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
L1_I_0: l1-icache {
compatible = "cache";
};
L1_D_0: l1-dcache {
compatible = "cache";
};
}; };
*/
CPU5: cpu@1 { opp-266000000 {
device_type = "cpu"; opp-hz = /bits/ 64 <266000000>;
compatible = "qcom,kryo260"; opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
reg = <0x0 0x1>; opp-peak-kBps = <1648000>;
enable-method = "psci"; opp-supported-hw = <0xFF>;
capacity-dmips-mhz = <640>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "cache";
};
L1_D_1: l1-dcache {
compatible = "cache";
};
}; };
CPU6: cpu@2 { opp-160000000 {
device_type = "cpu"; opp-hz = /bits/ 64 <160000000>;
compatible = "qcom,kryo260"; opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
reg = <0x0 0x2>; opp-peak-kBps = <1200000>;
enable-method = "psci"; opp-supported-hw = <0xFF>;
capacity-dmips-mhz = <640>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "cache";
};
L1_D_2: l1-dcache {
compatible = "cache";
};
}; };
CPU7: cpu@3 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x3>;
enable-method = "psci";
capacity-dmips-mhz = <640>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "cache";
};
L1_D_3: l1-dcache {
compatible = "cache";
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
cluster1 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
};
firmware {
scm {
compatible = "qcom,scm";
};
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
}; };
};
soc: soc { &CPU0 {
#address-cells = <1>; compatible = "qcom,kryo260";
#size-cells = <1>; capacity-dmips-mhz = <1024>;
ranges = <0 0 0 0xffffffff>; /delete-property/ operating-points-v2;
compatible = "simple-bus"; };
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdm660";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x00100000 0x94000>;
};
tlmm: pinctrl@3100000 {
compatible = "qcom,sdm660-pinctrl";
reg = <0x03100000 0x400000>,
<0x03500000 0x400000>,
<0x03900000 0x400000>;
reg-names = "south", "center", "north";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 114>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart_console_active: uart_console_active {
pinmux {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
pinconf { &CPU1 {
pins = "gpio4", "gpio5"; compatible = "qcom,kryo260";
drive-strength = <2>; capacity-dmips-mhz = <1024>;
bias-disable; /delete-property/ operating-points-v2;
}; };
};
};
spmi_bus: spmi@800f000 { &CPU2 {
compatible = "qcom,spmi-pmic-arb"; compatible = "qcom,kryo260";
reg = <0x0800f000 0x1000>, capacity-dmips-mhz = <1024>;
<0x08400000 0x1000000>, /delete-property/ operating-points-v2;
<0x09400000 0x1000000>, };
<0x0a400000 0x220000>,
<0x0800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
blsp1_uart2: serial@c170000 { &CPU3 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; compatible = "qcom,kryo260";
reg = <0x0c170000 0x1000>; capacity-dmips-mhz = <1024>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /delete-property/ operating-points-v2;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, };
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
timer@17920000 { &CPU4 {
#address-cells = <1>; compatible = "qcom,kryo260";
#size-cells = <1>; capacity-dmips-mhz = <640>;
ranges; /delete-property/ operating-points-v2;
compatible = "arm,armv7-timer-mem"; };
reg = <0x17920000 0x1000>;
frame@17921000 { &CPU5 {
frame-number = <0>; compatible = "qcom,kryo260";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, capacity-dmips-mhz = <640>;
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /delete-property/ operating-points-v2;
reg = <0x17921000 0x1000>, };
<0x17922000 0x1000>;
};
frame@17923000 { &CPU6 {
frame-number = <1>; compatible = "qcom,kryo260";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; capacity-dmips-mhz = <640>;
reg = <0x17923000 0x1000>; /delete-property/ operating-points-v2;
status = "disabled"; };
};
frame@17924000 { &CPU7 {
frame-number = <2>; compatible = "qcom,kryo260";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; capacity-dmips-mhz = <640>;
reg = <0x17924000 0x1000>; /delete-property/ operating-points-v2;
status = "disabled"; };
};
frame@17925000 { &gcc {
frame-number = <3>; compatible = "qcom,gcc-sdm660";
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; };
reg = <0x17925000 0x1000>;
status = "disabled";
};
frame@17926000 { &gpucc {
frame-number = <4>; compatible = "qcom,gpucc-sdm660";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; };
reg = <0x17926000 0x1000>;
status = "disabled";
};
frame@17927000 { &mmcc {
frame-number = <5>; compatible = "qcom,mmcc-sdm660";
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; /*
reg = <0x17927000 0x1000>; * 660 has one more dsi host/phy, which - when implemented
status = "disabled"; * and tested - should be added to the clocks property.
}; */
};
frame@17928000 { &tlmm {
frame-number = <6>; compatible = "qcom,sdm660-pinctrl";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; };
reg = <0x17928000 0x1000>;
status = "disabled";
};
};
intc: interrupt-controller@17a00000 { &tsens {
compatible = "arm,gic-v3"; #qcom,sensors = <14>;
reg = <0x17a00000 0x10000>,
<0x17b00000 0x100000>;
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
}; };
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