Commit 0a58d668 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller

tg3: Reintroduce 5717_PLUS

This patch reintroduces the TG3_FLG3_5717_PLUS to identify 5717 and
later devices.
Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1407deb1
...@@ -1042,8 +1042,7 @@ static int tg3_mdio_init(struct tg3 *tp) ...@@ -1042,8 +1042,7 @@ static int tg3_mdio_init(struct tg3 *tp)
u32 reg; u32 reg;
struct phy_device *phydev; struct phy_device *phydev;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
u32 is_serdes; u32 is_serdes;
tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1; tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
...@@ -1621,8 +1620,7 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) ...@@ -1621,8 +1620,7 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
u32 reg; u32 reg;
if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
(tp->phy_flags & TG3_PHYFLG_MII_SERDES))) (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
return; return;
...@@ -2045,8 +2043,7 @@ static int tg3_phy_reset(struct tg3 *tp) ...@@ -2045,8 +2043,7 @@ static int tg3_phy_reset(struct tg3 *tp)
} }
} }
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
return 0; return 0;
...@@ -7671,8 +7668,7 @@ static void tg3_rings_reset(struct tg3 *tp) ...@@ -7671,8 +7668,7 @@ static void tg3_rings_reset(struct tg3 *tp)
/* Disable all transmit rings but the first. */ /* Disable all transmit rings but the first. */
if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
...@@ -7686,8 +7682,7 @@ static void tg3_rings_reset(struct tg3 *tp) ...@@ -7686,8 +7682,7 @@ static void tg3_rings_reset(struct tg3 *tp)
/* Disable all receive return rings but the first. */ /* Disable all receive return rings but the first. */
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
...@@ -8089,8 +8084,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) ...@@ -8089,8 +8084,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
((u64) tpr->rx_std_mapping >> 32)); ((u64) tpr->rx_std_mapping >> 32));
tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
((u64) tpr->rx_std_mapping & 0xffffffff)); ((u64) tpr->rx_std_mapping & 0xffffffff));
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
NIC_SRAM_RX_BUFFER_DESC); NIC_SRAM_RX_BUFFER_DESC);
...@@ -10848,8 +10842,7 @@ static int tg3_test_memory(struct tg3 *tp) ...@@ -10848,8 +10842,7 @@ static int tg3_test_memory(struct tg3 *tp)
int err = 0; int err = 0;
int i; int i;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
mem_tbl = mem_tbl_5717; mem_tbl = mem_tbl_5717;
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
mem_tbl = mem_tbl_57765; mem_tbl = mem_tbl_57765;
...@@ -11930,8 +11923,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) ...@@ -11930,8 +11923,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
tg3_get_57780_nvram_info(tp); tg3_get_57780_nvram_info(tp);
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
tg3_get_5717_nvram_info(tp); tg3_get_5717_nvram_info(tp);
else else
tg3_get_nvram_info(tp); tg3_get_nvram_info(tp);
...@@ -13333,8 +13325,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -13333,8 +13325,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
tp->pdev_peer = tg3_find_peer(tp); tp->pdev_peer = tg3_find_peer(tp);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
tp->tg3_flags3 |= TG3_FLG3_57765_PLUS; tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
/* Intentionally exclude ASIC_REV_5906 */ /* Intentionally exclude ASIC_REV_5906 */
...@@ -13427,8 +13422,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -13427,8 +13422,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
} }
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP; tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
...@@ -13962,8 +13956,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp) ...@@ -13962,8 +13956,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
else else
tg3_nvram_unlock(tp); tg3_nvram_unlock(tp);
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
if (PCI_FUNC(tp->pdev->devfn) & 1) if (PCI_FUNC(tp->pdev->devfn) & 1)
mac_offset = 0xcc; mac_offset = 0xcc;
if (PCI_FUNC(tp->pdev->devfn) > 1) if (PCI_FUNC(tp->pdev->devfn) > 1)
...@@ -14760,8 +14753,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, ...@@ -14760,8 +14753,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
} }
if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
dev->netdev_ops = &tg3_netdev_ops; dev->netdev_ops = &tg3_netdev_ops;
else else
dev->netdev_ops = &tg3_netdev_ops_dma_bug; dev->netdev_ops = &tg3_netdev_ops_dma_bug;
......
...@@ -2917,6 +2917,7 @@ struct tg3 { ...@@ -2917,6 +2917,7 @@ struct tg3 {
#define TG3_FLG3_L1PLLPD_EN 0x00800000 #define TG3_FLG3_L1PLLPD_EN 0x00800000
#define TG3_FLG3_57765_PLUS 0x01000000 #define TG3_FLG3_57765_PLUS 0x01000000
#define TG3_FLG3_APE_HAS_NCSI 0x02000000 #define TG3_FLG3_APE_HAS_NCSI 0x02000000
#define TG3_FLG3_5717_PLUS 0x04000000
struct timer_list timer; struct timer_list timer;
u16 timer_counter; u16 timer_counter;
......
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