Commit 0bf0e8ae authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown

ASoC: davinci-mcasp: Simplify and clean up the AFIFO configuration code

We can have more linear code flow by using variables in
mcasp_common_hw_param() related to the AFIFO configuration.
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent f5b02b4a
...@@ -37,6 +37,8 @@ ...@@ -37,6 +37,8 @@
#include "davinci-pcm.h" #include "davinci-pcm.h"
#include "davinci-mcasp.h" #include "davinci-mcasp.h"
#define MCASP_MAX_AFIFO_DEPTH 64
struct davinci_mcasp_context { struct davinci_mcasp_context {
u32 txfmtctl; u32 txfmtctl;
u32 rxfmtctl; u32 rxfmtctl;
...@@ -469,9 +471,9 @@ static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, ...@@ -469,9 +471,9 @@ static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
int i; int i;
u8 tx_ser = 0; u8 tx_ser = 0;
u8 rx_ser = 0; u8 rx_ser = 0;
u8 ser;
u8 slots = mcasp->tdm_slots; u8 slots = mcasp->tdm_slots;
u8 max_active_serializers = (channels + slots - 1) / slots; u8 max_active_serializers = (channels + slots - 1) / slots;
u8 active_serializers, numevt;
u32 reg; u32 reg;
/* Default configuration */ /* Default configuration */
if (mcasp->version != MCASP_VERSION_4) if (mcasp->version != MCASP_VERSION_4)
...@@ -505,36 +507,34 @@ static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, ...@@ -505,36 +507,34 @@ static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
} }
} }
if (stream == SNDRV_PCM_STREAM_PLAYBACK) if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
ser = tx_ser; active_serializers = tx_ser;
else numevt = mcasp->txnumevt;
ser = rx_ser; reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
} else {
active_serializers = rx_ser;
numevt = mcasp->rxnumevt;
reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
}
if (ser < max_active_serializers) { if (active_serializers < max_active_serializers) {
dev_warn(mcasp->dev, "stream has more channels (%d) than are " dev_warn(mcasp->dev, "stream has more channels (%d) than are "
"enabled in mcasp (%d)\n", channels, ser * slots); "enabled in mcasp (%d)\n", channels,
active_serializers * slots);
return -EINVAL; return -EINVAL;
} }
if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) { /* AFIFO is not in use */
if (mcasp->txnumevt * tx_ser > 64) if (!numevt)
mcasp->txnumevt = 1; return 0;
reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
NUMEVT_MASK);
}
if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { if (numevt * active_serializers > MCASP_MAX_AFIFO_DEPTH)
if (mcasp->rxnumevt * rx_ser > 64) numevt = active_serializers;
mcasp->rxnumevt = 1;
reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; /* Configure the AFIFO */
mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK); numevt *= active_serializers;
mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8), mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
NUMEVT_MASK); mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
}
return 0; return 0;
} }
......
...@@ -283,6 +283,7 @@ ...@@ -283,6 +283,7 @@
*/ */
#define FIFO_ENABLE BIT(16) #define FIFO_ENABLE BIT(16)
#define NUMEVT_MASK (0xFF << 8) #define NUMEVT_MASK (0xFF << 8)
#define NUMEVT(x) (((x) & 0xFF) << 8)
#define NUMDMA_MASK (0xFF) #define NUMDMA_MASK (0xFF)
#endif /* DAVINCI_MCASP_H */ #endif /* DAVINCI_MCASP_H */
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