Commit 0d9c7789 authored by Chris Wilson's avatar Chris Wilson Committed by Eric Anholt

drm/i915: Install a fence register for fbc on g4x

To enable framebuffer compression on a g4x, we not only need the buffer
to tiled (X only), we also need to hold a fence register for the buffer.
Currently we only install a fence register for pre-i965s when setting up
the scanout buffer. Rather than adding some convoluted logic to
g4x_enable_fbc() to acquire a fence register, and perhaps to
g4x_disable_fbc() to release it again, we can extend the acquisition
during setup to all chipsets.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 0eb96d6e
......@@ -1260,9 +1260,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
return ret;
}
/* Pre-i965 needs to install a fence for tiled scan-out */
if (!IS_I965G(dev) &&
obj_priv->fence_reg == I915_FENCE_REG_NONE &&
/* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
* whereas 965+ only requires a fence if using framebuffer compression.
* For simplicity, we always install a fence as the cost is not that onerous.
*/
if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
obj_priv->tiling_mode != I915_TILING_NONE) {
ret = i915_gem_object_get_fence_reg(obj);
if (ret != 0) {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment