media: aspeed: refine hsync/vsync polarity setting logic

To prevent inaccurate detections of resolution, this commit enables
clearing of hsync/vsync polarity bits based on probed sync state.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>

drivers/media/platform/aspeed-video.c

@@ -614,7 +614,7 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
 	int i;
 	int hsync_counter = 0;
 	int vsync_counter = 0;
-	u32 sts;
+	u32 sts, ctrl;
 
 	for (i = 0; i < NUM_POLARITY_CHECKS; ++i) {
 		sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS);
@@ -629,30 +629,29 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
 			hsync_counter++;
 	}
 
-	if (hsync_counter < 0 || vsync_counter < 0) {
-		u32 ctrl = 0;
+	ctrl = aspeed_video_read(video, VE_CTRL);
 
 	if (hsync_counter < 0) {
-			ctrl = VE_CTRL_HSYNC_POL;
+		ctrl |= VE_CTRL_HSYNC_POL;
 		video->detected_timings.polarities &=
 			~V4L2_DV_HSYNC_POS_POL;
 	} else {
+		ctrl &= ~VE_CTRL_HSYNC_POL;
 		video->detected_timings.polarities |=
 			V4L2_DV_HSYNC_POS_POL;
 	}
 
 	if (vsync_counter < 0) {
-			ctrl = VE_CTRL_VSYNC_POL;
+		ctrl |= VE_CTRL_VSYNC_POL;
 		video->detected_timings.polarities &=
 			~V4L2_DV_VSYNC_POS_POL;
 	} else {
+		ctrl &= ~VE_CTRL_VSYNC_POL;
 		video->detected_timings.polarities |=
 			V4L2_DV_VSYNC_POS_POL;
 	}
 
-		if (ctrl)
-			aspeed_video_update(video, VE_CTRL, 0, ctrl);
-	}
+	aspeed_video_write(video, VE_CTRL, ctrl);
 }
 
 static bool aspeed_video_alloc_buf(struct aspeed_video *video,