Commit 0f315716 authored by Torin Cooper-Bennun's avatar Torin Cooper-Bennun Committed by Marc Kleine-Budde

can: m_can: make TXESC, RXESC config more explicit

Introduce masks for the three RXESC fields (RBDS, F1DS, F0DS) and the
one TXESC field (TBDS). Update m_can_chip_config() to explicitly set all
four fields to the 64-byte option (0x7) (and these defs are renamed to
be more concise).

This is an improvement in maintainability, and also makes it easier to
implement more flexible configuration of the M_CAN buffers in the
future.

Link: https://lore.kernel.org/r/20210504125123.500553-4-torin@maxiluxsystems.comSigned-off-by: default avatarTorin Cooper-Bennun <torin@maxiluxsystems.com>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 38395f30
...@@ -235,8 +235,10 @@ enum m_can_reg { ...@@ -235,8 +235,10 @@ enum m_can_reg {
#define RXFS_FFL_MASK GENMASK(6, 0) #define RXFS_FFL_MASK GENMASK(6, 0)
/* Rx Buffer / FIFO Element Size Configuration (RXESC) */ /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
#define M_CAN_RXESC_8BYTES 0x0 #define RXESC_RBDS_MASK GENMASK(10, 8)
#define M_CAN_RXESC_64BYTES 0x777 #define RXESC_F1DS_MASK GENMASK(6, 4)
#define RXESC_F0DS_MASK GENMASK(2, 0)
#define RXESC_64B 0x7
/* Tx Buffer Configuration (TXBC) */ /* Tx Buffer Configuration (TXBC) */
#define TXBC_TFQS_MASK GENMASK(29, 24) #define TXBC_TFQS_MASK GENMASK(29, 24)
...@@ -249,8 +251,8 @@ enum m_can_reg { ...@@ -249,8 +251,8 @@ enum m_can_reg {
#define TXFQS_TFFL_MASK GENMASK(5, 0) #define TXFQS_TFFL_MASK GENMASK(5, 0)
/* Tx Buffer Element Size Configuration(TXESC) */ /* Tx Buffer Element Size Configuration(TXESC) */
#define TXESC_TBDS_8BYTES 0x0 #define TXESC_TBDS_MASK GENMASK(2, 0)
#define TXESC_TBDS_64BYTES 0x7 #define TXESC_TBDS_64B 0x7
/* Tx Event FIFO Configuration (TXEFC) */ /* Tx Event FIFO Configuration (TXEFC) */
#define TXEFC_EFS_MASK GENMASK(21, 16) #define TXEFC_EFS_MASK GENMASK(21, 16)
...@@ -1191,7 +1193,10 @@ static void m_can_chip_config(struct net_device *dev) ...@@ -1191,7 +1193,10 @@ static void m_can_chip_config(struct net_device *dev)
m_can_config_endisable(cdev, true); m_can_config_endisable(cdev, true);
/* RX Buffer/FIFO Element Size 64 bytes data field */ /* RX Buffer/FIFO Element Size 64 bytes data field */
m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES); m_can_write(cdev, M_CAN_RXESC,
FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
/* Accept Non-matching Frames Into FIFO 0 */ /* Accept Non-matching Frames Into FIFO 0 */
m_can_write(cdev, M_CAN_GFC, 0x0); m_can_write(cdev, M_CAN_GFC, 0x0);
...@@ -1209,7 +1214,8 @@ static void m_can_chip_config(struct net_device *dev) ...@@ -1209,7 +1214,8 @@ static void m_can_chip_config(struct net_device *dev)
} }
/* support 64 bytes payload */ /* support 64 bytes payload */
m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES); m_can_write(cdev, M_CAN_TXESC,
FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
/* TX Event FIFO */ /* TX Event FIFO */
if (cdev->version == 30) { if (cdev->version == 30) {
......
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