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Commit 0fa821d8 authored by Linus Torvalds's avatar Linus Torvalds
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Merge with dri CVS

parent add8bcb8
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Showing with 1950 additions and 1512 deletions
drivers/char/drm/drm.h
View file @ 0fa821d8
......@@ -38,10 +38,27 @@
#if defined(__linux__)
#include <linux/config.h>
#include <asm/ioctl.h> /* For _IO* macros */
#define DRM_IOCTL_NR(n) _IOC_NR(n)
#elif defined(__FreeBSD__)
#define DRM_IOCTL_NR(n) _IOC_NR(n)
#define DRM_IOC_VOID _IOC_NONE
#define DRM_IOC_READ _IOC_READ
#define DRM_IOC_WRITE _IOC_WRITE
#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
#elif defined(__FreeBSD__) || defined(__NetBSD__)
#if defined(__FreeBSD__) && defined(XFree86Server)
/* Prevent name collision when including sys/ioccom.h */
#undef ioctl
#include <sys/ioccom.h>
#define DRM_IOCTL_NR(n) ((n) & 0xff)
#define ioctl(a,b,c) xf86ioctl(a,b,c)
#else
#include <sys/ioccom.h>
#endif /* __FreeBSD__ && xf86ioctl */
#define DRM_IOCTL_NR(n) ((n) & 0xff)
#define DRM_IOC_VOID IOC_VOID
#define DRM_IOC_READ IOC_OUT
#define DRM_IOC_WRITE IOC_IN
#define DRM_IOC_READWRITE IOC_INOUT
#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
#endif
#define XFREE86_VERSION(major,minor,patch,snap) \
......@@ -367,10 +384,9 @@ typedef struct drm_scatter_gather {
#define DRM_IOCTL_BASE 'd'
#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
......
drivers/char/drm/drmP.h
View file @ 0fa821d8
......@@ -71,6 +71,8 @@
#include <asm/pgalloc.h>
#include "drm.h"
#include "drm_os_linux.h"
/* DRM template customization defaults
*/
#ifndef __HAVE_AGP
......@@ -101,7 +103,7 @@
#define __REALLY_HAVE_AGP (__HAVE_AGP && (defined(CONFIG_AGP) || \
defined(CONFIG_AGP_MODULE)))
#define __REALLY_HAVE_MTRR (__HAVE_MTRR && defined(CONFIG_MTRR))
#define __REALLY_HAVE_SG (__HAVE_SG)
/* Begin the DRM...
*/
......
drivers/char/drm/drm_drv.h
View file @ 0fa821d8
......@@ -127,6 +127,22 @@ static struct file_operations DRM(fops) = { \
}
#endif
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* Use an additional macro to avoid preprocessor troubles */
#define DRM_OPTIONS_FUNC DRM(options)
static int __init DRM(options)( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", DRM_OPTIONS_FUNC );
#undef DRM_OPTIONS_FUNC
#endif
/*
* The default number of instances (minor numbers) to initialize.
......
drivers/char/drm/drm_os_linux.h 0 → 100644
View file @ 0fa821d8
#define __NO_VERSION__
#include <linux/interrupt.h> /* For task queue support */
#include <linux/delay.h>
#define DRM_IOCTL_ARGS struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data
#define DRM_ERR(d) -(d)
#define DRM_CURRENTPID current->pid
#define DRM_UDELAY(d) udelay(d)
#define DRM_READ8(addr) readb(addr)
#define DRM_READ32(addr) readl(addr)
#define DRM_WRITE8(addr, val) writeb(val, addr)
#define DRM_WRITE32(addr, val) writel(val, addr)
#define DRM_READMEMORYBARRIER() mb()
#define DRM_WRITEMEMORYBARRIER() wmb()
#define DRM_DEVICE drm_file_t *priv = filp->private_data; \
drm_device_t *dev = priv->dev
/* For data going from/to the kernel through the ioctl argument */
#define DRM_COPY_FROM_USER_IOCTL(arg1, arg2, arg3) \
if ( copy_from_user(&arg1, arg2, arg3) ) \
return -EFAULT
#define DRM_COPY_TO_USER_IOCTL(arg1, arg2, arg3) \
if ( copy_to_user(arg1, &arg2, arg3) ) \
return -EFAULT
/* Other copying of data from/to kernel space */
#define DRM_COPY_FROM_USER(arg1, arg2, arg3) \
copy_from_user(arg1, arg2, arg3)
#define DRM_COPY_TO_USER(arg1, arg2, arg3) \
copy_to_user(arg1, arg2, arg3)
/* Macros for copyfrom user, but checking readability only once */
#define DRM_VERIFYAREA_READ( uaddr, size ) \
verify_area( VERIFY_READ, uaddr, size )
#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \
__copy_from_user(arg1, arg2, arg3)
#define DRM_GET_USER_UNCHECKED(val, uaddr) \
__get_user(val, uaddr)
/* malloc/free without the overhead of DRM(alloc) */
#define DRM_MALLOC(x) kmalloc(x, GFP_KERNEL)
#define DRM_FREE(x) kfree(x)
#define DRM_GETSAREA() \
do { \
struct list_head *list; \
list_for_each( list, &dev->maplist->head ) { \
drm_map_list_t *entry = (drm_map_list_t *)list; \
if ( entry->map && \
entry->map->type == _DRM_SHM && \
(entry->map->flags & _DRM_CONTAINS_LOCK) ) { \
dev_priv->sarea = entry->map; \
break; \
} \
} \
} while (0)
drivers/char/drm/gamma.h
View file @ 0fa821d8
......@@ -38,6 +38,31 @@
*/
#define __HAVE_MTRR 1
#define DRIVER_AUTHOR "VA Linux Systems Inc."
#define DRIVER_NAME "gamma"
#define DRIVER_DESC "3DLabs gamma"
#define DRIVER_DATE "20010624"
#define DRIVER_MAJOR 2
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { gamma_dma, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_INIT)] = { gamma_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_COPY)] = { gamma_dma_copy, 1, 1 }
#define IOCTL_TABLE_NAME DRM(ioctls)
#define IOCTL_FUNC_NAME DRM(ioctl)
#define __HAVE_COUNTERS 5
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_DMA
#define __HAVE_COUNTER8 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER9 _DRM_STAT_SPECIAL
#define __HAVE_COUNTER10 _DRM_STAT_MISSED
/* DMA customization:
*/
#define __HAVE_DMA 1
......
drivers/char/drm/gamma_drv.c
View file @ 0fa821d8
......@@ -36,32 +36,6 @@
#include "gamma_drm.h"
#include "gamma_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."
#define DRIVER_NAME "gamma"
#define DRIVER_DESC "3DLabs gamma"
#define DRIVER_DATE "20010624"
#define DRIVER_MAJOR 2
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { gamma_dma, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_INIT)] = { gamma_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_COPY)] = { gamma_dma_copy, 1, 1 }
#define IOCTL_TABLE_NAME DRM(ioctls)
#define IOCTL_FUNC_NAME DRM(ioctl)
#define __HAVE_COUNTERS 5
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_DMA
#define __HAVE_COUNTER8 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER9 _DRM_STAT_SPECIAL
#define __HAVE_COUNTER10 _DRM_STAT_MISSED
#include "drm_auth.h"
#include "drm_agpsupport.h"
#include "drm_bufs.h"
......@@ -70,25 +44,6 @@
#include "drm_drawable.h"
#include "drm_drv.h"
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* JH- We have to hand expand the string ourselves because of the cpp. If
* anyone can think of a way that we can fit into the __setup macro without
* changing it, then please send the solution my way.
*/
static int __init gamma_options( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", gamma_options );
#endif
#include "drm_fops.h"
#include "drm_init.h"
#include "drm_ioctl.h"
......
drivers/char/drm/i810.h
View file @ 0fa821d8
......@@ -41,6 +41,47 @@
#define __HAVE_MTRR 1
#define __HAVE_CTX_BITMAP 1
#define DRIVER_AUTHOR "VA Linux Systems Inc."
#define DRIVER_NAME "i810"
#define DRIVER_DESC "Intel i810"
#define DRIVER_DATE "20020211"
/* Interface history
*
* 1.1 - XFree86 4.1
* 1.2 - XvMC interfaces
* - XFree86 4.2
* 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
* - Remove requirement for interrupt (leave stubs again)
*/
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 2
#define DRIVER_PATCHLEVEL 1
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)] = { i810_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)] = { i810_clear_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)] = { i810_copybuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0INFO)] = { i810_ov0_info, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_FSTATUS)] = { i810_fstatus, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_MC)] = { i810_dma_mc, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_RSTATUS)] = { i810_rstatus, 1, 0 }
#define __HAVE_COUNTERS 4
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
#define __HAVE_COUNTER9 _DRM_STAT_DMA
/* Driver customization:
*/
#define __HAVE_RELEASE 1
......
drivers/char/drm/i810_drv.c
View file @ 0fa821d8
......@@ -37,48 +37,6 @@
#include "i810_drm.h"
#include "i810_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."
#define DRIVER_NAME "i810"
#define DRIVER_DESC "Intel i810"
#define DRIVER_DATE "20020211"
/* Interface history
*
* 1.1 - XFree86 4.1
* 1.2 - XvMC interfaces
* - XFree86 4.2
* 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
* - Remove requirement for interrupt (leave stubs again)
*/
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 2
#define DRIVER_PATCHLEVEL 1
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)] = { i810_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)] = { i810_clear_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)] = { i810_copybuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0INFO)] = { i810_ov0_info, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_FSTATUS)] = { i810_fstatus, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_MC)] = { i810_dma_mc, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I810_RSTATUS)] = { i810_rstatus, 1, 0 }
#define __HAVE_COUNTERS 4
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
#define __HAVE_COUNTER9 _DRM_STAT_DMA
#include "drm_agpsupport.h"
#include "drm_auth.h"
#include "drm_bufs.h"
......@@ -87,25 +45,6 @@
#include "drm_drawable.h"
#include "drm_drv.h"
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* JH- We have to hand expand the string ourselves because of the cpp. If
* anyone can think of a way that we can fit into the __setup macro without
* changing it, then please send the solution my way.
*/
static int __init i810_options( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", i810_options );
#endif
#include "drm_fops.h"
#include "drm_init.h"
#include "drm_ioctl.h"
......
drivers/char/drm/i830.h
View file @ 0fa821d8
......@@ -41,6 +41,33 @@
#define __HAVE_MTRR 1
#define __HAVE_CTX_BITMAP 1
#define DRIVER_AUTHOR "VA Linux Systems Inc."
#define DRIVER_NAME "i830"
#define DRIVER_DESC "Intel 830M"
#define DRIVER_DATE "20011004"
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 2
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_I830_INIT)] = { i830_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_VERTEX)] = { i830_dma_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_CLEAR)] = { i830_clear_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_FLUSH)] = { i830_flush_ioctl, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_GETAGE)] = { i830_getage, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_GETBUF)] = { i830_getbuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_SWAP)] = { i830_swap_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_COPY)] = { i830_copybuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_DOCOPY)] = { i830_docopy, 1, 0 },
#define __HAVE_COUNTERS 4
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
#define __HAVE_COUNTER9 _DRM_STAT_DMA
/* Driver customization:
*/
#define __HAVE_RELEASE 1
......
drivers/char/drm/i830_drv.c
View file @ 0fa821d8
......@@ -38,34 +38,6 @@
#include "i830_drm.h"
#include "i830_drv.h"
#define DRIVER_AUTHOR "VA Linux Systems Inc."
#define DRIVER_NAME "i830"
#define DRIVER_DESC "Intel 830M"
#define DRIVER_DATE "20011004"
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 2
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_I830_INIT)] = { i830_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_VERTEX)] = { i830_dma_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_CLEAR)] = { i830_clear_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_FLUSH)] = { i830_flush_ioctl, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_GETAGE)] = { i830_getage, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_GETBUF)] = { i830_getbuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_SWAP)] = { i830_swap_bufs, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_COPY)] = { i830_copybuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_I830_DOCOPY)] = { i830_docopy, 1, 0 },
#define __HAVE_COUNTERS 4
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
#define __HAVE_COUNTER9 _DRM_STAT_DMA
#include "drm_agpsupport.h"
#include "drm_auth.h"
#include "drm_bufs.h"
......@@ -74,25 +46,6 @@
#include "drm_drawable.h"
#include "drm_drv.h"
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* JH- We have to hand expand the string ourselves because of the cpp. If
* anyone can think of a way that we can fit into the __setup macro without
* changing it, then please send the solution my way.
*/
static int __init i830_options( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", i830_options );
#endif
#include "drm_fops.h"
#include "drm_init.h"
#include "drm_ioctl.h"
......
drivers/char/drm/mga.h
View file @ 0fa821d8
......@@ -41,6 +41,33 @@
#define __HAVE_MTRR 1
#define __HAVE_CTX_BITMAP 1
#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
#define DRIVER_NAME "mga"
#define DRIVER_DESC "Matrox G200/G400"
#define DRIVER_DATE "20010321"
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 2
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma_buffers, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)] = { mga_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)] = { mga_dma_flush, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_RESET)] = { mga_dma_reset, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_dma_swap, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_dma_clear, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)] = { mga_dma_blit, 1, 0 },
#define __HAVE_COUNTERS 3
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
/* Driver customization:
*/
#define DRIVER_PRETAKEDOWN() do { \
......
drivers/char/drm/mga_dma.c
View file @ 0fa821d8
......@@ -33,16 +33,12 @@
* Gareth Hughes <gareth@valinux.com>
*/
#define __NO_VERSION__
#include "mga.h"
#include "drmP.h"
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
#include <linux/interrupt.h> /* For task queue support */
#include <linux/delay.h>
#define MGA_DEFAULT_USEC_TIMEOUT 10000
#define MGA_FREELIST_DEBUG 0
......@@ -55,7 +51,7 @@ int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
{
u32 status = 0;
int i;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
......@@ -63,32 +59,32 @@ int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
MGA_WRITE8( MGA_CRTC_INDEX, 0 );
return 0;
}
udelay( 1 );
DRM_UDELAY( 1 );
}
#if MGA_DMA_DEBUG
DRM_ERROR( "failed!\n" );
DRM_INFO( " status=0x%08x\n", status );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
int mga_do_dma_idle( drm_mga_private_t *dev_priv )
{
u32 status = 0;
int i;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK;
if ( status == MGA_ENDPRDMASTS ) return 0;
udelay( 1 );
DRM_UDELAY( 1 );
}
#if MGA_DMA_DEBUG
DRM_ERROR( "failed! status=0x%08x\n", status );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
int mga_do_dma_reset( drm_mga_private_t *dev_priv )
......@@ -96,7 +92,7 @@ int mga_do_dma_reset( drm_mga_private_t *dev_priv )
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_primary_buffer_t *primary = &dev_priv->prim;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
/* The primary DMA stream should look like new right about now.
*/
......@@ -117,13 +113,13 @@ int mga_do_dma_reset( drm_mga_private_t *dev_priv )
int mga_do_engine_reset( drm_mga_private_t *dev_priv )
{
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
/* Okay, so we've completely screwed up and locked the engine.
* How about we clean up after ourselves?
*/
MGA_WRITE( MGA_RST, MGA_SOFTRESET );
udelay( 15 ); /* Wait at least 10 usecs */
DRM_UDELAY( 15 ); /* Wait at least 10 usecs */
MGA_WRITE( MGA_RST, 0 );
/* Initialize the registers that get clobbered by the soft
......@@ -162,7 +158,7 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
drm_mga_primary_buffer_t *primary = &dev_priv->prim;
u32 head, tail;
DMA_LOCALS;
DRM_DEBUG( "%s:\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
if ( primary->tail == primary->last_flush ) {
DRM_DEBUG( " bailing out...\n" );
......@@ -201,7 +197,7 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
mga_flush_write_combine();
MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
DRM_DEBUG( "done.\n" );
}
void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
......@@ -209,7 +205,7 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
drm_mga_primary_buffer_t *primary = &dev_priv->prim;
u32 head, tail;
DMA_LOCALS;
DRM_DEBUG( "%s:\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
BEGIN_DMA_WRAP();
......@@ -244,7 +240,7 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
set_bit( 0, &primary->wrapped );
DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
DRM_DEBUG( "done.\n" );
}
void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
......@@ -252,7 +248,7 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
drm_mga_primary_buffer_t *primary = &dev_priv->prim;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
u32 head = dev_priv->primary->offset;
DRM_DEBUG( "%s:\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
sarea_priv->last_wrap++;
DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap );
......@@ -261,7 +257,7 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
clear_bit( 0, &primary->wrapped );
DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
DRM_DEBUG( "done.\n" );
}
......@@ -301,13 +297,12 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
drm_mga_buf_priv_t *buf_priv;
drm_mga_freelist_t *entry;
int i;
DRM_DEBUG( "%s: count=%d\n",
__FUNCTION__, dma->buf_count );
DRM_DEBUG( "count=%d\n", dma->buf_count );
dev_priv->head = DRM(alloc)( sizeof(drm_mga_freelist_t),
DRM_MEM_DRIVER );
if ( dev_priv->head == NULL )
return -ENOMEM;
return DRM_ERR(ENOMEM);
memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) );
SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 );
......@@ -319,7 +314,7 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
entry = DRM(alloc)( sizeof(drm_mga_freelist_t),
DRM_MEM_DRIVER );
if ( entry == NULL )
return -ENOMEM;
return DRM_ERR(ENOMEM);
memset( entry, 0, sizeof(drm_mga_freelist_t) );
......@@ -348,7 +343,7 @@ static void mga_freelist_cleanup( drm_device_t *dev )
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_freelist_t *entry;
drm_mga_freelist_t *next;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
entry = dev_priv->head;
while ( entry ) {
......@@ -386,7 +381,7 @@ static drm_buf_t *mga_freelist_get( drm_device_t *dev )
drm_mga_freelist_t *prev;
drm_mga_freelist_t *tail = dev_priv->tail;
u32 head, wrap;
DRM_DEBUG( "%s:\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
head = MGA_READ( MGA_PRIMADDRESS );
wrap = dev_priv->sarea_priv->last_wrap;
......@@ -418,8 +413,7 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
drm_mga_buf_priv_t *buf_priv = buf->dev_private;
drm_mga_freelist_t *head, *entry, *prev;
DRM_DEBUG( "%s: age=0x%06lx wrap=%d\n",
__FUNCTION__,
DRM_DEBUG( "age=0x%06lx wrap=%d\n",
buf_priv->list_entry->age.head -
dev_priv->primary->offset,
buf_priv->list_entry->age.wrap );
......@@ -452,13 +446,12 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
{
drm_mga_private_t *dev_priv;
struct list_head *list;
int ret;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
dev_priv = DRM(alloc)( sizeof(drm_mga_private_t), DRM_MEM_DRIVER );
if ( !dev_priv )
return -ENOMEM;
return DRM_ERR(ENOMEM);
memset( dev_priv, 0, sizeof(drm_mga_private_t) );
......@@ -488,21 +481,14 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
dev_priv->texture_offset = init->texture_offset[0];
dev_priv->texture_size = init->texture_size[0];
list_for_each( list, &dev->maplist->head ) {
drm_map_list_t *entry = (drm_map_list_t *)list;
if ( entry->map &&
entry->map->type == _DRM_SHM &&
(entry->map->flags & _DRM_CONTAINS_LOCK) ) {
dev_priv->sarea = entry->map;
break;
}
}
DRM_GETSAREA();
if(!dev_priv->sarea) {
DRM_ERROR( "failed to find sarea!\n" );
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
......@@ -511,7 +497,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
if(!dev_priv->mmio) {
......@@ -519,7 +505,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->status, init->status_offset );
if(!dev_priv->status) {
......@@ -527,7 +513,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->warp, init->warp_offset );
......@@ -536,7 +522,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->primary, init->primary_offset );
if(!dev_priv->primary) {
......@@ -544,7 +530,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
if(!dev_priv->buffers) {
......@@ -552,7 +538,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
dev_priv->sarea_priv =
......@@ -570,7 +556,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
ret = mga_warp_install_microcode( dev_priv );
......@@ -620,8 +606,6 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
spin_lock_init( &dev_priv->prim.list_lock );
dev_priv->prim.status[0] = dev_priv->primary->offset;
dev_priv->prim.status[1] = 0;
......@@ -634,7 +618,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
/* Assign dev_private so we can do cleanup. */
dev->dev_private = (void *)dev_priv;
mga_do_cleanup_dma( dev );
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
/* Make dev_private visable to others. */
......@@ -644,7 +628,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
int mga_do_cleanup_dma( drm_device_t *dev )
{
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
if ( dev->dev_private ) {
drm_mga_private_t *dev_priv = dev->dev_private;
......@@ -665,15 +649,12 @@ int mga_do_cleanup_dma( drm_device_t *dev )
return 0;
}
int mga_dma_init( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_init( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_init_t init;
if ( copy_from_user( &init, (drm_mga_init_t *)arg, sizeof(init) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( init, (drm_mga_init_t *)data, sizeof(init) );
switch ( init.func ) {
case MGA_INIT_DMA:
......@@ -682,7 +663,7 @@ int mga_dma_init( struct inode *inode, struct file *filp,
return mga_do_cleanup_dma( dev );
}
return -EINVAL;
return DRM_ERR(EINVAL);
}
......@@ -690,21 +671,17 @@ int mga_dma_init( struct inode *inode, struct file *filp,
* Primary DMA stream management
*/
int mga_dma_flush( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_flush( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
drm_lock_t lock;
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &lock, (drm_lock_t *)arg, sizeof(lock) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t *)data, sizeof(lock) );
DRM_DEBUG( "%s: %s%s%s\n",
__FUNCTION__,
DRM_DEBUG( "%s%s%s\n",
(lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
(lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
(lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" );
......@@ -719,7 +696,7 @@ int mga_dma_flush( struct inode *inode, struct file *filp,
#if MGA_DMA_DEBUG
int ret = mga_do_wait_for_idle( dev_priv );
if ( ret < 0 )
DRM_INFO( __FUNCTION__": -EBUSY\n" );
DRM_INFO( "%s: -EBUSY\n", __func__ );
return ret;
#else
return mga_do_wait_for_idle( dev_priv );
......@@ -729,11 +706,9 @@ int mga_dma_flush( struct inode *inode, struct file *filp,
}
}
int mga_dma_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_reset( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
LOCK_TEST_WITH_RETURN( dev );
......@@ -753,27 +728,25 @@ static int mga_dma_get_buffers( drm_device_t *dev, drm_dma_t *d )
for ( i = d->granted_count ; i < d->request_count ; i++ ) {
buf = mga_freelist_get( dev );
if ( !buf ) return -EAGAIN;
if ( !buf ) return DRM_ERR(EAGAIN);
buf->pid = current->pid;
buf->pid = DRM_CURRENTPID;
if ( copy_to_user( &d->request_indices[i],
if ( DRM_COPY_TO_USER( &d->request_indices[i],
&buf->idx, sizeof(buf->idx) ) )
return -EFAULT;
if ( copy_to_user( &d->request_sizes[i],
return DRM_ERR(EFAULT);
if ( DRM_COPY_TO_USER( &d->request_sizes[i],
&buf->total, sizeof(buf->total) ) )
return -EFAULT;
return DRM_ERR(EFAULT);
d->granted_count++;
}
return 0;
}
int mga_dma_buffers( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_buffers( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_device_dma_t *dma = dev->dma;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
drm_dma_t d;
......@@ -781,23 +754,22 @@ int mga_dma_buffers( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
/* Please don't send us buffers.
*/
if ( d.send_count != 0 ) {
DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
current->pid, d.send_count );
return -EINVAL;
DRM_CURRENTPID, d.send_count );
return DRM_ERR(EINVAL);
}
/* We'll send you buffers.
*/
if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
current->pid, d.request_count, dma->buf_count );
return -EINVAL;
DRM_CURRENTPID, d.request_count, dma->buf_count );
return DRM_ERR(EINVAL);
}
WRAP_TEST_WITH_RETURN( dev_priv );
......@@ -808,8 +780,7 @@ int mga_dma_buffers( struct inode *inode, struct file *filp,
ret = mga_dma_get_buffers( dev, &d );
}
if ( copy_to_user( (drm_dma_t *)arg, &d, sizeof(d) ) )
return -EFAULT;
DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
return ret;
}
drivers/char/drm/mga_drv.c
View file @ 0fa821d8
......@@ -35,36 +35,6 @@
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
#define DRIVER_NAME "mga"
#define DRIVER_DESC "Matrox G200/G400"
#define DRIVER_DATE "20010321"
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 2
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma_buffers, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)] = { mga_dma_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)] = { mga_dma_flush, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_RESET)] = { mga_dma_reset, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_dma_swap, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_dma_clear, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)] = { mga_dma_blit, 1, 0 },
#define __HAVE_COUNTERS 3
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
#include "drm_agpsupport.h"
#include "drm_auth.h"
#include "drm_bufs.h"
......@@ -72,27 +42,6 @@
#include "drm_dma.h"
#include "drm_drawable.h"
#include "drm_drv.h"
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* JH- We have to hand expand the string ourselves because of the cpp. If
* anyone can think of a way that we can fit into the __setup macro without
* changing it, then please send the solution my way.
*/
static int __init mga_options( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", mga_options );
#endif
#include "drm_fops.h"
#include "drm_init.h"
#include "drm_ioctl.h"
......
drivers/char/drm/mga_drv.h
View file @ 0fa821d8
......@@ -38,7 +38,7 @@ typedef struct drm_mga_primary_buffer {
u32 tail;
int space;
volatile long wrapped;
int wrapped;
volatile u32 *status;
......@@ -46,8 +46,6 @@ typedef struct drm_mga_primary_buffer {
u32 last_wrap;
u32 high_mark;
spinlock_t list_lock;
} drm_mga_primary_buffer_t;
typedef struct drm_mga_freelist {
......@@ -103,14 +101,10 @@ typedef struct drm_mga_private {
} drm_mga_private_t;
/* mga_dma.c */
extern int mga_dma_init( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_flush( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_buffers( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_init( DRM_IOCTL_ARGS );
extern int mga_dma_flush( DRM_IOCTL_ARGS );
extern int mga_dma_reset( DRM_IOCTL_ARGS );
extern int mga_dma_buffers( DRM_IOCTL_ARGS );
extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
......@@ -125,24 +119,18 @@ extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
/* mga_state.c */
extern int mga_dma_clear( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_swap( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_vertex( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_indices( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_iload( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_blit( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int mga_dma_clear( DRM_IOCTL_ARGS );
extern int mga_dma_swap( DRM_IOCTL_ARGS );
extern int mga_dma_vertex( DRM_IOCTL_ARGS );
extern int mga_dma_indices( DRM_IOCTL_ARGS );
extern int mga_dma_iload( DRM_IOCTL_ARGS );
extern int mga_dma_blit( DRM_IOCTL_ARGS );
/* mga_warp.c */
extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
extern int mga_warp_init( drm_mga_private_t *dev_priv );
#define mga_flush_write_combine() mb()
#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
......@@ -153,12 +141,12 @@ extern int mga_warp_init( drm_mga_private_t *dev_priv );
#ifdef __alpha__
#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
#define MGA_WRITE( reg, val ) do { wmb(); MGA_DEREF( reg ) = val; } while (0)
#define MGA_WRITE8( reg, val ) do { wmb(); MGA_DEREF8( reg ) = val; } while (0)
#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
static inline u32 _MGA_READ(u32 *addr)
{
mb();
DRM_READMEMORYBARRIER();
return *(volatile u32 *)addr;
}
......@@ -198,10 +186,10 @@ do { \
#define LOCK_TEST_WITH_RETURN( dev ) \
do { \
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
dev->lock.pid != current->pid ) { \
dev->lock.pid != DRM_CURRENTPID ) { \
DRM_ERROR( "%s called without lock held\n", \
__FUNCTION__ ); \
return -EINVAL; \
__func__ ); \
return DRM_ERR(EINVAL); \
} \
} while (0)
......@@ -213,8 +201,8 @@ do { \
} else if ( dev_priv->prim.space < \
dev_priv->prim.high_mark ) { \
if ( MGA_DMA_DEBUG ) \
DRM_INFO( __FUNCTION__": wrap...\n" ); \
return -EBUSY; \
DRM_INFO( "%s: wrap...\n", __func__ ); \
return DRM_ERR(EBUSY); \
} \
} \
} while (0)
......@@ -224,8 +212,8 @@ do { \
if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
if ( MGA_DMA_DEBUG ) \
DRM_INFO( __FUNCTION__": wrap...\n" ); \
return -EBUSY; \
DRM_INFO( "%s: wrap...\n", __func__ ); \
return DRM_ERR(EBUSY); \
} \
mga_do_dma_wrap_end( dev_priv ); \
} \
......@@ -246,7 +234,7 @@ do { \
do { \
if ( MGA_VERBOSE ) { \
DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
(n), __FUNCTION__ ); \
(n), __func__ ); \
DRM_INFO( " space=0x%x req=0x%x\n", \
dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
} \
......@@ -257,7 +245,7 @@ do { \
#define BEGIN_DMA_WRAP() \
do { \
if ( MGA_VERBOSE ) { \
DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
DRM_INFO( "BEGIN_DMA() in %s\n", __func__ ); \
DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
} \
prim = dev_priv->prim.start; \
......@@ -276,7 +264,7 @@ do { \
#define FLUSH_DMA() \
do { \
if ( 0 ) { \
DRM_INFO( __FUNCTION__ ":\n" ); \
DRM_INFO( "%s:\n", __func__ ); \
DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
dev_priv->prim.tail, \
MGA_READ( MGA_PRIMADDRESS ) - \
......@@ -634,7 +622,7 @@ do { \
/* Simple idle test.
*/
static inline int mga_is_idle( drm_mga_private_t *dev_priv )
static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
{
u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
return ( status == MGA_ENDPRDMASTS );
......
drivers/char/drm/mga_state.c
View file @ 0fa821d8
......@@ -32,7 +32,6 @@
* Gareth Hughes <gareth@valinux.com>
*/
#define __NO_VERSION__
#include "mga.h"
#include "drmP.h"
#include "drm.h"
......@@ -71,7 +70,7 @@ static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
ADVANCE_DMA();
}
static inline void mga_g200_emit_context( drm_mga_private_t *dev_priv )
static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
......@@ -97,7 +96,7 @@ static inline void mga_g200_emit_context( drm_mga_private_t *dev_priv )
ADVANCE_DMA();
}
static inline void mga_g400_emit_context( drm_mga_private_t *dev_priv )
static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
......@@ -128,7 +127,7 @@ static inline void mga_g400_emit_context( drm_mga_private_t *dev_priv )
ADVANCE_DMA();
}
static inline void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
......@@ -159,7 +158,7 @@ static inline void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
ADVANCE_DMA();
}
static inline void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
......@@ -203,7 +202,7 @@ static inline void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
ADVANCE_DMA();
}
static inline void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
......@@ -244,7 +243,7 @@ static inline void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
ADVANCE_DMA();
}
static inline void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->warp_pipe;
......@@ -274,7 +273,7 @@ static inline void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
ADVANCE_DMA();
}
static inline void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->warp_pipe;
......@@ -422,7 +421,7 @@ static int mga_verify_context( drm_mga_private_t *dev_priv )
ctx->dstorg, dev_priv->front_offset,
dev_priv->back_offset );
ctx->dstorg = 0;
return -EINVAL;
return DRM_ERR(EINVAL);
}
return 0;
......@@ -442,7 +441,7 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
tex->texorg, unit );
tex->texorg = 0;
return -EINVAL;
return DRM_ERR(EINVAL);
}
return 0;
......@@ -484,13 +483,13 @@ static int mga_verify_iload( drm_mga_private_t *dev_priv,
dstorg + length > (dev_priv->texture_offset +
dev_priv->texture_size) ) {
DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( length & MGA_ILOAD_MASK ) {
DRM_ERROR( "*** bad iload length: 0x%x\n",
length & MGA_ILOAD_MASK );
return -EINVAL;
return DRM_ERR(EINVAL);
}
return 0;
......@@ -503,7 +502,7 @@ static int mga_verify_blit( drm_mga_private_t *dev_priv,
(dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
srcorg, dstorg );
return -EINVAL;
return DRM_ERR(EINVAL);
}
return 0;
}
......@@ -523,7 +522,7 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
int nbox = sarea_priv->nbox;
int i;
DMA_LOCALS;
DRM_DEBUG( __FUNCTION__ ":\n" );
DRM_DEBUG( "\n" );
BEGIN_DMA( 1 );
......@@ -617,7 +616,7 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
int nbox = sarea_priv->nbox;
int i;
DMA_LOCALS;
DRM_DEBUG( __FUNCTION__ ":\n" );
DRM_DEBUG( "\n" );
sarea_priv->last_frame.head = dev_priv->prim.tail;
sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
......@@ -663,7 +662,7 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
FLUSH_DMA();
DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
DRM_DEBUG( "%s... done.\n", __func__ );
}
static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
......@@ -771,8 +770,7 @@ static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
u32 y2;
DMA_LOCALS;
DRM_DEBUG( "%s: buf=%d used=%d\n",
__FUNCTION__, buf->idx, buf->used );
DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used );
y2 = length / 64;
......@@ -826,7 +824,7 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
int nbox = sarea_priv->nbox;
u32 scandir = 0, i;
DMA_LOCALS;
DRM_DEBUG( __FUNCTION__ ":\n" );
DRM_DEBUG( "\n" );
BEGIN_DMA( 4 + nbox );
......@@ -883,19 +881,16 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
*
*/
int mga_dma_clear( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_clear( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_clear_t clear;
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &clear, (drm_mga_clear_t *) arg, sizeof(clear) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t *)data, sizeof(clear) );
if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
......@@ -911,11 +906,9 @@ int mga_dma_clear( struct inode *inode, struct file *filp,
return 0;
}
int mga_dma_swap( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_swap( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
......@@ -935,11 +928,9 @@ int mga_dma_swap( struct inode *inode, struct file *filp,
return 0;
}
int mga_dma_vertex( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_vertex( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
......@@ -948,12 +939,11 @@ int mga_dma_vertex( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &vertex,
(drm_mga_vertex_t *)arg,
sizeof(vertex) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( vertex,
(drm_mga_vertex_t *)data,
sizeof(vertex) );
if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL);
buf = dma->buflist[vertex.idx];
buf_priv = buf->dev_private;
......@@ -967,7 +957,7 @@ int mga_dma_vertex( struct inode *inode, struct file *filp,
buf_priv->dispatched = 0;
mga_freelist_put( dev, buf );
}
return -EINVAL;
return DRM_ERR(EINVAL);
}
WRAP_TEST_WITH_RETURN( dev_priv );
......@@ -977,11 +967,9 @@ int mga_dma_vertex( struct inode *inode, struct file *filp,
return 0;
}
int mga_dma_indices( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_indices( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
......@@ -990,12 +978,11 @@ int mga_dma_indices( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &indices,
(drm_mga_indices_t *)arg,
sizeof(indices) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( indices,
(drm_mga_indices_t *)data,
sizeof(indices) );
if(indices.idx < 0 || indices.idx > dma->buf_count) return -EINVAL;
if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL);
buf = dma->buflist[indices.idx];
buf_priv = buf->dev_private;
......@@ -1009,7 +996,7 @@ int mga_dma_indices( struct inode *inode, struct file *filp,
buf_priv->dispatched = 0;
mga_freelist_put( dev, buf );
}
return -EINVAL;
return DRM_ERR(EINVAL);
}
WRAP_TEST_WITH_RETURN( dev_priv );
......@@ -1019,38 +1006,35 @@ int mga_dma_indices( struct inode *inode, struct file *filp,
return 0;
}
int mga_dma_iload( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_iload( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_device_dma_t *dma = dev->dma;
drm_mga_private_t *dev_priv = dev->dev_private;
drm_buf_t *buf;
drm_mga_buf_priv_t *buf_priv;
drm_mga_iload_t iload;
DRM_DEBUG( __FUNCTION__ ":\n" );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &iload, (drm_mga_iload_t *)arg, sizeof(iload) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t *)data, sizeof(iload) );
#if 0
if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {
if ( MGA_DMA_DEBUG )
DRM_INFO( __FUNCTION__": -EBUSY\n" );
return -EBUSY;
DRM_INFO( "%s: -EBUSY\n", __func__ );
return DRM_ERR(EBUSY);
}
#endif
if(iload.idx < 0 || iload.idx > dma->buf_count) return -EINVAL;
if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL);
buf = dma->buflist[iload.idx];
buf_priv = buf->dev_private;
if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
mga_freelist_put( dev, buf );
return -EINVAL;
return DRM_ERR(EINVAL);
}
WRAP_TEST_WITH_RETURN( dev_priv );
......@@ -1064,26 +1048,23 @@ int mga_dma_iload( struct inode *inode, struct file *filp,
return 0;
}
int mga_dma_blit( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int mga_dma_blit( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_blit_t blit;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &blit, (drm_mga_blit_t *)arg, sizeof(blit) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t *)data, sizeof(blit) );
if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
return -EINVAL;
return DRM_ERR(EINVAL);
WRAP_TEST_WITH_RETURN( dev_priv );
......
drivers/char/drm/mga_warp.c
View file @ 0fa821d8
......@@ -107,7 +107,7 @@ static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv )
if ( size > dev_priv->warp->size ) {
DRM_ERROR( "microcode too large! (%u > %lu)\n",
size, dev_priv->warp->size );
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
memset( dev_priv->warp_pipe_phys, 0,
......@@ -144,7 +144,7 @@ static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv )
if ( size > dev_priv->warp->size ) {
DRM_ERROR( "microcode too large! (%u > %lu)\n",
size, dev_priv->warp->size );
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
memset( dev_priv->warp_pipe_phys, 0,
......@@ -170,7 +170,7 @@ int mga_warp_install_microcode( drm_mga_private_t *dev_priv )
case MGA_CARD_TYPE_G200:
return mga_warp_install_g200_microcode( dev_priv );
default:
return -EINVAL;
return DRM_ERR(EINVAL);
}
}
......@@ -195,7 +195,7 @@ int mga_warp_init( drm_mga_private_t *dev_priv )
MGA_WRITE( MGA_WVRTXSZ, 7 );
break;
default:
return -EINVAL;
return DRM_ERR(EINVAL);
}
MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
......@@ -205,7 +205,7 @@ int mga_warp_init( drm_mga_private_t *dev_priv )
if ( wmisc != WMISC_EXPECTED ) {
DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n",
wmisc, WMISC_EXPECTED );
return -EINVAL;
return DRM_ERR(EINVAL);
}
return 0;
......
drivers/char/drm/r128.h
View file @ 0fa821d8
......@@ -43,6 +43,35 @@
#define __HAVE_SG 1
#define __HAVE_PCI_DMA 1
#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
#define DRIVER_NAME "r128"
#define DRIVER_DESC "ATI Rage 128"
#define DRIVER_DATE "20010917"
#define DRIVER_MAJOR 2
#define DRIVER_MINOR 2
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { r128_cce_buffers, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_cce_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_engine_reset, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)] = { r128_cce_indices, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)] = { r128_cce_blit, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 },
/* Driver customization:
*/
#define DRIVER_PRERELEASE() do { \
......
drivers/char/drm/r128_cce.c
View file @ 0fa821d8
......@@ -28,19 +28,14 @@
* Gareth Hughes <gareth@valinux.com>
*/
#define __NO_VERSION__
#include "r128.h"
#include "drmP.h"
#include "drm.h"
#include "r128_drm.h"
#include "r128_drv.h"
#include <linux/interrupt.h> /* For task queue support */
#include <linux/delay.h>
#define R128_FIFO_DEBUG 0
/* CCE microcode (from ATI) */
static u32 r128_cce_microcode[] = {
0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
......@@ -86,6 +81,7 @@ static u32 r128_cce_microcode[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
int r128_do_wait_for_idle( drm_r128_private_t *dev_priv );
int R128_READ_PLL(drm_device_t *dev, int addr)
{
......@@ -130,13 +126,13 @@ static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
return 0;
}
udelay( 1 );
DRM_UDELAY( 1 );
}
#if R128_FIFO_DEBUG
DRM_ERROR( "%s failed!\n", __FUNCTION__ );
DRM_ERROR( "failed!\n" );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
......@@ -146,13 +142,13 @@ static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
if ( slots >= entries ) return 0;
udelay( 1 );
DRM_UDELAY( 1 );
}
#if R128_FIFO_DEBUG
DRM_ERROR( "%s failed!\n", __FUNCTION__ );
DRM_ERROR( "failed!\n" );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
......@@ -160,20 +156,20 @@ int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
int i, ret;
ret = r128_do_wait_for_fifo( dev_priv, 64 );
if ( ret < 0 ) return ret;
if ( ret ) return ret;
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
r128_do_pixcache_flush( dev_priv );
return 0;
}
udelay( 1 );
DRM_UDELAY( 1 );
}
#if R128_FIFO_DEBUG
DRM_ERROR( "%s failed!\n", __FUNCTION__ );
DRM_ERROR( "failed!\n" );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
......@@ -186,7 +182,7 @@ static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
{
int i;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
r128_do_wait_for_idle( dev_priv );
......@@ -227,14 +223,14 @@ int r128_do_cce_idle( drm_r128_private_t *dev_priv )
return r128_do_pixcache_flush( dev_priv );
}
}
udelay( 1 );
DRM_UDELAY( 1 );
}
#if R128_FIFO_DEBUG
DRM_ERROR( "failed!\n" );
r128_status( dev_priv );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
/* Start the Concurrent Command Engine.
......@@ -322,7 +318,7 @@ static void r128_cce_init_ring_buffer( drm_device_t *dev,
u32 ring_start;
u32 tmp;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
/* The manual (p. 2) says this address is in "VM space". This
* means it's an offset from the start of AGP space.
......@@ -377,13 +373,12 @@ static void r128_cce_init_ring_buffer( drm_device_t *dev,
static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
{
drm_r128_private_t *dev_priv;
struct list_head *list;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
if ( dev_priv == NULL )
return -ENOMEM;
return DRM_ERR(ENOMEM);
memset( dev_priv, 0, sizeof(drm_r128_private_t) );
......@@ -393,7 +388,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
DRM_ERROR( "PCI GART memory not allocated!\n" );
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
dev_priv->usec_timeout = init->usec_timeout;
......@@ -402,7 +397,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
DRM_DEBUG( "TIMEOUT problem!\n" );
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
dev_priv->cce_mode = init->cce_mode;
......@@ -422,7 +417,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
DRM_DEBUG( "Bad cce_mode!\n" );
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
switch ( init->cce_mode ) {
......@@ -484,20 +479,13 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
(dev_priv->span_offset >> 5));
list_for_each(list, &dev->maplist->head) {
drm_map_list_t *r_list = (drm_map_list_t *)list;
if( r_list->map &&
r_list->map->type == _DRM_SHM &&
r_list->map->flags & _DRM_CONTAINS_LOCK ) {
dev_priv->sarea = r_list->map;
break;
}
}
DRM_GETSAREA();
if(!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
......@@ -505,35 +493,35 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
DRM_ERROR("could not find framebuffer!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
if(!dev_priv->mmio) {
DRM_ERROR("could not find mmio region!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset );
if(!dev_priv->cce_ring) {
DRM_ERROR("could not find cce ring region!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
if(!dev_priv->ring_rptr) {
DRM_ERROR("could not find ring read pointer!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
if(!dev_priv->buffers) {
DRM_ERROR("could not find dma buffer region!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( !dev_priv->is_pci ) {
......@@ -543,7 +531,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
DRM_ERROR("could not find agp texture region!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -EINVAL;
return DRM_ERR(EINVAL);
}
}
......@@ -561,7 +549,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
DRM_ERROR("Could not ioremap agp regions!\n");
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
} else {
dev_priv->cce_ring->handle =
......@@ -599,16 +587,18 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
R128_WRITE( R128_LAST_DISPATCH_REG,
dev_priv->sarea_priv->last_dispatch );
#if __REALLY_HAVE_SG
if ( dev_priv->is_pci ) {
if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
&dev_priv->bus_pci_gart) ) {
DRM_ERROR( "failed to init PCI GART!\n" );
dev->dev_private = (void *)dev_priv;
r128_do_cleanup_cce( dev );
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
}
#endif
r128_cce_init_ring_buffer( dev, dev_priv );
r128_cce_load_microcode( dev_priv );
......@@ -625,16 +615,20 @@ int r128_do_cleanup_cce( drm_device_t *dev )
if ( dev->dev_private ) {
drm_r128_private_t *dev_priv = dev->dev_private;
#if __REALLY_HAVE_SG
if ( !dev_priv->is_pci ) {
#endif
DRM_IOREMAPFREE( dev_priv->cce_ring );
DRM_IOREMAPFREE( dev_priv->ring_rptr );
DRM_IOREMAPFREE( dev_priv->buffers );
#if __REALLY_HAVE_SG
} else {
if (!DRM(ati_pcigart_cleanup)( dev,
dev_priv->phys_pci_gart,
dev_priv->bus_pci_gart ))
DRM_ERROR( "failed to cleanup PCI GART!\n" );
}
#endif
DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
DRM_MEM_DRIVER );
......@@ -644,17 +638,14 @@ int r128_do_cleanup_cce( drm_device_t *dev )
return 0;
}
int r128_cce_init( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_init( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_init_t init;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
if ( copy_from_user( &init, (drm_r128_init_t *)arg, sizeof(init) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t *)data, sizeof(init) );
switch ( init.func ) {
case R128_INIT_CCE:
......@@ -663,21 +654,19 @@ int r128_cce_init( struct inode *inode, struct file *filp,
return r128_do_cleanup_cce( dev );
}
return -EINVAL;
return DRM_ERR(EINVAL);
}
int r128_cce_start( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_start( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
DRM_DEBUG( "%s while CCE running\n", __func__ );
return 0;
}
......@@ -689,20 +678,17 @@ int r128_cce_start( struct inode *inode, struct file *filp,
/* Stop the CCE. The engine must have been idled before calling this
* routine.
*/
int r128_cce_stop( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_stop( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_cce_stop_t stop;
int ret;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &stop, (drm_r128_init_t *)arg, sizeof(stop) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t *)data, sizeof(stop) );
/* Flush any pending CCE commands. This ensures any outstanding
* commands are exectuted by the engine before we turn it off.
......@@ -716,7 +702,7 @@ int r128_cce_stop( struct inode *inode, struct file *filp,
*/
if ( stop.idle ) {
ret = r128_do_cce_idle( dev_priv );
if ( ret < 0 ) return ret;
if ( ret ) return ret;
}
/* Finally, we can turn off the CCE. If the engine isn't idle,
......@@ -733,19 +719,17 @@ int r128_cce_stop( struct inode *inode, struct file *filp,
/* Just reset the CCE ring. Called as part of an X Server engine reset.
*/
int r128_cce_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_reset( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
return -EINVAL;
DRM_DEBUG( "%s called before init done\n", __func__ );
return DRM_ERR(EINVAL);
}
r128_do_cce_reset( dev_priv );
......@@ -756,13 +740,11 @@ int r128_cce_reset( struct inode *inode, struct file *filp,
return 0;
}
int r128_cce_idle( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_idle( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
......@@ -773,12 +755,10 @@ int r128_cce_idle( struct inode *inode, struct file *filp,
return r128_do_cce_idle( dev_priv );
}
int r128_engine_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_engine_reset( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEVICE;
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
......@@ -793,7 +773,7 @@ int r128_engine_reset( struct inode *inode, struct file *filp,
static int r128_do_init_pageflip( drm_device_t *dev )
{
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET );
dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
......@@ -811,7 +791,7 @@ static int r128_do_init_pageflip( drm_device_t *dev )
int r128_do_cleanup_pageflip( drm_device_t *dev )
{
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset );
R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
......@@ -822,17 +802,14 @@ int r128_do_cleanup_pageflip( drm_device_t *dev )
return 0;
}
int r128_fullscreen( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_fullscreen( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_fullscreen_t fs;
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &fs, (drm_r128_fullscreen_t *)arg, sizeof(fs) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( fs, (drm_r128_fullscreen_t *)data, sizeof(fs) );
switch ( fs.func ) {
case R128_INIT_FULLSCREEN:
......@@ -841,7 +818,7 @@ int r128_fullscreen( struct inode *inode, struct file *filp,
return r128_do_cleanup_pageflip( dev );
}
return -EINVAL;
return DRM_ERR(EINVAL);
}
......@@ -864,7 +841,7 @@ static int r128_freelist_init( drm_device_t *dev )
dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t),
DRM_MEM_DRIVER );
if ( dev_priv->head == NULL )
return -ENOMEM;
return DRM_ERR(ENOMEM);
memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
dev_priv->head->age = R128_BUFFER_USED;
......@@ -875,7 +852,7 @@ static int r128_freelist_init( drm_device_t *dev )
entry = DRM(alloc)( sizeof(drm_r128_freelist_t),
DRM_MEM_DRIVER );
if ( !entry ) return -ENOMEM;
if ( !entry ) return DRM_ERR(ENOMEM);
entry->age = R128_BUFFER_FREE;
entry->buf = buf;
......@@ -930,7 +907,7 @@ drm_buf_t *r128_freelist_get( drm_device_t *dev )
return buf;
}
}
udelay( 1 );
DRM_UDELAY( 1 );
}
DRM_ERROR( "returning NULL!\n" );
......@@ -963,12 +940,12 @@ int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
r128_update_ring_snapshot( ring );
if ( ring->space >= n )
return 0;
udelay( 1 );
DRM_UDELAY( 1 );
}
/* FIXME: This is being ignored... */
DRM_ERROR( "failed!\n" );
return -EBUSY;
return DRM_ERR(EBUSY);
}
static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d )
......@@ -978,50 +955,47 @@ static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d )
for ( i = d->granted_count ; i < d->request_count ; i++ ) {
buf = r128_freelist_get( dev );
if ( !buf ) return -EAGAIN;
if ( !buf ) return DRM_ERR(EAGAIN);
buf->pid = current->pid;
buf->pid = DRM_CURRENTPID;
if ( copy_to_user( &d->request_indices[i], &buf->idx,
if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
sizeof(buf->idx) ) )
return -EFAULT;
if ( copy_to_user( &d->request_sizes[i], &buf->total,
return DRM_ERR(EFAULT);
if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
sizeof(buf->total) ) )
return -EFAULT;
return DRM_ERR(EFAULT);
d->granted_count++;
}
return 0;
}
int r128_cce_buffers( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_buffers( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_device_dma_t *dma = dev->dma;
int ret = 0;
drm_dma_t d;
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *) data, sizeof(d) );
/* Please don't send us buffers.
*/
if ( d.send_count != 0 ) {
DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
current->pid, d.send_count );
return -EINVAL;
DRM_CURRENTPID, d.send_count );
return DRM_ERR(EINVAL);
}
/* We'll send you buffers.
*/
if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
current->pid, d.request_count, dma->buf_count );
return -EINVAL;
DRM_CURRENTPID, d.request_count, dma->buf_count );
return DRM_ERR(EINVAL);
}
d.granted_count = 0;
......@@ -1030,8 +1004,7 @@ int r128_cce_buffers( struct inode *inode, struct file *filp,
ret = r128_cce_get_buffers( dev, &d );
}
if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) )
return -EFAULT;
DRM_COPY_TO_USER_IOCTL((drm_dma_t *) data, d, sizeof(d) );
return ret;
}
drivers/char/drm/r128_drv.c
View file @ 0fa821d8
......@@ -37,45 +37,6 @@
#include "r128_drv.h"
#include "ati_pcigart.h"
#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
#define DRIVER_NAME "r128"
#define DRIVER_DESC "ATI Rage 128"
#define DRIVER_DATE "20010917"
#define DRIVER_MAJOR 2
#define DRIVER_MINOR 2
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { r128_cce_buffers, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_cce_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_engine_reset, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)] = { r128_cce_indices, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)] = { r128_cce_blit, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 },
#if 0
/* GH: Count data sent to card via ring or vertex/indirect buffers.
*/
#define __HAVE_COUNTERS 3
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
#endif
#include "drm_agpsupport.h"
#include "drm_auth.h"
#include "drm_bufs.h"
......@@ -83,26 +44,6 @@
#include "drm_dma.h"
#include "drm_drawable.h"
#include "drm_drv.h"
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* JH- We have to hand expand the string ourselves because of the cpp. If
* anyone can think of a way that we can fit into the __setup macro without
* changing it, then please send the solution my way.
*/
static int __init r128_options( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", r128_options );
#endif
#include "drm_fops.h"
#include "drm_init.h"
#include "drm_ioctl.h"
......
drivers/char/drm/r128_drv.h
View file @ 0fa821d8
......@@ -34,8 +34,8 @@
#ifndef __R128_DRV_H__
#define __R128_DRV_H__
#define GET_RING_HEAD(ring) readl( (volatile u32 *) (ring)->head )
#define SET_RING_HEAD(ring,val) writel( (val), (volatile u32 *) (ring)->head )
#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head )
#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head, (val) )
typedef struct drm_r128_freelist {
unsigned int age;
......@@ -116,29 +116,21 @@ typedef struct drm_r128_buf_priv {
} drm_r128_buf_priv_t;
/* r128_cce.c */
extern int r128_cce_init( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_start( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_stop( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_idle( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_engine_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_fullscreen( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_buffers( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_init( DRM_IOCTL_ARGS );
extern int r128_cce_start( DRM_IOCTL_ARGS );
extern int r128_cce_stop( DRM_IOCTL_ARGS );
extern int r128_cce_reset( DRM_IOCTL_ARGS );
extern int r128_cce_idle( DRM_IOCTL_ARGS );
extern int r128_engine_reset( DRM_IOCTL_ARGS );
extern int r128_fullscreen( DRM_IOCTL_ARGS );
extern int r128_cce_buffers( DRM_IOCTL_ARGS );
extern void r128_freelist_reset( drm_device_t *dev );
extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
static inline void
static __inline__ void
r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring )
{
ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32);
......@@ -151,22 +143,14 @@ extern int r128_do_cleanup_cce( drm_device_t *dev );
extern int r128_do_cleanup_pageflip( drm_device_t *dev );
/* r128_state.c */
extern int r128_cce_clear( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_swap( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_vertex( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_indices( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_blit( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_depth( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_stipple( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_indirect( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int r128_cce_clear( DRM_IOCTL_ARGS );
extern int r128_cce_swap( DRM_IOCTL_ARGS );
extern int r128_cce_vertex( DRM_IOCTL_ARGS );
extern int r128_cce_indices( DRM_IOCTL_ARGS );
extern int r128_cce_blit( DRM_IOCTL_ARGS );
extern int r128_cce_depth( DRM_IOCTL_ARGS );
extern int r128_cce_stipple( DRM_IOCTL_ARGS );
extern int r128_cce_indirect( DRM_IOCTL_ARGS );
/* Register definitions, register access macros and drmAddMap constants
......@@ -384,11 +368,11 @@ extern int r128_cce_indirect( struct inode *inode, struct file *filp,
#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
#define R128_ADDR(reg) (R128_BASE( reg ) + reg)
#define R128_READ(reg) readl( (volatile u32 *) R128_ADDR(reg) )
#define R128_WRITE(reg,val) writel( (val), (volatile u32 *) R128_ADDR(reg) )
#define R128_READ(reg) DRM_READ32( (volatile u32 *) R128_ADDR(reg) )
#define R128_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) R128_ADDR(reg), (val) )
#define R128_READ8(reg) readb( (volatile u8 *) R128_ADDR(reg) )
#define R128_WRITE8(reg,val) writeb( (val), (volatile u8 *) R128_ADDR(reg) )
#define R128_READ8(reg) DRM_READ8( (volatile u8 *) R128_ADDR(reg) )
#define R128_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) R128_ADDR(reg), (val) )
#define R128_WRITE_PLL(addr,val) \
do { \
......@@ -416,10 +400,9 @@ extern int R128_READ_PLL(drm_device_t *dev, int addr);
#define LOCK_TEST_WITH_RETURN( dev ) \
do { \
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
dev->lock.pid != current->pid ) { \
DRM_ERROR( "%s called without lock held\n", \
__FUNCTION__ ); \
return -EINVAL; \
dev->lock.pid != DRM_CURRENTPID ) { \
DRM_ERROR( "%s called without lock held\n", __func__ ); \
return DRM_ERR(EINVAL); \
} \
} while (0)
......@@ -431,12 +414,13 @@ do { \
r128_update_ring_snapshot( ring ); \
if ( ring->space >= ring->high_mark ) \
goto __ring_space_done; \
udelay( 1 ); \
DRM_UDELAY(1); \
} \
DRM_ERROR( "ring space check failed!\n" ); \
return -EBUSY; \
return DRM_ERR(EBUSY); \
} \
__ring_space_done: \
; \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
......@@ -444,7 +428,7 @@ do { \
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
int __ret = r128_do_cce_idle( dev_priv ); \
if ( __ret < 0 ) return __ret; \
if ( __ret ) return __ret; \
sarea_priv->last_dispatch = 0; \
r128_freelist_reset( dev ); \
} \
......@@ -463,7 +447,7 @@ do { \
#if defined(__powerpc__)
#define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
#else
#define r128_flush_write_combine() mb()
#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER()
#endif
......@@ -475,7 +459,7 @@ do { \
#define BEGIN_RING( n ) do { \
if ( R128_VERBOSE ) { \
DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
(n), __FUNCTION__ ); \
(n), __func__ ); \
} \
if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
......
drivers/char/drm/r128_state.c
View file @ 0fa821d8
......@@ -27,14 +27,11 @@
* Gareth Hughes <gareth@valinux.com>
*/
#define __NO_VERSION__
#include "r128.h"
#include "drmP.h"
#include "drm.h"
#include "r128_drm.h"
#include "r128_drv.h"
#include "drm.h"
#include <linux/delay.h>
/* ================================================================
......@@ -46,7 +43,7 @@ static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
{
u32 aux_sc_cntl = 0x00000000;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 17 );
......@@ -84,12 +81,12 @@ static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
ADVANCE_RING();
}
static inline void r128_emit_core( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 2 );
......@@ -99,12 +96,12 @@ static inline void r128_emit_core( drm_r128_private_t *dev_priv )
ADVANCE_RING();
}
static inline void r128_emit_context( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 13 );
......@@ -125,12 +122,12 @@ static inline void r128_emit_context( drm_r128_private_t *dev_priv )
ADVANCE_RING();
}
static inline void r128_emit_setup( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 3 );
......@@ -141,12 +138,12 @@ static inline void r128_emit_setup( drm_r128_private_t *dev_priv )
ADVANCE_RING();
}
static inline void r128_emit_masks( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 5 );
......@@ -160,12 +157,12 @@ static inline void r128_emit_masks( drm_r128_private_t *dev_priv )
ADVANCE_RING();
}
static inline void r128_emit_window( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 2 );
......@@ -175,14 +172,14 @@ static inline void r128_emit_window( drm_r128_private_t *dev_priv )
ADVANCE_RING();
}
static inline void r128_emit_tex0( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
int i;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS );
......@@ -202,13 +199,13 @@ static inline void r128_emit_tex0( drm_r128_private_t *dev_priv )
ADVANCE_RING();
}
static inline void r128_emit_tex1( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
int i;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
DRM_DEBUG( " %s\n", __func__ );
BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS );
......@@ -226,12 +223,12 @@ static inline void r128_emit_tex1( drm_r128_private_t *dev_priv )
ADVANCE_RING();
}
static inline void r128_emit_state( drm_r128_private_t *dev_priv )
static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int dirty = sarea_priv->dirty;
DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
DRM_DEBUG( "%s: dirty=0x%08x\n", __func__, dirty );
if ( dirty & R128_UPLOAD_CORE ) {
r128_emit_core( dev_priv );
......@@ -372,7 +369,7 @@ static void r128_cce_dispatch_clear( drm_device_t *dev,
unsigned int flags = clear->flags;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "%s\n", __func__ );
if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
unsigned int tmp = flags;
......@@ -475,7 +472,7 @@ static void r128_cce_dispatch_swap( drm_device_t *dev )
drm_clip_rect_t *pbox = sarea_priv->boxes;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "%s\n", __func__ );
#if R128_PERFORMANCE_BOXES
/* Do some trivial performance monitoring...
......@@ -531,7 +528,7 @@ static void r128_cce_dispatch_flip( drm_device_t *dev )
{
drm_r128_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
DRM_DEBUG( "page=%d\n", dev_priv->current_page );
#if R128_PERFORMANCE_BOXES
/* Do some trivial performance monitoring...
......@@ -580,8 +577,7 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
int prim = buf_priv->prim;
int i = 0;
RING_LOCALS;
DRM_DEBUG( "%s: buf=%d nbox=%d\n",
__FUNCTION__, buf->idx, sarea_priv->nbox );
DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox );
if ( 0 )
r128_print_dirty( "dispatch_vertex", sarea_priv->dirty );
......@@ -792,7 +788,7 @@ static int r128_cce_dispatch_blit( drm_device_t *dev,
u32 *data;
int dword_shift, dwords;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
/* The compiler won't optimize away a division by a variable,
* even if the only legal values are powers of two. Thus, we'll
......@@ -813,7 +809,7 @@ static int r128_cce_dispatch_blit( drm_device_t *dev,
break;
default:
DRM_ERROR( "invalid blit format %d\n", blit->format );
return -EINVAL;
return DRM_ERR(EINVAL);
}
/* Flush the pixel cache, and mark the contents as Read Invalid.
......@@ -833,14 +829,14 @@ static int r128_cce_dispatch_blit( drm_device_t *dev,
buf = dma->buflist[blit->idx];
buf_priv = buf->dev_private;
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", blit->idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
buf_priv->discard = 1;
......@@ -902,36 +898,36 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
u8 *mask;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
count = depth->n;
if ( copy_from_user( &x, depth->x, sizeof(x) ) ) {
return -EFAULT;
if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
return DRM_ERR(EFAULT);
}
if ( copy_from_user( &y, depth->y, sizeof(y) ) ) {
return -EFAULT;
if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) {
return DRM_ERR(EFAULT);
}
buffer = kmalloc( depth->n * sizeof(u32), GFP_KERNEL );
buffer = DRM_MALLOC( depth->n * sizeof(u32) );
if ( buffer == NULL )
return -ENOMEM;
if ( copy_from_user( buffer, depth->buffer,
return DRM_ERR(ENOMEM);
if ( DRM_COPY_FROM_USER( buffer, depth->buffer,
depth->n * sizeof(u32) ) ) {
kfree( buffer );
return -EFAULT;
DRM_FREE( buffer );
return DRM_ERR(EFAULT);
}
if ( depth->mask ) {
mask = kmalloc( depth->n * sizeof(u8), GFP_KERNEL );
mask = DRM_MALLOC( depth->n * sizeof(u8) );
if ( mask == NULL ) {
kfree( buffer );
return -ENOMEM;
DRM_FREE( buffer );
return DRM_ERR(ENOMEM);
}
if ( copy_from_user( mask, depth->mask,
if ( DRM_COPY_FROM_USER( mask, depth->mask,
depth->n * sizeof(u8) ) ) {
kfree( buffer );
kfree( mask );
return -EFAULT;
DRM_FREE( buffer );
DRM_FREE( mask );
return DRM_ERR(EFAULT);
}
for ( i = 0 ; i < count ; i++, x++ ) {
......@@ -957,7 +953,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
}
}
kfree( mask );
DRM_FREE( mask );
} else {
for ( i = 0 ; i < count ; i++, x++ ) {
BEGIN_RING( 6 );
......@@ -981,7 +977,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
}
}
kfree( buffer );
DRM_FREE( buffer );
return 0;
}
......@@ -995,59 +991,59 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
u8 *mask;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
count = depth->n;
x = kmalloc( count * sizeof(*x), GFP_KERNEL );
x = DRM_MALLOC( count * sizeof(*x) );
if ( x == NULL ) {
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
y = kmalloc( count * sizeof(*y), GFP_KERNEL );
y = DRM_MALLOC( count * sizeof(*y) );
if ( y == NULL ) {
kfree( x );
return -ENOMEM;
DRM_FREE( x );
return DRM_ERR(ENOMEM);
}
if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) {
kfree( x );
kfree( y );
return -EFAULT;
if ( DRM_COPY_FROM_USER( x, depth->x, count * sizeof(int) ) ) {
DRM_FREE( x );
DRM_FREE( y );
return DRM_ERR(EFAULT);
}
if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) {
kfree( x );
kfree( y );
return -EFAULT;
if ( DRM_COPY_FROM_USER( y, depth->y, count * sizeof(int) ) ) {
DRM_FREE( x );
DRM_FREE( y );
return DRM_ERR(EFAULT);
}
buffer = kmalloc( depth->n * sizeof(u32), GFP_KERNEL );
buffer = DRM_MALLOC( depth->n * sizeof(u32) );
if ( buffer == NULL ) {
kfree( x );
kfree( y );
return -ENOMEM;
DRM_FREE( x );
DRM_FREE( y );
return DRM_ERR(ENOMEM);
}
if ( copy_from_user( buffer, depth->buffer,
if ( DRM_COPY_FROM_USER( buffer, depth->buffer,
depth->n * sizeof(u32) ) ) {
kfree( x );
kfree( y );
kfree( buffer );
return -EFAULT;
DRM_FREE( x );
DRM_FREE( y );
DRM_FREE( buffer );
return DRM_ERR(EFAULT);
}
if ( depth->mask ) {
mask = kmalloc( depth->n * sizeof(u8), GFP_KERNEL );
mask = DRM_MALLOC( depth->n * sizeof(u8) );
if ( mask == NULL ) {
kfree( x );
kfree( y );
kfree( buffer );
return -ENOMEM;
DRM_FREE( x );
DRM_FREE( y );
DRM_FREE( buffer );
return DRM_ERR(ENOMEM);
}
if ( copy_from_user( mask, depth->mask,
if ( DRM_COPY_FROM_USER( mask, depth->mask,
depth->n * sizeof(u8) ) ) {
kfree( x );
kfree( y );
kfree( buffer );
kfree( mask );
return -EFAULT;
DRM_FREE( x );
DRM_FREE( y );
DRM_FREE( buffer );
DRM_FREE( mask );
return DRM_ERR(EFAULT);
}
for ( i = 0 ; i < count ; i++ ) {
......@@ -1073,7 +1069,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
}
}
kfree( mask );
DRM_FREE( mask );
} else {
for ( i = 0 ; i < count ; i++ ) {
BEGIN_RING( 6 );
......@@ -1097,9 +1093,9 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
}
}
kfree( x );
kfree( y );
kfree( buffer );
DRM_FREE( x );
DRM_FREE( y );
DRM_FREE( buffer );
return 0;
}
......@@ -1110,14 +1106,14 @@ static int r128_cce_dispatch_read_span( drm_device_t *dev,
drm_r128_private_t *dev_priv = dev->dev_private;
int count, x, y;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
count = depth->n;
if ( copy_from_user( &x, depth->x, sizeof(x) ) ) {
return -EFAULT;
if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
return DRM_ERR(EFAULT);
}
if ( copy_from_user( &y, depth->y, sizeof(y) ) ) {
return -EFAULT;
if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) {
return DRM_ERR(EFAULT);
}
BEGIN_RING( 7 );
......@@ -1152,31 +1148,31 @@ static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
int count, *x, *y;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "%s\n", __func__ );
count = depth->n;
if ( count > dev_priv->depth_pitch ) {
count = dev_priv->depth_pitch;
}
x = kmalloc( count * sizeof(*x), GFP_KERNEL );
x = DRM_MALLOC( count * sizeof(*x) );
if ( x == NULL ) {
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
y = kmalloc( count * sizeof(*y), GFP_KERNEL );
y = DRM_MALLOC( count * sizeof(*y) );
if ( y == NULL ) {
kfree( x );
return -ENOMEM;
DRM_FREE( x );
return DRM_ERR(ENOMEM);
}
if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) {
kfree( x );
kfree( y );
return -EFAULT;
if ( DRM_COPY_FROM_USER( x, depth->x, count * sizeof(int) ) ) {
DRM_FREE( x );
DRM_FREE( y );
return DRM_ERR(EFAULT);
}
if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) {
kfree( x );
kfree( y );
return -EFAULT;
if ( DRM_COPY_FROM_USER( y, depth->y, count * sizeof(int) ) ) {
DRM_FREE( x );
DRM_FREE( y );
return DRM_ERR(EFAULT);
}
for ( i = 0 ; i < count ; i++ ) {
......@@ -1203,8 +1199,8 @@ static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
ADVANCE_RING();
}
kfree( x );
kfree( y );
DRM_FREE( x );
DRM_FREE( y );
return 0;
}
......@@ -1219,7 +1215,7 @@ static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple )
drm_r128_private_t *dev_priv = dev->dev_private;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "%s\n", __func__ );
BEGIN_RING( 33 );
......@@ -1236,21 +1232,18 @@ static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple )
* IOCTL functions
*/
int r128_cce_clear( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_clear( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_clear_t clear;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &clear, (drm_r128_clear_t *) arg,
sizeof(clear) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t *) data,
sizeof(clear) );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1266,14 +1259,12 @@ int r128_cce_clear( struct inode *inode, struct file *filp,
return 0;
}
int r128_cce_swap( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_swap( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "%s\n", __func__ );
LOCK_TEST_WITH_RETURN( dev );
......@@ -1293,11 +1284,9 @@ int r128_cce_swap( struct inode *inode, struct file *filp,
return 0;
}
int r128_cce_vertex( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_vertex( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
......@@ -1307,27 +1296,26 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &vertex, (drm_r128_vertex_t *)arg,
sizeof(vertex) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t *) data,
sizeof(vertex) );
DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
__FUNCTION__, current->pid,
DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
DRM_CURRENTPID,
vertex.idx, vertex.count, vertex.discard );
if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
vertex.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( vertex.prim < 0 ||
vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
DRM_ERROR( "buffer prim %d\n", vertex.prim );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1336,14 +1324,14 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
buf = dma->buflist[vertex.idx];
buf_priv = buf->dev_private;
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
buf->used = vertex.count;
......@@ -1355,11 +1343,9 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
return 0;
}
int r128_cce_indices( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_indices( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
......@@ -1370,27 +1356,25 @@ int r128_cce_indices( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &elts, (drm_r128_indices_t *)arg,
sizeof(elts) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t *) data,
sizeof(elts) );
DRM_DEBUG( "%s: pid=%d buf=%d s=%d e=%d d=%d\n",
__FUNCTION__, current->pid,
DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
elts.idx, elts.start, elts.end, elts.discard );
if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
elts.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( elts.prim < 0 ||
elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
DRM_ERROR( "buffer prim %d\n", elts.prim );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1399,14 +1383,14 @@ int r128_cce_indices( struct inode *inode, struct file *filp,
buf = dma->buflist[elts.idx];
buf_priv = buf->dev_private;
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", elts.idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
count = (elts.end - elts.start) / sizeof(u16);
......@@ -1414,11 +1398,11 @@ int r128_cce_indices( struct inode *inode, struct file *filp,
if ( elts.start & 0x7 ) {
DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( elts.start < buf->used ) {
DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
return -EINVAL;
return DRM_ERR(EINVAL);
}
buf->used = elts.end;
......@@ -1430,28 +1414,24 @@ int r128_cce_indices( struct inode *inode, struct file *filp,
return 0;
}
int r128_cce_blit( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_blit( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_device_dma_t *dma = dev->dma;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_blit_t blit;
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &blit, (drm_r128_blit_t *)arg,
sizeof(blit) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t *) data,
sizeof(blit) );
DRM_DEBUG( "%s: pid=%d index=%d\n",
__FUNCTION__, current->pid, blit.idx );
DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx );
if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
blit.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1460,19 +1440,16 @@ int r128_cce_blit( struct inode *inode, struct file *filp,
return r128_cce_dispatch_blit( dev, &blit );
}
int r128_cce_depth( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_depth( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_depth_t depth;
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &depth, (drm_r128_depth_t *)arg,
sizeof(depth) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t *) data,
sizeof(depth) );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1487,27 +1464,24 @@ int r128_cce_depth( struct inode *inode, struct file *filp,
return r128_cce_dispatch_read_pixels( dev, &depth );
}
return -EINVAL;
return DRM_ERR(EINVAL);
}
int r128_cce_stipple( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_stipple( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_stipple_t stipple;
u32 mask[32];
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &stipple, (drm_r128_stipple_t *)arg,
sizeof(stipple) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t *) data,
sizeof(stipple) );
if ( copy_from_user( &mask, stipple.mask,
if ( DRM_COPY_FROM_USER( &mask, stipple.mask,
32 * sizeof(u32) ) )
return -EFAULT;
return DRM_ERR( EFAULT );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1516,11 +1490,9 @@ int r128_cce_stipple( struct inode *inode, struct file *filp,
return 0;
}
int r128_cce_indirect( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int r128_cce_indirect( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
......@@ -1533,13 +1505,12 @@ int r128_cce_indirect( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &indirect, (drm_r128_indirect_t *)arg,
sizeof(indirect) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t *) data,
sizeof(indirect) );
DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
indirect.idx, indirect.start,
......@@ -1548,26 +1519,26 @@ int r128_cce_indirect( struct inode *inode, struct file *filp,
if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
indirect.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
buf = dma->buflist[indirect.idx];
buf_priv = buf->dev_private;
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( indirect.start < buf->used ) {
DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
indirect.start, buf->used );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......
drivers/char/drm/radeon.h
View file @ 0fa821d8
......@@ -25,6 +25,7 @@
*
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Keith Whitwell <keith@tungstengraphics.com>
*/
#ifndef __RADEON_H__
......@@ -43,6 +44,51 @@
#define __HAVE_SG 1
#define __HAVE_PCI_DMA 1
#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
#define DRIVER_NAME "radeon"
#define DRIVER_DESC "ATI Radeon"
#define DRIVER_DATE "20020611"
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 4
#define DRIVER_PATCHLEVEL 0
/* Interface history:
*
* 1.1 - ??
* 1.2 - Add vertex2 ioctl (keith)
* - Add stencil capability to clear ioctl (gareth, keith)
* - Increase MAX_TEXTURE_LEVELS (brian)
* 1.3 - Add cmdbuf ioctl (keith)
* - Add support for new radeon packets (keith)
* - Add getparam ioctl (keith)
* - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
* 1.4 - Add r200 packets to cmdbuf ioctl
* - Add r200 function to init ioctl
* - Add 'scalar2' hack to cmdbuf ioctl (must die)
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 },
/* Driver customization:
*/
#define DRIVER_PRERELEASE() do { \
......@@ -62,15 +108,6 @@
*/
#define __HAVE_DMA 1
#if 0
/* GH: Remove this for now... */
#define __HAVE_DMA_QUIESCENT 1
#define DRIVER_DMA_QUIESCENT() do { \
drm_radeon_private_t *dev_priv = dev->dev_private; \
return radeon_do_cp_idle( dev_priv ); \
} while (0)
#endif
/* Buffer customization:
*/
#define DRIVER_BUF_PRIV_T drm_radeon_buf_priv_t
......
drivers/char/drm/radeon_cp.c
View file @ 0fa821d8
......@@ -28,16 +28,12 @@
* Gareth Hughes <gareth@valinux.com>
*/
#define __NO_VERSION__
#include "radeon.h"
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include <linux/interrupt.h> /* For task queue support */
#include <linux/delay.h>
#define RADEON_FIFO_DEBUG 0
#if defined(__alpha__) || defined(__powerpc__)
......@@ -48,6 +44,266 @@
/* CP microcode (from ATI) */
static u32 R200_cp_microcode[][2] = {
{ 0x21007000, 0000000000 },
{ 0x20007000, 0000000000 },
{ 0x000000ab, 0x00000004 },
{ 0x000000af, 0x00000004 },
{ 0x66544a49, 0000000000 },
{ 0x49494174, 0000000000 },
{ 0x54517d83, 0000000000 },
{ 0x498d8b64, 0000000000 },
{ 0x49494949, 0000000000 },
{ 0x49da493c, 0000000000 },
{ 0x49989898, 0000000000 },
{ 0xd34949d5, 0000000000 },
{ 0x9dc90e11, 0000000000 },
{ 0xce9b9b9b, 0000000000 },
{ 0x000f0000, 0x00000016 },
{ 0x352e232c, 0000000000 },
{ 0x00000013, 0x00000004 },
{ 0x000f0000, 0x00000016 },
{ 0x352e272c, 0000000000 },
{ 0x000f0001, 0x00000016 },
{ 0x3239362f, 0000000000 },
{ 0x000077ef, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x00000020, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00061000, 0x00000002 },
{ 0x00000020, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00061000, 0x00000002 },
{ 0x00000020, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00000016, 0x00000004 },
{ 0x0003802a, 0x00000002 },
{ 0x040067e0, 0x00000002 },
{ 0x00000016, 0x00000004 },
{ 0x000077e0, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x000037e1, 0x00000002 },
{ 0x040067e1, 0x00000006 },
{ 0x000077e0, 0x00000002 },
{ 0x000077e1, 0x00000002 },
{ 0x000077e1, 0x00000006 },
{ 0xffffffff, 0000000000 },
{ 0x10000000, 0000000000 },
{ 0x0003802a, 0x00000002 },
{ 0x040067e0, 0x00000006 },
{ 0x00007675, 0x00000002 },
{ 0x00007676, 0x00000002 },
{ 0x00007677, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0003802b, 0x00000002 },
{ 0x04002676, 0x00000002 },
{ 0x00007677, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0000002e, 0x00000018 },
{ 0x0000002e, 0x00000018 },
{ 0000000000, 0x00000006 },
{ 0x0000002f, 0x00000018 },
{ 0x0000002f, 0x00000018 },
{ 0000000000, 0x00000006 },
{ 0x01605000, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x00098000, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x64c0603d, 0x00000004 },
{ 0x00080000, 0x00000016 },
{ 0000000000, 0000000000 },
{ 0x0400251d, 0x00000002 },
{ 0x00007580, 0x00000002 },
{ 0x00067581, 0x00000002 },
{ 0x04002580, 0x00000002 },
{ 0x00067581, 0x00000002 },
{ 0x00000046, 0x00000004 },
{ 0x00005000, 0000000000 },
{ 0x00061000, 0x00000002 },
{ 0x0000750e, 0x00000002 },
{ 0x00019000, 0x00000002 },
{ 0x00011055, 0x00000014 },
{ 0x00000055, 0x00000012 },
{ 0x0400250f, 0x00000002 },
{ 0x0000504a, 0x00000004 },
{ 0x00007565, 0x00000002 },
{ 0x00007566, 0x00000002 },
{ 0x00000051, 0x00000004 },
{ 0x01e655b4, 0x00000002 },
{ 0x4401b0dc, 0x00000002 },
{ 0x01c110dc, 0x00000002 },
{ 0x2666705d, 0x00000018 },
{ 0x040c2565, 0x00000002 },
{ 0x0000005d, 0x00000018 },
{ 0x04002564, 0x00000002 },
{ 0x00007566, 0x00000002 },
{ 0x00000054, 0x00000004 },
{ 0x00401060, 0x00000008 },
{ 0x00101000, 0x00000002 },
{ 0x000d80ff, 0x00000002 },
{ 0x00800063, 0x00000008 },
{ 0x000f9000, 0x00000002 },
{ 0x000e00ff, 0x00000002 },
{ 0000000000, 0x00000006 },
{ 0x00000080, 0x00000018 },
{ 0x00000054, 0x00000004 },
{ 0x00007576, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x00009000, 0x00000002 },
{ 0x00041000, 0x00000002 },
{ 0x0c00350e, 0x00000002 },
{ 0x00049000, 0x00000002 },
{ 0x00051000, 0x00000002 },
{ 0x01e785f8, 0x00000002 },
{ 0x00200000, 0x00000002 },
{ 0x00600073, 0x0000000c },
{ 0x00007563, 0x00000002 },
{ 0x006075f0, 0x00000021 },
{ 0x20007068, 0x00000004 },
{ 0x00005068, 0x00000004 },
{ 0x00007576, 0x00000002 },
{ 0x00007577, 0x00000002 },
{ 0x0000750e, 0x00000002 },
{ 0x0000750f, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00600076, 0x0000000c },
{ 0x006075f0, 0x00000021 },
{ 0x000075f8, 0x00000002 },
{ 0x00000076, 0x00000004 },
{ 0x000a750e, 0x00000002 },
{ 0x0020750f, 0x00000002 },
{ 0x00600079, 0x00000004 },
{ 0x00007570, 0x00000002 },
{ 0x00007571, 0x00000002 },
{ 0x00007572, 0x00000006 },
{ 0x00005000, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00007568, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x00000084, 0x0000000c },
{ 0x00058000, 0x00000002 },
{ 0x0c607562, 0x00000002 },
{ 0x00000086, 0x00000004 },
{ 0x00600085, 0x00000004 },
{ 0x400070dd, 0000000000 },
{ 0x000380dd, 0x00000002 },
{ 0x00000093, 0x0000001c },
{ 0x00065095, 0x00000018 },
{ 0x040025bb, 0x00000002 },
{ 0x00061096, 0x00000018 },
{ 0x040075bc, 0000000000 },
{ 0x000075bb, 0x00000002 },
{ 0x000075bc, 0000000000 },
{ 0x00090000, 0x00000006 },
{ 0x00090000, 0x00000002 },
{ 0x000d8002, 0x00000006 },
{ 0x00005000, 0x00000002 },
{ 0x00007821, 0x00000002 },
{ 0x00007800, 0000000000 },
{ 0x00007821, 0x00000002 },
{ 0x00007800, 0000000000 },
{ 0x01665000, 0x00000002 },
{ 0x000a0000, 0x00000002 },
{ 0x000671cc, 0x00000002 },
{ 0x0286f1cd, 0x00000002 },
{ 0x000000a3, 0x00000010 },
{ 0x21007000, 0000000000 },
{ 0x000000aa, 0x0000001c },
{ 0x00065000, 0x00000002 },
{ 0x000a0000, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x000b0000, 0x00000002 },
{ 0x38067000, 0x00000002 },
{ 0x000a00a6, 0x00000004 },
{ 0x20007000, 0000000000 },
{ 0x01200000, 0x00000002 },
{ 0x20077000, 0x00000002 },
{ 0x01200000, 0x00000002 },
{ 0x20007000, 0000000000 },
{ 0x00061000, 0x00000002 },
{ 0x0120751b, 0x00000002 },
{ 0x8040750a, 0x00000002 },
{ 0x8040750b, 0x00000002 },
{ 0x00110000, 0x00000002 },
{ 0x000380dd, 0x00000002 },
{ 0x000000bd, 0x0000001c },
{ 0x00061096, 0x00000018 },
{ 0x844075bd, 0x00000002 },
{ 0x00061095, 0x00000018 },
{ 0x840075bb, 0x00000002 },
{ 0x00061096, 0x00000018 },
{ 0x844075bc, 0x00000002 },
{ 0x000000c0, 0x00000004 },
{ 0x804075bd, 0x00000002 },
{ 0x800075bb, 0x00000002 },
{ 0x804075bc, 0x00000002 },
{ 0x00108000, 0x00000002 },
{ 0x01400000, 0x00000002 },
{ 0x006000c4, 0x0000000c },
{ 0x20c07000, 0x00000020 },
{ 0x000000c6, 0x00000012 },
{ 0x00800000, 0x00000006 },
{ 0x0080751d, 0x00000006 },
{ 0x000025bb, 0x00000002 },
{ 0x000040c0, 0x00000004 },
{ 0x0000775c, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00661000, 0x00000002 },
{ 0x0460275d, 0x00000020 },
{ 0x00004000, 0000000000 },
{ 0x00007999, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00661000, 0x00000002 },
{ 0x0460299b, 0x00000020 },
{ 0x00004000, 0000000000 },
{ 0x01e00830, 0x00000002 },
{ 0x21007000, 0000000000 },
{ 0x00005000, 0x00000002 },
{ 0x00038042, 0x00000002 },
{ 0x040025e0, 0x00000002 },
{ 0x000075e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000380d9, 0x00000002 },
{ 0x04007394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static u32 radeon_cp_microcode[][2] = {
{ 0x21007000, 0000000000 },
{ 0x20007000, 0000000000 },
......@@ -349,6 +605,8 @@ static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
u32 tmp;
int i;
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
tmp |= RADEON_RB2D_DC_FLUSH_ALL;
RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
......@@ -358,14 +616,14 @@ static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
& RADEON_RB2D_DC_BUSY) ) {
return 0;
}
udelay( 1 );
DRM_UDELAY( 1 );
}
#if RADEON_FIFO_DEBUG
DRM_ERROR( "failed!\n" );
radeon_status( dev_priv );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
......@@ -373,26 +631,30 @@ static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
{
int i;
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
& RADEON_RBBM_FIFOCNT_MASK );
if ( slots >= entries ) return 0;
udelay( 1 );
DRM_UDELAY( 1 );
}
#if RADEON_FIFO_DEBUG
DRM_ERROR( "failed!\n" );
radeon_status( dev_priv );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
{
int i, ret;
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
ret = radeon_do_wait_for_fifo( dev_priv, 64 );
if ( ret < 0 ) return ret;
if ( ret ) return ret;
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
if ( !(RADEON_READ( RADEON_RBBM_STATUS )
......@@ -400,14 +662,14 @@ static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
radeon_do_pixcache_flush( dev_priv );
return 0;
}
udelay( 1 );
DRM_UDELAY( 1 );
}
#if RADEON_FIFO_DEBUG
DRM_ERROR( "failed!\n" );
radeon_status( dev_priv );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
......@@ -419,16 +681,31 @@ static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
{
int i;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
radeon_do_wait_for_idle( dev_priv );
RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
for ( i = 0 ; i < 256 ; i++ ) {
RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
radeon_cp_microcode[i][1] );
RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
radeon_cp_microcode[i][0] );
if (dev_priv->is_r200)
{
DRM_INFO("Loading R200 Microcode\n");
for ( i = 0 ; i < 256 ; i++ )
{
RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
R200_cp_microcode[i][1] );
RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
R200_cp_microcode[i][0] );
}
}
else
{
for ( i = 0 ; i < 256 ; i++ ) {
RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
radeon_cp_microcode[i][1] );
RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
radeon_cp_microcode[i][0] );
}
}
}
......@@ -438,7 +715,7 @@ static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
*/
static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
{
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
#if 0
u32 tmp;
......@@ -452,7 +729,7 @@ static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
{
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
BEGIN_RING( 6 );
......@@ -471,7 +748,7 @@ int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
{
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
radeon_do_wait_for_idle( dev_priv );
......@@ -496,7 +773,7 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
{
u32 cur_read_ptr;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
......@@ -510,7 +787,7 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
*/
static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
{
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
......@@ -523,7 +800,7 @@ static int radeon_do_engine_reset( drm_device_t *dev )
{
drm_radeon_private_t *dev_priv = dev->dev_private;
u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
radeon_do_pixcache_flush( dev_priv );
......@@ -632,6 +909,34 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
entry->handle + tmp_ofs );
}
/* Initialize the scratch register pointer. This will cause
* the scratch register values to be written out to memory
* whenever they are updated.
*
* We simply put this behind the ring read pointer, this works
* with PCI GART as well as (whatever kind of) AGP GART
*/
RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
+ RADEON_SCRATCH_REG_OFFSET );
dev_priv->scratch = ((__volatile__ u32 *)
dev_priv->ring.head +
(RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
RADEON_WRITE( RADEON_LAST_FRAME_REG,
dev_priv->sarea_priv->last_frame );
dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
dev_priv->sarea_priv->last_dispatch );
dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
RADEON_WRITE( RADEON_LAST_CLEAR_REG,
dev_priv->sarea_priv->last_clear );
/* Set ring buffer size */
#ifdef __BIG_ENDIAN
RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
......@@ -656,13 +961,12 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
{
drm_radeon_private_t *dev_priv;
struct list_head *list;
u32 tmp;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
if ( dev_priv == NULL )
return -ENOMEM;
return DRM_ERR(ENOMEM);
memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
......@@ -675,7 +979,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
#endif
......@@ -683,7 +987,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
DRM_ERROR( "PCI GART memory not allocated!\n" );
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
dev_priv->usec_timeout = init->usec_timeout;
......@@ -692,15 +996,13 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
DRM_DEBUG( "TIMEOUT problem!\n" );
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
dev_priv->do_boxes = 1;
dev_priv->cp_mode = init->cp_mode;
/* Simple idle check.
*/
atomic_set( &dev_priv->idle_count, 0 );
/* We don't support anything other than bus-mastering ring mode,
* but the ring can be in either AGP or PCI space for the ring
* read pointer.
......@@ -710,7 +1012,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
switch ( init->fb_bpp ) {
......@@ -776,20 +1078,13 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
RADEON_ROUND_MODE_TRUNC |
RADEON_ROUND_PREC_8TH_PIX);
list_for_each(list, &dev->maplist->head) {
drm_map_list_t *r_list = (drm_map_list_t *)list;
if( r_list->map &&
r_list->map->type == _DRM_SHM &&
r_list->map->flags & _DRM_CONTAINS_LOCK ) {
dev_priv->sarea = r_list->map;
break;
}
}
DRM_GETSAREA();
if(!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
......@@ -797,35 +1092,35 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
DRM_ERROR("could not find framebuffer!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
if(!dev_priv->mmio) {
DRM_ERROR("could not find mmio region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
if(!dev_priv->cp_ring) {
DRM_ERROR("could not find cp ring region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
if(!dev_priv->ring_rptr) {
DRM_ERROR("could not find ring read pointer!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
if(!dev_priv->buffers) {
DRM_ERROR("could not find dma buffer region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( !dev_priv->is_pci ) {
......@@ -835,7 +1130,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
DRM_ERROR("could not find agp texture region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
}
......@@ -853,7 +1148,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
DRM_ERROR("could not find ioremap agp regions!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -EINVAL;
return DRM_ERR(EINVAL);
}
} else {
dev_priv->cp_ring->handle =
......@@ -905,41 +1200,14 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
#if 0
/* Initialize the scratch register pointer. This will cause
* the scratch register values to be written out to memory
* whenever they are updated.
* FIXME: This doesn't quite work yet, so we're disabling it
* for the release.
*/
RADEON_WRITE( RADEON_SCRATCH_ADDR, (dev_priv->ring_rptr->offset +
RADEON_SCRATCH_REG_OFFSET) );
RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
#endif
dev_priv->scratch = ((__volatile__ u32 *)
dev_priv->ring_rptr->handle +
(RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
dev_priv->sarea_priv->last_frame = 0;
RADEON_WRITE( RADEON_LAST_FRAME_REG,
dev_priv->sarea_priv->last_frame );
dev_priv->sarea_priv->last_dispatch = 0;
RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
dev_priv->sarea_priv->last_dispatch );
dev_priv->sarea_priv->last_clear = 0;
RADEON_WRITE( RADEON_LAST_CLEAR_REG,
dev_priv->sarea_priv->last_clear );
#if __REALLY_HAVE_SG
if ( dev_priv->is_pci ) {
if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
&dev_priv->bus_pci_gart)) {
DRM_ERROR( "failed to init PCI GART!\n" );
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return -ENOMEM;
return DRM_ERR(ENOMEM);
}
/* Turn on PCI GART
*/
......@@ -962,12 +1230,15 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
} else {
#endif /* __REALLY_HAVE_SG */
/* Turn off PCI GART
*/
tmp = RADEON_READ( RADEON_AIC_CNTL )
& ~RADEON_PCIGART_TRANSLATE_EN;
RADEON_WRITE( RADEON_AIC_CNTL, tmp );
#if __REALLY_HAVE_SG
}
#endif /* __REALLY_HAVE_SG */
radeon_cp_load_microcode( dev_priv );
radeon_cp_init_ring_buffer( dev, dev_priv );
......@@ -983,7 +1254,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
int radeon_do_cleanup_cp( drm_device_t *dev )
{
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
if ( dev->dev_private ) {
drm_radeon_private_t *dev_priv = dev->dev_private;
......@@ -993,10 +1264,12 @@ int radeon_do_cleanup_cp( drm_device_t *dev )
DRM_IOREMAPFREE( dev_priv->ring_rptr );
DRM_IOREMAPFREE( dev_priv->buffers );
} else {
#if __REALLY_HAVE_SG
if (!DRM(ati_pcigart_cleanup)( dev,
dev_priv->phys_pci_gart,
dev_priv->bus_pci_gart ))
DRM_ERROR( "failed to cleanup PCI GART!\n" );
#endif /* __REALLY_HAVE_SG */
}
DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
......@@ -1007,43 +1280,39 @@ int radeon_do_cleanup_cp( drm_device_t *dev )
return 0;
}
int radeon_cp_init( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_init( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_init_t init;
if ( copy_from_user( &init, (drm_radeon_init_t *)arg, sizeof(init) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
switch ( init.func ) {
case RADEON_INIT_CP:
case RADEON_INIT_R200_CP:
return radeon_do_init_cp( dev, &init );
case RADEON_CLEANUP_CP:
return radeon_do_cleanup_cp( dev );
}
return -EINVAL;
return DRM_ERR(EINVAL);
}
int radeon_cp_start( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_start( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( dev_priv->cp_running ) {
DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
DRM_DEBUG( "%s while CP running\n", __func__ );
return 0;
}
if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
__FUNCTION__, dev_priv->cp_mode );
__func__, dev_priv->cp_mode );
return 0;
}
......@@ -1055,20 +1324,17 @@ int radeon_cp_start( struct inode *inode, struct file *filp,
/* Stop the CP. The engine must have been idled before calling this
* routine.
*/
int radeon_cp_stop( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_stop( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_cp_stop_t stop;
int ret;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &stop, (drm_radeon_init_t *)arg, sizeof(stop) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
/* Flush any pending CP commands. This ensures any outstanding
* commands are exectuted by the engine before we turn it off.
......@@ -1082,7 +1348,7 @@ int radeon_cp_stop( struct inode *inode, struct file *filp,
*/
if ( stop.idle ) {
ret = radeon_do_cp_idle( dev_priv );
if ( ret < 0 ) return ret;
if ( ret ) return ret;
}
/* Finally, we can turn off the CP. If the engine isn't idle,
......@@ -1099,19 +1365,17 @@ int radeon_cp_stop( struct inode *inode, struct file *filp,
/* Just reset the CP ring. Called as part of an X Server engine reset.
*/
int radeon_cp_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_reset( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
return -EINVAL;
DRM_DEBUG( "%s called before init done\n", __func__ );
return DRM_ERR(EINVAL);
}
radeon_do_cp_reset( dev_priv );
......@@ -1122,25 +1386,21 @@ int radeon_cp_reset( struct inode *inode, struct file *filp,
return 0;
}
int radeon_cp_idle( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_idle( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
return radeon_do_cp_idle( dev_priv );
}
int radeon_engine_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_engine_reset( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEVICE;
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
......@@ -1154,8 +1414,7 @@ int radeon_engine_reset( struct inode *inode, struct file *filp,
/* KW: Deprecated to say the least:
*/
int radeon_fullscreen( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_fullscreen( DRM_IOCTL_ARGS )
{
return 0;
}
......@@ -1172,6 +1431,14 @@ int radeon_fullscreen( struct inode *inode, struct file *filp,
* completed rendering.
*
* KW: It's also a good way to find free buffers quickly.
*
* KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
* sleep. However, bugs in older versions of radeon_accel.c mean that
* we essentially have to do this, else old clients will break.
*
* However, it does leave open a potential deadlock where all the
* buffers are held by other clients, which can't release them because
* they can't get the lock.
*/
drm_buf_t *radeon_freelist_get( drm_device_t *dev )
......@@ -1189,23 +1456,63 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
start = dev_priv->last_buf;
for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
u32 done_age = DRM_READ32(&dev_priv->scratch[1]);
for ( i = start ; i < dma->buf_count ; i++ ) {
buf = dma->buflist[i];
buf_priv = buf->dev_private;
if ( buf->pid == 0 || (buf->pending &&
buf_priv->age <= done_age) ) {
dev_priv->stats.requested_bufs++;
buf->pending = 0;
return buf;
}
start = 0;
}
udelay( 1 );
if (t) {
DRM_UDELAY( 1 );
dev_priv->stats.freelist_loops++;
}
}
DRM_ERROR( "returning NULL!\n" );
return NULL;
}
#if 0
drm_buf_t *radeon_freelist_get( drm_device_t *dev )
{
drm_device_dma_t *dma = dev->dma;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_buf_priv_t *buf_priv;
drm_buf_t *buf;
int i, t;
int start;
u32 done_age = DRM_READ32(&dev_priv->scratch[1]);
if ( ++dev_priv->last_buf >= dma->buf_count )
dev_priv->last_buf = 0;
start = dev_priv->last_buf;
dev_priv->stats.freelist_loops++;
for ( t = 0 ; t < 2 ; t++ ) {
for ( i = start ; i < dma->buf_count ; i++ ) {
buf = dma->buflist[i];
buf_priv = buf->dev_private;
if ( buf->pid == 0 || (buf->pending &&
buf_priv->age <= done_age) ) {
dev_priv->stats.requested_bufs++;
buf->pending = 0;
return buf;
}
}
start = 0;
}
return NULL;
}
#endif
void radeon_freelist_reset( drm_device_t *dev )
{
......@@ -1230,12 +1537,24 @@ int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
{
drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
int i;
u32 last_head = GET_RING_HEAD(ring);
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
radeon_update_ring_snapshot( ring );
u32 head = GET_RING_HEAD(ring);
ring->space = (head - ring->tail) * sizeof(u32);
if ( ring->space <= 0 )
ring->space += ring->size;
if ( ring->space > n )
return 0;
udelay( 1 );
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
if (head != last_head)
i = 0;
last_head = head;
DRM_UDELAY( 1 );
}
/* FIXME: This return value is ignored in the BEGIN_RING macro! */
......@@ -1243,7 +1562,7 @@ int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
radeon_status( dev_priv );
DRM_ERROR( "failed!\n" );
#endif
return -EBUSY;
return DRM_ERR(EBUSY);
}
static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
......@@ -1253,50 +1572,47 @@ static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
for ( i = d->granted_count ; i < d->request_count ; i++ ) {
buf = radeon_freelist_get( dev );
if ( !buf ) return -EAGAIN;
if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
buf->pid = current->pid;
buf->pid = DRM_CURRENTPID;
if ( copy_to_user( &d->request_indices[i], &buf->idx,
if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
sizeof(buf->idx) ) )
return -EFAULT;
if ( copy_to_user( &d->request_sizes[i], &buf->total,
return DRM_ERR(EFAULT);
if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
sizeof(buf->total) ) )
return -EFAULT;
return DRM_ERR(EFAULT);
d->granted_count++;
}
return 0;
}
int radeon_cp_buffers( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_buffers( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_device_dma_t *dma = dev->dma;
int ret = 0;
drm_dma_t d;
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
/* Please don't send us buffers.
*/
if ( d.send_count != 0 ) {
DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
current->pid, d.send_count );
return -EINVAL;
DRM_CURRENTPID, d.send_count );
return DRM_ERR(EINVAL);
}
/* We'll send you buffers.
*/
if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
current->pid, d.request_count, dma->buf_count );
return -EINVAL;
DRM_CURRENTPID, d.request_count, dma->buf_count );
return DRM_ERR(EINVAL);
}
d.granted_count = 0;
......@@ -1305,8 +1621,7 @@ int radeon_cp_buffers( struct inode *inode, struct file *filp,
ret = radeon_cp_get_buffers( dev, &d );
}
if ( copy_to_user( (drm_dma_t *)arg, &d, sizeof(d) ) )
return -EFAULT;
DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
return ret;
}
drivers/char/drm/radeon_drm.h
View file @ 0fa821d8
......@@ -89,7 +89,47 @@
#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
#define RADEON_MAX_STATE_PACKETS 21
#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
#define R200_EMIT_VAP_CTL 32 /* vap/1 */
#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
#define RADEON_MAX_STATE_PACKETS 61
/* Commands understood by cmd_buffer ioctl. More can be added but
......@@ -101,24 +141,25 @@
#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
#define RADEON_CMD_PACKET3 5 /* emit hw packet */
#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
typedef union {
int i;
struct {
char cmd_type, pad0, pad1, pad2;
unsigned char cmd_type, pad0, pad1, pad2;
} header;
struct {
char cmd_type, packet_id, pad0, pad1;
unsigned char cmd_type, packet_id, pad0, pad1;
} packet;
struct {
char cmd_type, offset, stride, count;
unsigned char cmd_type, offset, stride, count;
} scalars;
struct {
char cmd_type, offset, stride, count;
unsigned char cmd_type, offset, stride, count;
} vectors;
struct {
char cmd_type, buf_idx, pad0, pad1;
unsigned char cmd_type, buf_idx, pad0, pad1;
} dma;
} drm_radeon_cmd_header_t;
......@@ -327,7 +368,8 @@ typedef struct {
typedef struct drm_radeon_init {
enum {
RADEON_INIT_CP = 0x01,
RADEON_CLEANUP_CP = 0x02
RADEON_CLEANUP_CP = 0x02,
RADEON_INIT_R200_CP = 0x03,
} func;
unsigned long sarea_priv_offset;
int is_pci;
......@@ -458,6 +500,9 @@ typedef struct drm_radeon_indirect {
* client any other way.
*/
#define RADEON_PARAM_AGP_BUFFER_OFFSET 0x1
#define RADEON_PARAM_LAST_FRAME 0x2
#define RADEON_PARAM_LAST_DISPATCH 0x3
#define RADEON_PARAM_LAST_CLEAR 0x4
typedef struct drm_radeon_getparam {
int param;
......
drivers/char/drm/radeon_drv.c
View file @ 0fa821d8
......@@ -35,49 +35,6 @@
#include "radeon_drv.h"
#include "ati_pcigart.h"
#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
#define DRIVER_NAME "radeon"
#define DRIVER_DESC "ATI Radeon"
#define DRIVER_DATE "20020611"
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 3
#define DRIVER_PATCHLEVEL 1
/* Interface history:
*
* 1.1 - ??
* 1.2 - Add vertex2 ioctl (keith)
* - Add stencil capability to clear ioctl (gareth, keith)
* - Increase MAX_TEXTURE_LEVELS (brian)
* 1.3 - Add cmdbuf ioctl (keith)
* - Add support for new radeon packets (keith)
* - Add getparam ioctl (keith)
* - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 },
#include "drm_agpsupport.h"
#include "drm_auth.h"
#include "drm_bufs.h"
......@@ -85,26 +42,6 @@
#include "drm_dma.h"
#include "drm_drawable.h"
#include "drm_drv.h"
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* JH- We have to hand expand the string ourselves because of the cpp. If
* anyone can think of a way that we can fit into the __setup macro without
* changing it, then please send the solution my way.
*/
static int __init radeon_options( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", radeon_options );
#endif
#include "drm_fops.h"
#include "drm_init.h"
#include "drm_ioctl.h"
......
drivers/char/drm/radeon_drv.h
View file @ 0fa821d8
......@@ -31,8 +31,8 @@
#ifndef __RADEON_DRV_H__
#define __RADEON_DRV_H__
#define GET_RING_HEAD(ring) readl( (volatile u32 *) (ring)->head )
#define SET_RING_HEAD(ring,val) writel( (val), (volatile u32 *) (ring)->head )
#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head )
#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head , (val))
typedef struct drm_radeon_freelist {
unsigned int age;
......@@ -78,12 +78,25 @@ typedef struct drm_radeon_private {
volatile u32 *scratch;
int usec_timeout;
int is_r200;
int is_pci;
unsigned long phys_pci_gart;
dma_addr_t bus_pci_gart;
atomic_t idle_count;
struct {
u32 boxes;
int freelist_timeouts;
int freelist_loops;
int requested_bufs;
int last_frame_reads;
int last_clear_reads;
int clears;
int texture_uploads;
} stats;
int do_boxes;
int page_flipping;
int current_page;
u32 crtc_offset;
......@@ -119,63 +132,44 @@ typedef struct drm_radeon_buf_priv {
} drm_radeon_buf_priv_t;
/* radeon_cp.c */
extern int radeon_cp_init( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_start( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_stop( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_idle( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_engine_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_fullscreen( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_buffers( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_init( DRM_IOCTL_ARGS );
extern int radeon_cp_start( DRM_IOCTL_ARGS );
extern int radeon_cp_stop( DRM_IOCTL_ARGS );
extern int radeon_cp_reset( DRM_IOCTL_ARGS );
extern int radeon_cp_idle( DRM_IOCTL_ARGS );
extern int radeon_engine_reset( DRM_IOCTL_ARGS );
extern int radeon_fullscreen( DRM_IOCTL_ARGS );
extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
extern void radeon_freelist_reset( drm_device_t *dev );
extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
static inline void
radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring )
{
ring->space = (GET_RING_HEAD(ring) - ring->tail) * sizeof(u32);
if ( ring->space <= 0 )
ring->space += ring->size;
}
extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
extern int radeon_do_cleanup_cp( drm_device_t *dev );
extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
/* radeon_state.c */
extern int radeon_cp_clear( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_swap( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_vertex( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_indices( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_texture( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_stipple( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_indirect( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_vertex2( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_getparam( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_flip( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_clear( DRM_IOCTL_ARGS );
extern int radeon_cp_swap( DRM_IOCTL_ARGS );
extern int radeon_cp_vertex( DRM_IOCTL_ARGS );
extern int radeon_cp_indices( DRM_IOCTL_ARGS );
extern int radeon_cp_texture( DRM_IOCTL_ARGS );
extern int radeon_cp_stipple( DRM_IOCTL_ARGS );
extern int radeon_cp_indirect( DRM_IOCTL_ARGS );
extern int radeon_cp_vertex2( DRM_IOCTL_ARGS );
extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS );
extern int radeon_cp_getparam( DRM_IOCTL_ARGS );
extern int radeon_cp_flip( DRM_IOCTL_ARGS );
/* Flags for stats.boxes
*/
#define RADEON_BOX_DMA_IDLE 0x1
#define RADEON_BOX_RING_FULL 0x2
#define RADEON_BOX_FLIP 0x4
#define RADEON_BOX_WAIT_IDLE 0x8
#define RADEON_BOX_TEXTURE_LOAD 0x10
......@@ -296,6 +290,7 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp,
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
#define RADEON_RB3D_DEPTHPITCH 0x1c28
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
#define RADEON_RB3D_ZCACHE_MODE 0x3250
......@@ -527,6 +522,62 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp,
#define RADEON_TXFORMAT_ARGB8888 6
#define RADEON_TXFORMAT_RGBA8888 7
#define R200_PP_TXCBLEND_0 0x2f00
#define R200_PP_TXCBLEND_1 0x2f10
#define R200_PP_TXCBLEND_2 0x2f20
#define R200_PP_TXCBLEND_3 0x2f30
#define R200_PP_TXCBLEND_4 0x2f40
#define R200_PP_TXCBLEND_5 0x2f50
#define R200_PP_TXCBLEND_6 0x2f60
#define R200_PP_TXCBLEND_7 0x2f70
#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
#define R200_PP_TFACTOR_0 0x2ee0
#define R200_SE_VTX_FMT_0 0x2088
#define R200_SE_VAP_CNTL 0x2080
#define R200_SE_TCL_MATRIX_SEL_0 0x2230
#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
#define R200_PP_TXFILTER_5 0x2ca0
#define R200_PP_TXFILTER_4 0x2c80
#define R200_PP_TXFILTER_3 0x2c60
#define R200_PP_TXFILTER_2 0x2c40
#define R200_PP_TXFILTER_1 0x2c20
#define R200_PP_TXFILTER_0 0x2c00
#define R200_PP_TXOFFSET_5 0x2d78
#define R200_PP_TXOFFSET_4 0x2d60
#define R200_PP_TXOFFSET_3 0x2d48
#define R200_PP_TXOFFSET_2 0x2d30
#define R200_PP_TXOFFSET_1 0x2d18
#define R200_PP_TXOFFSET_0 0x2d00
#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
#define R200_SE_VTE_CNTL 0x20b0
#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
#define R200_PP_TAM_DEBUG3 0x2d9c
#define R200_PP_CNTL_X 0x2cc4
#define R200_SE_VAP_CNTL_STATUS 0x2140
#define R200_RE_SCISSOR_TL_0 0x1cd8
#define R200_RE_SCISSOR_TL_1 0x1ce0
#define R200_RE_SCISSOR_TL_2 0x1ce8
#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
#define R200_SE_VTX_STATE_CNTL 0x2180
#define R200_RE_POINTSIZE 0x2648
#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
#define R200_3D_DRAW_IMMD_2 0xC0003500
#define R200_SE_VTX_FMT_1 0x208c
#define R200_RE_CNTL 0x1c50
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
......@@ -544,11 +595,11 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp,
#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg)
#define RADEON_READ(reg) readl( (volatile u32 *) RADEON_ADDR(reg) )
#define RADEON_WRITE(reg,val) writel( (val), (volatile u32 *) RADEON_ADDR(reg) )
#define RADEON_READ(reg) DRM_READ32( (volatile u32 *) RADEON_ADDR(reg) )
#define RADEON_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) RADEON_ADDR(reg), (val) )
#define RADEON_READ8(reg) readb( (volatile u8 *) RADEON_ADDR(reg) )
#define RADEON_WRITE8(reg,val) writeb( (val), (volatile u8 *) RADEON_ADDR(reg) )
#define RADEON_READ8(reg) DRM_READ8( (volatile u8 *) RADEON_ADDR(reg) )
#define RADEON_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) RADEON_ADDR(reg), (val) )
#define RADEON_WRITE_PLL( addr, val ) \
do { \
......@@ -628,36 +679,22 @@ extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
#define LOCK_TEST_WITH_RETURN( dev ) \
do { \
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
dev->lock.pid != current->pid ) { \
DRM_ERROR( "%s called without lock held\n", \
__FUNCTION__ ); \
return -EINVAL; \
dev->lock.pid != DRM_CURRENTPID ) { \
DRM_ERROR( "%s called without lock held\n", __func__ ); \
return DRM_ERR(EINVAL); \
} \
} while (0)
/* Perfbox functionality only.
*/
#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
do { \
drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; \
if ( ring->space < ring->high_mark ) { \
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
radeon_update_ring_snapshot( ring ); \
if ( ring->space >= ring->high_mark ) \
goto __ring_space_done; \
udelay( 1 ); \
} \
DRM_ERROR( "ring space check from memory failed, reading register...\n" ); \
/* If ring space check fails from RAM, try reading the \
register directly */ \
ring->space = 4 * ( RADEON_READ( RADEON_CP_RB_RPTR ) - ring->tail ); \
if ( ring->space <= 0 ) \
ring->space += ring->size; \
if ( ring->space >= ring->high_mark ) \
goto __ring_space_done; \
\
DRM_ERROR( "ring space check failed!\n" ); \
return -EBUSY; \
if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
u32 head = GET_RING_HEAD(&dev_priv->ring); \
if (head == dev_priv->ring.tail) \
dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
} \
__ring_space_done: \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
......@@ -665,7 +702,7 @@ do { \
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret < 0 ) return __ret; \
if ( __ret ) return __ret; \
sarea_priv->last_dispatch = 0; \
radeon_freelist_reset( dev ); \
} \
......@@ -694,18 +731,18 @@ do { \
#if defined(__powerpc__)
#define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
#else
#define radeon_flush_write_combine() mb()
#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER()
#endif
#define RADEON_VERBOSE 0
#define RING_LOCALS int write, _nr; unsigned int mask; volatile u32 *ring;
#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
#define BEGIN_RING( n ) do { \
if ( RADEON_VERBOSE ) { \
DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
n, __FUNCTION__ ); \
n, __func__ ); \
} \
if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
COMMIT_RING(); \
......@@ -724,16 +761,15 @@ do { \
} \
if (((dev_priv->ring.tail + _nr) & mask) != write) { \
DRM_ERROR( \
"ADVANCE_RING(): mismatch: nr: %x write: %x\n", \
"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
((dev_priv->ring.tail + _nr) & mask), \
write); \
write, __LINE__); \
} else \
dev_priv->ring.tail = write; \
} while (0)
#define COMMIT_RING() do { \
radeon_flush_write_combine(); \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
#define COMMIT_RING() do { \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
} while (0)
#define OUT_RING( x ) do { \
......@@ -757,23 +793,21 @@ do { \
\
if (write + _size > mask) { \
int i = (mask+1) - write; \
if (__copy_from_user( (int *)(ring+write), \
if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
_tab, i*4 )) \
return -EFAULT; \
return DRM_ERR(EFAULT); \
write = 0; \
_size -= i; \
_tab += i; \
} \
\
if (_size && __copy_from_user( (int *)(ring+write), \
if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
_tab, _size*4 )) \
return -EFAULT; \
return DRM_ERR(EFAULT); \
\
write += _size; \
write &= mask; \
} while (0)
#define RADEON_PERFORMANCE_BOXES 0
#endif /* __RADEON_DRV_H__ */
drivers/char/drm/radeon_state.c
View file @ 0fa821d8
......@@ -27,20 +27,18 @@
* Kevin E. Martin <martin@valinux.com>
*/
#define __NO_VERSION__
#include "radeon.h"
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include <linux/delay.h>
/* ================================================================
* CP hardware state programming functions
*/
static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
drm_clip_rect_t *box )
{
RING_LOCALS;
......@@ -48,10 +46,12 @@ static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n",
box->x1, box->y1, box->x2, box->y2 );
BEGIN_RING( 3 );
OUT_RING( CP_PACKET3( RADEON_CNTL_SET_SCISSORS, 1 ));
BEGIN_RING( 4 );
OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
OUT_RING( (box->y1 << 16) | box->x1 );
OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/
OUT_RING( (box->y2 << 16) | box->x2 );
ADVANCE_RING();
}
......@@ -63,7 +63,7 @@ static void radeon_emit_state( drm_radeon_private_t *dev_priv,
unsigned int dirty )
{
RING_LOCALS;
DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
DRM_DEBUG( "dirty=0x%08x\n", dirty );
if ( dirty & RADEON_UPLOAD_CONTEXT ) {
BEGIN_RING( 14 );
......@@ -240,18 +240,50 @@ static struct {
{ RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
{ RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
{ RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
{ R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" },
{ R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
{ R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
{ R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
{ R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
{ R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
{ R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
{ R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
{ R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
{ R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
{ R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
{ R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
{ R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
{ R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
{ R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
{ R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
{ R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
{ R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
{ R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
{ R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
{ R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
{ R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
{ R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
{ R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
{ R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
{ R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
{ R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
{ R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
{ R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
{ R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
{ R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
{ R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
{ R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
{ R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
{ R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
{ R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
{ R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
{ R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
};
#if RADEON_PERFORMANCE_BOXES
/* ================================================================
* Performance monitoring functions
*/
......@@ -260,10 +292,12 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
int x, int y, int w, int h,
int r, int g, int b )
{
u32 pitch, offset;
u32 color;
RING_LOCALS;
x += dev_priv->sarea_priv->boxes[0].x1;
y += dev_priv->sarea_priv->boxes[0].y1;
switch ( dev_priv->color_fmt ) {
case RADEON_COLOR_FORMAT_RGB565:
color = (((r & 0xf8) << 8) |
......@@ -276,8 +310,11 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
break;
}
offset = dev_priv->back_offset;
pitch = dev_priv->back_pitch >> 3;
BEGIN_RING( 4 );
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
OUT_RING( 0xffffffff );
ADVANCE_RING();
BEGIN_RING( 6 );
......@@ -289,7 +326,12 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
RADEON_ROP3_P |
RADEON_GMC_CLR_CMP_CNTL_DIS );
OUT_RING( (pitch << 22) | (offset >> 5) );
if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
OUT_RING( dev_priv->front_pitch_offset );
} else {
OUT_RING( dev_priv->back_pitch_offset );
}
OUT_RING( color );
OUT_RING( (x << 16) | y );
......@@ -300,16 +342,57 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
{
if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
} else {
atomic_set( &dev_priv->idle_count, 0 );
/* Collapse various things into a wait flag -- trying to
* guess if userspase slept -- better just to have them tell us.
*/
if (dev_priv->stats.last_frame_reads > 1 ||
dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
}
}
#endif
if (dev_priv->stats.freelist_loops) {
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
}
/* Purple box for page flipping
*/
if ( dev_priv->stats.boxes & RADEON_BOX_FLIP )
radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 );
/* Red box if we have to wait for idle at any point
*/
if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE )
radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 );
/* Blue box: lost context?
*/
/* Yellow box for texture swaps
*/
if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD )
radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 );
/* Green box if hardware never idles (as far as we can tell)
*/
if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) )
radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
/* Draw bars indicating number of buffers allocated
* (not a great measure, easily confused)
*/
if (dev_priv->stats.requested_bufs) {
if (dev_priv->stats.requested_bufs > 100)
dev_priv->stats.requested_bufs = 100;
radeon_clear_box( dev_priv, 4, 16,
dev_priv->stats.requested_bufs, 4,
196, 128, 128 );
}
memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) );
}
/* ================================================================
* CP command dispatch functions
*/
......@@ -327,7 +410,10 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
int i;
RING_LOCALS;
DRM_DEBUG( __FUNCTION__": flags = 0x%x\n", flags );
DRM_DEBUG( "flags = 0x%x\n", flags );
dev_priv->stats.clears++;
if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
unsigned int tmp = flags;
......@@ -337,120 +423,251 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT;
}
if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
BEGIN_RING( 4 );
/* Ensure the 3D stream is idle before doing a
* 2D fill to clear the front or back buffer.
*/
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
OUT_RING( clear->color_mask );
ADVANCE_RING();
/* Make sure we restore the 3D state next time.
*/
dev_priv->sarea_priv->ctx_owner = 0;
for ( i = 0 ; i < nbox ; i++ ) {
int x = pbox[i].x1;
int y = pbox[i].y1;
int w = pbox[i].x2 - x;
int h = pbox[i].y2 - y;
DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
x, y, w, h, flags );
if ( flags & RADEON_FRONT ) {
BEGIN_RING( 6 );
OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
(dev_priv->color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P |
RADEON_GMC_CLR_CMP_CNTL_DIS );
OUT_RING( dev_priv->front_pitch_offset );
OUT_RING( clear->clear_color );
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
if ( flags & RADEON_BACK ) {
BEGIN_RING( 6 );
OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
(dev_priv->color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P |
RADEON_GMC_CLR_CMP_CNTL_DIS );
OUT_RING( dev_priv->back_pitch_offset );
OUT_RING( clear->clear_color );
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
}
}
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
* make sure the 3D engine is configured correctly.
*/
if ( flags & (RADEON_DEPTH | RADEON_STENCIL) ) {
rb3d_cntl = depth_clear->rb3d_cntl;
if ( dev_priv->is_r200 &&
(flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
if ( flags & RADEON_DEPTH ) {
rb3d_cntl |= RADEON_Z_ENABLE;
} else {
rb3d_cntl &= ~RADEON_Z_ENABLE;
}
int tempPP_CNTL;
int tempRE_CNTL;
int tempRB3D_CNTL;
int tempRB3D_ZSTENCILCNTL;
int tempRB3D_STENCILREFMASK;
int tempRB3D_PLANEMASK;
int tempSE_CNTL;
int tempSE_VTE_CNTL;
int tempSE_VTX_FMT_0;
int tempSE_VTX_FMT_1;
int tempSE_VAP_CNTL;
int tempRE_AUX_SCISSOR_CNTL;
if ( flags & RADEON_STENCIL ) {
rb3d_cntl |= RADEON_STENCIL_ENABLE;
rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
} else {
rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
rb3d_stencilrefmask = 0x00000000;
}
}
tempPP_CNTL = 0;
tempRE_CNTL = 0;
for ( i = 0 ; i < nbox ; i++ ) {
int x = pbox[i].x1;
int y = pbox[i].y1;
int w = pbox[i].x2 - x;
int h = pbox[i].y2 - y;
tempRB3D_CNTL = depth_clear->rb3d_cntl;
tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
x, y, w, h, flags );
tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
tempRB3D_STENCILREFMASK = 0x0;
if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
BEGIN_RING( 4 );
tempSE_CNTL = depth_clear->se_cntl;
/* Ensure the 3D stream is idle before doing a
* 2D fill to clear the front or back buffer.
*/
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
OUT_RING( clear->color_mask );
ADVANCE_RING();
/* Disable TCL */
/* Make sure we restore the 3D state next time.
*/
dev_priv->sarea_priv->ctx_owner = 0;
}
tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
(0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
if ( flags & RADEON_FRONT ) {
BEGIN_RING( 6 );
tempRB3D_PLANEMASK = 0x0;
OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
(dev_priv->color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P |
RADEON_GMC_CLR_CMP_CNTL_DIS );
tempRE_AUX_SCISSOR_CNTL = 0x0;
OUT_RING( dev_priv->front_pitch_offset );
OUT_RING( clear->clear_color );
tempSE_VTE_CNTL =
SE_VTE_CNTL__VTX_XY_FMT_MASK |
SE_VTE_CNTL__VTX_Z_FMT_MASK;
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
/* Vertex format (X, Y, Z, W)*/
tempSE_VTX_FMT_0 =
SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
tempSE_VTX_FMT_1 = 0x0;
ADVANCE_RING();
/*
* Depth buffer specific enables
*/
if (flags & RADEON_DEPTH) {
/* Enable depth buffer */
tempRB3D_CNTL |= RADEON_Z_ENABLE;
} else {
/* Disable depth buffer */
tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
}
if ( flags & RADEON_BACK ) {
BEGIN_RING( 6 );
/*
* Stencil buffer specific enables
*/
if ( flags & RADEON_STENCIL ) {
tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
tempRB3D_STENCILREFMASK = clear->depth_mask;
} else {
tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
tempRB3D_STENCILREFMASK = 0x00000000;
}
OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
(dev_priv->color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P |
RADEON_GMC_CLR_CMP_CNTL_DIS );
BEGIN_RING( 26 );
RADEON_WAIT_UNTIL_2D_IDLE();
OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL );
OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL );
OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL );
OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
tempRB3D_ZSTENCILCNTL );
OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
tempRB3D_STENCILREFMASK );
OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK );
OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL );
OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL );
OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 );
OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 );
OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
tempRE_AUX_SCISSOR_CNTL );
ADVANCE_RING();
OUT_RING( dev_priv->back_pitch_offset );
OUT_RING( clear->clear_color );
/* Make sure we restore the 3D state next time.
*/
dev_priv->sarea_priv->ctx_owner = 0;
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
for ( i = 0 ; i < nbox ; i++ ) {
/* Funny that this should be required --
* sets top-left?
*/
radeon_emit_clip_rect( dev_priv,
&sarea_priv->boxes[i] );
BEGIN_RING( 14 );
OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) );
OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
RADEON_PRIM_WALK_RING |
(3 << RADEON_NUM_VERTICES_SHIFT)) );
OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
OUT_RING( 0x3f800000 );
OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
OUT_RING( 0x3f800000 );
OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
OUT_RING( 0x3f800000 );
ADVANCE_RING();
}
}
else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
if ( flags & (RADEON_DEPTH | RADEON_STENCIL) ) {
rb3d_cntl = depth_clear->rb3d_cntl;
radeon_emit_clip_rect( dev_priv,
&sarea_priv->boxes[i] );
if ( flags & RADEON_DEPTH ) {
rb3d_cntl |= RADEON_Z_ENABLE;
} else {
rb3d_cntl &= ~RADEON_Z_ENABLE;
}
BEGIN_RING( 28 );
if ( flags & RADEON_STENCIL ) {
rb3d_cntl |= RADEON_STENCIL_ENABLE;
rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
} else {
rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
rb3d_stencilrefmask = 0x00000000;
}
RADEON_WAIT_UNTIL_2D_IDLE();
BEGIN_RING( 13 );
RADEON_WAIT_UNTIL_2D_IDLE();
OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
OUT_RING( 0x00000000 );
OUT_RING( rb3d_cntl );
OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
OUT_RING( 0x00000000 );
OUT_RING( rb3d_cntl );
OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
depth_clear->rb3d_zstencilcntl );
OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
rb3d_stencilrefmask );
OUT_RING_REG( RADEON_RB3D_PLANEMASK,
0x00000000 );
OUT_RING_REG( RADEON_SE_CNTL,
depth_clear->se_cntl );
ADVANCE_RING();
OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
depth_clear->rb3d_zstencilcntl );
OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
rb3d_stencilrefmask );
OUT_RING_REG( RADEON_RB3D_PLANEMASK,
0x00000000 );
OUT_RING_REG( RADEON_SE_CNTL,
depth_clear->se_cntl );
/* Make sure we restore the 3D state next time.
*/
dev_priv->sarea_priv->ctx_owner = 0;
/* Radeon 7500 doesn't like vertices without
* color.
for ( i = 0 ; i < nbox ; i++ ) {
/* Funny that this should be required --
* sets top-left?
*/
radeon_emit_clip_rect( dev_priv,
&sarea_priv->boxes[i] );
BEGIN_RING( 15 );
OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) );
OUT_RING( RADEON_VTX_Z_PRESENT |
RADEON_VTX_PKCOLOR_PRESENT);
......@@ -460,6 +677,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
RADEON_VTX_FMT_RADEON_MODE |
(3 << RADEON_NUM_VERTICES_SHIFT)) );
OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
......@@ -476,10 +694,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
OUT_RING( 0x0 );
ADVANCE_RING();
/* Make sure we restore the 3D state next time.
*/
dev_priv->sarea_priv->ctx_owner = 0;
}
}
......@@ -505,13 +719,14 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
drm_clip_rect_t *pbox = sarea_priv->boxes;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
#if RADEON_PERFORMANCE_BOXES
/* Do some trivial performance monitoring...
*/
radeon_cp_performance_boxes( dev_priv );
#endif
if (dev_priv->do_boxes)
radeon_cp_performance_boxes( dev_priv );
/* Wait for the 3D stream to idle before dispatching the bitblt.
* This will prevent data corruption between the two streams.
......@@ -580,13 +795,17 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
{
drm_radeon_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
__FUNCTION__,
dev_priv->current_page,
dev_priv->sarea_priv->pfCurrentPage);
#if RADEON_PERFORMANCE_BOXES
/* Do some trivial performance monitoring...
*/
radeon_cp_performance_boxes( dev_priv );
#endif
if (dev_priv->do_boxes) {
dev_priv->stats.boxes |= RADEON_BOX_FLIP;
radeon_cp_performance_boxes( dev_priv );
}
BEGIN_RING( 4 );
......@@ -668,8 +887,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
int i = 0;
RING_LOCALS;
DRM_DEBUG("%s: hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
__FUNCTION__,
DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
prim->prim,
prim->vc_format,
prim->start,
......@@ -685,7 +903,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
do {
/* Emit the next cliprect */
if ( i < nbox ) {
if (__copy_from_user( &box, &boxes[i], sizeof(box) ))
if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
return;
radeon_emit_clip_rect( dev_priv, &box );
......@@ -780,8 +998,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
int count = (prim->finish - start) / sizeof(u16);
DRM_DEBUG("%s: hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
__FUNCTION__,
DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
prim->prim,
prim->vc_format,
prim->start,
......@@ -819,7 +1036,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
do {
if ( i < nbox ) {
if (__copy_from_user( &box, &boxes[i], sizeof(box) ))
if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
return;
radeon_emit_clip_rect( dev_priv, &box );
......@@ -844,16 +1061,18 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
drm_buf_t *buf;
u32 format;
u32 *buffer;
u8 *data;
const u8 *data;
int size, dwords, tex_width, blit_width;
u32 y, height;
int ret = 0, i;
RING_LOCALS;
dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
/* FIXME: Be smarter about this...
*/
buf = radeon_freelist_get( dev );
if ( !buf ) return -EAGAIN;
if ( !buf ) return DRM_ERR(EAGAIN);
DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
tex->offset >> 10, tex->pitch, tex->format,
......@@ -886,7 +1105,7 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
break;
default:
DRM_ERROR( "invalid texture format %d\n", tex->format );
return -EINVAL;
return DRM_ERR(EINVAL);
}
DRM_DEBUG( " tex=%dx%d blit=%d\n",
......@@ -918,13 +1137,13 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
*/
y = image->y;
height = image->height;
data = (u8 *)image->data;
data = (const u8 *)image->data;
size = height * blit_width;
if ( size > RADEON_MAX_TEXTURE_SIZE ) {
/* Texture image is too large, do a multipass upload */
ret = -EAGAIN;
ret = DRM_ERR(EAGAIN);
/* Adjust the blit size to fit the indirect buffer */
height = RADEON_MAX_TEXTURE_SIZE / blit_width;
......@@ -933,11 +1152,11 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
/* Update the input parameters for next time */
image->y += height;
image->height -= height;
image->data = (char *)image->data + size;
image->data = (const char *)image->data + size;
if ( copy_to_user( tex->image, image, sizeof(*image) ) ) {
if ( DRM_COPY_TO_USER( tex->image, image, sizeof(*image) ) ) {
DRM_ERROR( "EFAULT on tex->image\n" );
return -EFAULT;
return DRM_ERR(EFAULT);
}
} else if ( size < 4 && size > 0 ) {
size = 4;
......@@ -972,9 +1191,9 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
/* Texture image width is larger than the minimum, so we
* can upload it directly.
*/
if ( copy_from_user( buffer, data, dwords * sizeof(u32) ) ) {
if ( DRM_COPY_FROM_USER( buffer, data, dwords * sizeof(u32) ) ) {
DRM_ERROR( "EFAULT on data, %d dwords\n", dwords );
return -EFAULT;
return DRM_ERR(EFAULT);
}
} else {
/* Texture image width is less than the minimum, so we
......@@ -982,17 +1201,17 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
* width.
*/
for ( i = 0 ; i < tex->height ; i++ ) {
if ( copy_from_user( buffer, data, tex_width ) ) {
if ( DRM_COPY_FROM_USER( buffer, data, tex_width ) ) {
DRM_ERROR( "EFAULT on pad, %d bytes\n",
tex_width );
return -EFAULT;
return DRM_ERR(EFAULT);
}
buffer += 8;
data += tex_width;
}
}
buf->pid = current->pid;
buf->pid = DRM_CURRENTPID;
buf->used = (dwords + 8) * sizeof(u32);
radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
......@@ -1017,7 +1236,7 @@ static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
drm_radeon_private_t *dev_priv = dev->dev_private;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
BEGIN_RING( 35 );
......@@ -1037,31 +1256,28 @@ static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
* IOCTL functions
*/
int radeon_cp_clear( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_clear( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_radeon_clear_t clear;
drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &clear, (drm_radeon_clear_t *)arg,
sizeof(clear) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t *)data,
sizeof(clear) );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
if ( copy_from_user( &depth_boxes, clear.depth_boxes,
if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes,
sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
return -EFAULT;
return DRM_ERR(EFAULT);
radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
......@@ -1076,15 +1292,17 @@ int radeon_cp_clear( struct inode *inode, struct file *filp,
static int radeon_do_init_pageflip( drm_device_t *dev )
{
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
RING_LOCALS;
DRM_DEBUG( "\n" );
dev_priv->crtc_offset = RADEON_READ( RADEON_CRTC_OFFSET );
dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset );
RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL,
dev_priv->crtc_offset_cntl |
RADEON_CRTC_OFFSET_FLIP_CNTL );
BEGIN_RING( 4 );
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
OUT_RING( dev_priv->crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL );
ADVANCE_RING();
dev_priv->page_flipping = 1;
dev_priv->current_page = 0;
......@@ -1096,28 +1314,27 @@ static int radeon_do_init_pageflip( drm_device_t *dev )
int radeon_do_cleanup_pageflip( drm_device_t *dev )
{
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->crtc_offset );
RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
if (dev_priv->current_page != 0)
radeon_cp_dispatch_flip( dev );
/* FIXME: If the X server changes screen resolution, it
* clobbers the value of RADEON_CRTC_OFFSET_CNTL, above,
* leading to a flashing efect.
*/
dev_priv->page_flipping = 0;
dev_priv->current_page = 0;
dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
return 0;
}
/* Swapping and flipping are different operations, need different ioctls.
* They can & should be intermixed to support multiple 3d windows.
*/
int radeon_cp_flip( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_flip( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
......@@ -1132,14 +1349,12 @@ int radeon_cp_flip( struct inode *inode, struct file *filp,
return 0;
}
int radeon_cp_swap( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_swap( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
DRM_DEBUG( "%s\n", __FUNCTION__ );
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev );
......@@ -1155,11 +1370,9 @@ int radeon_cp_swap( struct inode *inode, struct file *filp,
return 0;
}
int radeon_cp_vertex( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_vertex( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_device_dma_t *dma = dev->dma;
......@@ -1170,27 +1383,26 @@ int radeon_cp_vertex( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg,
sizeof(vertex) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t *)data,
sizeof(vertex) );
DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
__FUNCTION__, current->pid,
DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
DRM_CURRENTPID,
vertex.idx, vertex.count, vertex.discard );
if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
vertex.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( vertex.prim < 0 ||
vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
DRM_ERROR( "buffer prim %d\n", vertex.prim );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1198,14 +1410,14 @@ int radeon_cp_vertex( struct inode *inode, struct file *filp,
buf = dma->buflist[vertex.idx];
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
/* Build up a prim_t record:
......@@ -1244,11 +1456,9 @@ int radeon_cp_vertex( struct inode *inode, struct file *filp,
return 0;
}
int radeon_cp_indices( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_indices( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_device_dma_t *dma = dev->dma;
......@@ -1260,27 +1470,26 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &elts, (drm_radeon_indices_t *)arg,
sizeof(elts) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t *)data,
sizeof(elts) );
DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n",
__FUNCTION__, current->pid,
DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n",
DRM_CURRENTPID,
elts.idx, elts.start, elts.end, elts.discard );
if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
elts.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( elts.prim < 0 ||
elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
DRM_ERROR( "buffer prim %d\n", elts.prim );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1288,14 +1497,14 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
buf = dma->buflist[elts.idx];
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", elts.idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
count = (elts.end - elts.start) / sizeof(u16);
......@@ -1303,11 +1512,11 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
if ( elts.start & 0x7 ) {
DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( elts.start < buf->used ) {
DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
return -EINVAL;
return DRM_ERR(EINVAL);
}
buf->used = elts.end;
......@@ -1345,11 +1554,9 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
return 0;
}
int radeon_cp_texture( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_texture( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_texture_t tex;
drm_radeon_tex_image_t image;
......@@ -1357,18 +1564,17 @@ int radeon_cp_texture( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &tex, (drm_radeon_texture_t *)arg, sizeof(tex) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t *)data, sizeof(tex) );
if ( tex.image == NULL ) {
DRM_ERROR( "null texture image!\n" );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &image,
if ( DRM_COPY_FROM_USER( &image,
(drm_radeon_tex_image_t *)tex.image,
sizeof(image) ) )
return -EFAULT;
return DRM_ERR(EFAULT);
RING_SPACE_TEST_WITH_RETURN( dev_priv );
VB_AGE_TEST_WITH_RETURN( dev_priv );
......@@ -1379,23 +1585,20 @@ int radeon_cp_texture( struct inode *inode, struct file *filp,
return ret;
}
int radeon_cp_stipple( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_stipple( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_stipple_t stipple;
u32 mask[32];
LOCK_TEST_WITH_RETURN( dev );
if ( copy_from_user( &stipple, (drm_radeon_stipple_t *)arg,
sizeof(stipple) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t *)data,
sizeof(stipple) );
if ( copy_from_user( &mask, stipple.mask, 32 * sizeof(u32) ) )
return -EFAULT;
if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) )
return DRM_ERR(EFAULT);
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1405,11 +1608,9 @@ int radeon_cp_stipple( struct inode *inode, struct file *filp,
return 0;
}
int radeon_cp_indirect( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_indirect( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
......@@ -1419,13 +1620,12 @@ int radeon_cp_indirect( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &indirect, (drm_radeon_indirect_t *)arg,
sizeof(indirect) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t *)data,
sizeof(indirect) );
DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
indirect.idx, indirect.start,
......@@ -1434,25 +1634,25 @@ int radeon_cp_indirect( struct inode *inode, struct file *filp,
if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
indirect.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
buf = dma->buflist[indirect.idx];
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( indirect.start < buf->used ) {
DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
indirect.start, buf->used );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1483,11 +1683,9 @@ int radeon_cp_indirect( struct inode *inode, struct file *filp,
return 0;
}
int radeon_cp_vertex2( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_vertex2( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_device_dma_t *dma = dev->dma;
......@@ -1499,21 +1697,21 @@ int radeon_cp_vertex2( struct inode *inode, struct file *filp,
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg,
sizeof(vertex) ) )
return -EFAULT;
DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t *)data,
sizeof(vertex) );
DRM_DEBUG( __FUNCTION__": pid=%d index=%d discard=%d\n",
current->pid, vertex.idx, vertex.discard );
DRM_DEBUG( "pid=%d index=%d discard=%d\n",
DRM_CURRENTPID,
vertex.idx, vertex.discard );
if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
vertex.idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
......@@ -1521,34 +1719,34 @@ int radeon_cp_vertex2( struct inode *inode, struct file *filp,
buf = dma->buflist[vertex.idx];
if ( buf->pid != current->pid ) {
if ( buf->pid != DRM_CURRENTPID ) {
DRM_ERROR( "process %d using buffer owned by %d\n",
current->pid, buf->pid );
return -EINVAL;
DRM_CURRENTPID, buf->pid );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
return -EINVAL;
return DRM_ERR(EINVAL);
}
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
return -EINVAL;
return DRM_ERR(EINVAL);
for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
drm_radeon_prim_t prim;
drm_radeon_tcl_prim_t tclprim;
if ( copy_from_user( &prim, &vertex.prim[i], sizeof(prim) ) )
return -EFAULT;
if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) )
return DRM_ERR(EFAULT);
if ( prim.stateidx != laststate ) {
drm_radeon_state_t state;
if ( copy_from_user( &state,
if ( DRM_COPY_FROM_USER( &state,
&vertex.state[prim.stateidx],
sizeof(state) ) )
return -EFAULT;
return DRM_ERR(EFAULT);
radeon_emit_state2( dev_priv, &state );
......@@ -1601,7 +1799,7 @@ static int radeon_emit_packets(
RING_LOCALS;
if (sz * sizeof(int) > cmdbuf->bufsz)
return -EINVAL;
return DRM_ERR(EINVAL);
BEGIN_RING(sz+1);
OUT_RING( CP_PACKET0( reg, (sz-1) ) );
......@@ -1613,7 +1811,7 @@ static int radeon_emit_packets(
return 0;
}
static inline int radeon_emit_scalars(
static __inline__ int radeon_emit_scalars(
drm_radeon_private_t *dev_priv,
drm_radeon_cmd_header_t header,
drm_radeon_cmd_buffer_t *cmdbuf )
......@@ -1635,7 +1833,31 @@ static inline int radeon_emit_scalars(
return 0;
}
static inline int radeon_emit_vectors(
/* God this is ugly
*/
static __inline__ int radeon_emit_scalars2(
drm_radeon_private_t *dev_priv,
drm_radeon_cmd_header_t header,
drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
int start = ((unsigned int)header.scalars.offset) + 0x100;
int stride = header.scalars.stride;
RING_LOCALS;
BEGIN_RING( 3+sz );
OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
OUT_RING_USER_TABLE( data, sz );
ADVANCE_RING();
cmdbuf->buf += sz * sizeof(int);
cmdbuf->bufsz -= sz * sizeof(int);
return 0;
}
static __inline__ int radeon_emit_vectors(
drm_radeon_private_t *dev_priv,
drm_radeon_cmd_header_t header,
drm_radeon_cmd_buffer_t *cmdbuf )
......@@ -1668,16 +1890,16 @@ static int radeon_emit_packet3( drm_device_t *dev,
RING_LOCALS;
DRM_DEBUG("%s\n", __FUNCTION__);
DRM_DEBUG("\n");
if (__get_user( tmp, &cmd[0]))
return -EFAULT;
if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0]))
return DRM_ERR(EFAULT);
cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
cmdsz * 4 > cmdbuf->bufsz)
return -EINVAL;
return DRM_ERR(EINVAL);
BEGIN_RING( cmdsz );
OUT_RING_USER_TABLE( cmd, cmdsz );
......@@ -1690,7 +1912,8 @@ static int radeon_emit_packet3( drm_device_t *dev,
static int radeon_emit_packet3_cliprect( drm_device_t *dev,
drm_radeon_cmd_buffer_t *cmdbuf )
drm_radeon_cmd_buffer_t *cmdbuf,
int orig_nbox )
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_clip_rect_t box;
......@@ -1700,21 +1923,24 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
int i = 0;
RING_LOCALS;
DRM_DEBUG("%s\n", __FUNCTION__);
DRM_DEBUG("\n");
if (__get_user( tmp, &cmd[0]))
return -EFAULT;
if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0]))
return DRM_ERR(EFAULT);
cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
cmdsz * 4 > cmdbuf->bufsz)
return -EINVAL;
return DRM_ERR(EINVAL);
if (!orig_nbox)
goto out;
do {
if ( i < cmdbuf->nbox ) {
if (__copy_from_user( &box, &boxes[i], sizeof(box) ))
return -EFAULT;
if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
return DRM_ERR(EFAULT);
radeon_emit_clip_rect( dev_priv, &box );
}
......@@ -1727,6 +1953,7 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
if (cmdbuf->nbox == 1)
cmdbuf->nbox = 0;
out:
cmdbuf->buf += cmdsz * 4;
cmdbuf->bufsz -= cmdsz * 4;
return 0;
......@@ -1734,49 +1961,47 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf = 0;
int idx;
drm_radeon_cmd_buffer_t cmdbuf;
drm_radeon_cmd_header_t header;
int orig_nbox;
LOCK_TEST_WITH_RETURN( dev );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &cmdbuf, (drm_radeon_cmd_buffer_t *)arg,
sizeof(cmdbuf) ) ) {
DRM_ERROR("copy_from_user\n");
return -EFAULT;
}
DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t *)data,
sizeof(cmdbuf) );
DRM_DEBUG( __FUNCTION__": pid=%d\n", current->pid );
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
VB_AGE_TEST_WITH_RETURN( dev_priv );
if (verify_area( VERIFY_READ, cmdbuf.buf, cmdbuf.bufsz ))
return -EFAULT;
if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz ))
return DRM_ERR(EFAULT);
if (cmdbuf.nbox &&
verify_area( VERIFY_READ, cmdbuf.boxes,
DRM_VERIFYAREA_READ(cmdbuf.boxes,
cmdbuf.nbox * sizeof(drm_clip_rect_t)))
return -EFAULT;
return DRM_ERR(EFAULT);
orig_nbox = cmdbuf.nbox;
while ( cmdbuf.bufsz >= sizeof(header) ) {
if (__get_user( header.i, (int *)cmdbuf.buf )) {
if (DRM_GET_USER_UNCHECKED( header.i, (int *)cmdbuf.buf )) {
DRM_ERROR("__get_user %p\n", cmdbuf.buf);
return -EFAULT;
return DRM_ERR(EFAULT);
}
cmdbuf.buf += sizeof(header);
......@@ -1784,105 +2009,125 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
switch (header.header.cmd_type) {
case RADEON_CMD_PACKET:
DRM_DEBUG("RADEON_CMD_PACKET\n");
if (radeon_emit_packets( dev_priv, header, &cmdbuf )) {
DRM_ERROR("radeon_emit_packets failed\n");
return -EINVAL;
return DRM_ERR(EINVAL);
}
break;
case RADEON_CMD_SCALARS:
DRM_DEBUG("RADEON_CMD_SCALARS\n");
if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
DRM_ERROR("radeon_emit_scalars failed\n");
return -EINVAL;
return DRM_ERR(EINVAL);
}
break;
case RADEON_CMD_VECTORS:
DRM_DEBUG("RADEON_CMD_VECTORS\n");
if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
DRM_ERROR("radeon_emit_vectors failed\n");
return -EINVAL;
return DRM_ERR(EINVAL);
}
break;
case RADEON_CMD_DMA_DISCARD:
DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
idx = header.dma.buf_idx;
if ( idx < 0 || idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
idx, dma->buf_count - 1 );
return -EINVAL;
return DRM_ERR(EINVAL);
}
buf = dma->buflist[idx];
if ( buf->pid != current->pid || buf->pending ) {
if ( buf->pid != DRM_CURRENTPID || buf->pending ) {
DRM_ERROR( "bad buffer\n" );
return -EINVAL;
return DRM_ERR(EINVAL);
}
radeon_cp_discard_buffer( dev, buf );
break;
case RADEON_CMD_PACKET3:
DRM_DEBUG("RADEON_CMD_PACKET3\n");
if (radeon_emit_packet3( dev, &cmdbuf )) {
DRM_ERROR("radeon_emit_packet3 failed\n");
return -EINVAL;
return DRM_ERR(EINVAL);
}
break;
case RADEON_CMD_PACKET3_CLIP:
if (radeon_emit_packet3_cliprect( dev, &cmdbuf )) {
DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
if (radeon_emit_packet3_cliprect( dev, &cmdbuf, orig_nbox )) {
DRM_ERROR("radeon_emit_packet3_clip failed\n");
return -EINVAL;
return DRM_ERR(EINVAL);
}
break;
case RADEON_CMD_SCALARS2:
DRM_DEBUG("RADEON_CMD_SCALARS2\n");
if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
DRM_ERROR("radeon_emit_scalars2 failed\n");
return DRM_ERR(EINVAL);
}
break;
default:
DRM_ERROR("bad cmd_type %d at %p\n",
header.header.cmd_type,
cmdbuf.buf - sizeof(header));
return -EINVAL;
return DRM_ERR(EINVAL);
}
}
DRM_DEBUG("DONE\n");
COMMIT_RING();
return 0;
}
int radeon_cp_getparam( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg )
int radeon_cp_getparam( DRM_IOCTL_ARGS )
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_getparam_t param;
int value;
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return -EINVAL;
DRM_ERROR( "%s called with no initialization\n", __func__ );
return DRM_ERR(EINVAL);
}
if ( copy_from_user( &param, (drm_radeon_getparam_t *)arg,
sizeof(param) ) ) {
DRM_ERROR("copy_from_user\n");
return -EFAULT;
}
DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t *)data,
sizeof(param) );
DRM_DEBUG( __FUNCTION__": pid=%d\n", current->pid );
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
switch( param.param ) {
case RADEON_PARAM_AGP_BUFFER_OFFSET:
value = dev_priv->agp_buffers_offset;
break;
case RADEON_PARAM_LAST_FRAME:
dev_priv->stats.last_frame_reads++;
value = DRM_READ32(&dev_priv->scratch[0]);
break;
case RADEON_PARAM_LAST_DISPATCH:
value = DRM_READ32(&dev_priv->scratch[1]);
break;
case RADEON_PARAM_LAST_CLEAR:
dev_priv->stats.last_clear_reads++;
value = DRM_READ32(&dev_priv->scratch[2]);
break;
default:
return -EINVAL;
return DRM_ERR(EINVAL);
}
if ( copy_to_user( param.value, &value, sizeof(int) ) ) {
if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
DRM_ERROR( "copy_to_user\n" );
return -EFAULT;
return DRM_ERR(EFAULT);
}
return 0;
......
drivers/char/drm/sis.h
View file @ 0fa821d8
......@@ -42,6 +42,31 @@
#define __HAVE_MTRR 1
#define __HAVE_CTX_BITMAP 1
#define DRIVER_AUTHOR "SIS"
#define DRIVER_NAME "sis"
#define DRIVER_DESC "SIS 300/630/540"
#define DRIVER_DATE "20010503"
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(SIS_IOCTL_FB_ALLOC)] = { sis_fb_alloc, 1, 0 }, \
[DRM_IOCTL_NR(SIS_IOCTL_FB_FREE)] = { sis_fb_free, 1, 0 }, \
/* AGP Memory Management */ \
[DRM_IOCTL_NR(SIS_IOCTL_AGP_INIT)] = { sisp_agp_init, 1, 0 }, \
[DRM_IOCTL_NR(SIS_IOCTL_AGP_ALLOC)] = { sisp_agp_alloc, 1, 0 }, \
[DRM_IOCTL_NR(SIS_IOCTL_AGP_FREE)] = { sisp_agp_free, 1, 0 }
#if 0 /* these don't appear to be defined */
/* SIS Stereo */
[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { sis_control, 1, 1 },
[DRM_IOCTL_NR(SIS_IOCTL_FLIP)] = { sis_flip, 1, 1 },
[DRM_IOCTL_NR(SIS_IOCTL_FLIP_INIT)] = { sis_flip_init, 1, 1 },
[DRM_IOCTL_NR(SIS_IOCTL_FLIP_FINAL)] = { sis_flip_final, 1, 1 }
#endif
#define __HAVE_COUNTERS 5
/* Buffer customization:
*/
#define DRIVER_AGP_BUFFERS_MAP( dev ) \
......
drivers/char/drm/sis_drv.c
View file @ 0fa821d8
......@@ -31,31 +31,6 @@
#include "sis_drm.h"
#include "sis_drv.h"
#define DRIVER_AUTHOR "SIS"
#define DRIVER_NAME "sis"
#define DRIVER_DESC "SIS 300/630/540"
#define DRIVER_DATE "20010503"
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(SIS_IOCTL_FB_ALLOC)] = { sis_fb_alloc, 1, 0 }, \
[DRM_IOCTL_NR(SIS_IOCTL_FB_FREE)] = { sis_fb_free, 1, 0 }, \
/* AGP Memory Management */ \
[DRM_IOCTL_NR(SIS_IOCTL_AGP_INIT)] = { sisp_agp_init, 1, 0 }, \
[DRM_IOCTL_NR(SIS_IOCTL_AGP_ALLOC)] = { sisp_agp_alloc, 1, 0 }, \
[DRM_IOCTL_NR(SIS_IOCTL_AGP_FREE)] = { sisp_agp_free, 1, 0 }
#if 0 /* these don't appear to be defined */
/* SIS Stereo */
[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { sis_control, 1, 1 },
[DRM_IOCTL_NR(SIS_IOCTL_FLIP)] = { sis_flip, 1, 1 },
[DRM_IOCTL_NR(SIS_IOCTL_FLIP_INIT)] = { sis_flip_init, 1, 1 },
[DRM_IOCTL_NR(SIS_IOCTL_FLIP_FINAL)] = { sis_flip_final, 1, 1 }
#endif
#define __HAVE_COUNTERS 5
#include "drm_auth.h"
#include "drm_agpsupport.h"
#include "drm_bufs.h"
......
drivers/char/drm/tdfx_drv.c
View file @ 0fa821d8
......@@ -82,25 +82,6 @@ static drm_pci_list_t DRM(idlist)[] = {
#include "drm_drawable.h"
#include "drm_drv.h"
#ifndef MODULE
/* DRM(options) is called by the kernel to parse command-line options
* passed via the boot-loader (e.g., LILO). It calls the insmod option
* routine, drm_parse_drm.
*/
/* JH- We have to hand expand the string ourselves because of the cpp. If
* anyone can think of a way that we can fit into the __setup macro without
* changing it, then please send the solution my way.
*/
static int __init tdfx_options( char *str )
{
DRM(parse_options)( str );
return 1;
}
__setup( DRIVER_NAME "=", tdfx_options );
#endif
#include "drm_fops.h"
#include "drm_init.h"
#include "drm_ioctl.h"
......
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