Commit 0fd06c90 authored by Sujith's avatar Sujith Committed by John W. Linville

ath9k: Fix bug in disabling MIB counters

This patch fixes a bug in ANI, where the MIB counters were
being cleared before the stats were updated.
Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent edf7c060
...@@ -642,14 +642,13 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) ...@@ -642,14 +642,13 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
} }
/* Freeze the MIB counters, get the stats and then clear them */
void ath9k_hw_disable_mib_counters(struct ath_hw *ah) void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
{ {
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n");
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
REG_WRITE(ah, AR_FILT_OFDM, 0); REG_WRITE(ah, AR_FILT_OFDM, 0);
REG_WRITE(ah, AR_FILT_CCK, 0); REG_WRITE(ah, AR_FILT_CCK, 0);
} }
......
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