[PATCH] spelling fix accessable -> accessible

This provides the following spelling fix.

 accessable -> accessible

drivers/isdn/hardware/eicon/io.c

@@ -534,7 +534,7 @@ pcm_req (PISDN_ADAPTER IoAdapter, ENTITY *e)
   goto Trapped ;
  }
 /*
- * memory based shared ram is accessable from different
+ * memory based shared ram is accessible from different
  * processors without disturbing concurrent processes.
  */
  a->ram_out (a, &IoAdapter->pcm->rc, 0) ;

drivers/net/au1000_eth.c

@@ -465,7 +465,7 @@ static int __init mii_probe (struct net_device * dev)
 
 		mii_status = mdio_read(dev, phy_addr, MII_STATUS);
 		if (mii_status == 0xffff || mii_status == 0x0000)
-			/* the mii is not accessable, try next one */
+			/* the mii is not accessible, try next one */
 			continue;
 
 		phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0);

drivers/net/dgrs_plx9060.h

@@ -18,7 +18,7 @@
 #define	PCI_INT_LINE		0x3C
 
 /*
- *	Registers accessable directly from PCI and local side.
+ *	Registers accessible directly from PCI and local side.
  *	Offset is from PCI side.  Add PLX_LCL_OFFSET for local address.
  */
 #define	PLX_LCL_OFFSET	0x80	/* Offset of regs from local side */

drivers/net/sis900.c

@@ -526,7 +526,7 @@ static int __init sis900_mii_probe (struct net_device * net_dev)
 			mii_status = mdio_read(net_dev, phy_addr, MII_STATUS);
 
 		if (mii_status == 0xffff || mii_status == 0x0000)
-			/* the mii is not accessable, try next one */
+			/* the mii is not accessible, try next one */
 			continue;
 		
 		if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) == NULL) {

drivers/net/sk98lin/skge.c

@@ -2516,7 +2516,7 @@ if (pAC->RlmtNets == 1) {
 		/*
 		 * Do not set the Limit to 0, because this could cause
 		 * wrap around with ReQueue'ed buffers (a buffer could
-		 * be requeued in the same position, made accessable to
+		 * be requeued in the same position, made accessible to
 		 * the hardware, and the hardware could change its
 		 * contents!
 		 */

drivers/net/sk98lin/skgeinit.c

@@ -1781,7 +1781,7 @@ SK_IOC	IoC)		/* IO context */
  * Returns:
  *	0:	success
  *	1:	Number of MACs exceeds SK_MAX_MACS	( after level 1)
- *	2:	Adapter not present or not accessable
+ *	2:	Adapter not present or not accessible
  *	3:	Illegal initialization level
  *	4:	Initialization Level 1 Call missing
  *	5:	Unexpected PHY type detected
@@ -1808,7 +1808,7 @@ int		Level)		/* initialization level */
 		/* Initialization Level 1 */
 		RetVal = SkGeInit1(pAC, IoC);
 
-		/* Check if the adapter seems to be accessable */
+		/* Check if the adapter seems to be accessible */
 		SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);
 		SK_IN32(IoC, B2_IRQM_INI, &DWord);
 		SK_OUT32(IoC, B2_IRQM_INI, 0x00000000L);

drivers/net/skfp/pmf.c

@@ -122,7 +122,7 @@ static const struct s_p_tab {
 
 	/*
 	 * PRIVATE EXTENSIONS
-	 * only accessable locally to get/set passwd
+	 * only accessible locally to get/set passwd
 	 */
 	{ SMT_P10F0,AC_GR,	MOFFSA(fddiPRPMFPasswd),	"8"	} ,
 	{ SMT_P10F1,AC_GR,	MOFFSS(fddiPRPMFStation),	"8"	} ,
@@ -211,7 +211,7 @@ static const struct s_p_tab {
 
 	/*
 	 * PRIVATE EXTENSIONS
-	 * only accessable locally to get/set TMIN
+	 * only accessible locally to get/set TMIN
 	 */
 	{ SMT_P20F0,AC_NA						} ,
 	{ SMT_P20F1,AC_GR,	MOFFMS(fddiMACT_Min),		"lT"	} ,

drivers/s390/cio/chsc.c

@@ -486,7 +486,7 @@ do_process_crw(void *ignore)
 	case 2: /* i/o resource accessibiliy */
 		CIO_CRW_EVENT(4, "chsc_process_crw: "
 			      "channel subsystem reports some I/O "
-			      "devices may have become accessable\n");
+			      "devices may have become accessible\n");
 		pr_debug( KERN_DEBUG "Data received after sei: \n");
 		pr_debug( KERN_DEBUG "Validity flags: %x\n", sei_res->vf);
 

drivers/scsi/aic7xxx/aic79xx_osm.c

@@ -1826,7 +1826,7 @@ ahd_dmamem_alloc(struct ahd_softc *ahd, bus_dma_tag_t dmat, void** vaddr,
 	 * At least in 2.2.14, malloc is a slab allocator so all
 	 * allocations are aligned.  We assume for these kernel versions
 	 * that all allocations will be bellow 4Gig, physically contiguous,
-	 * and accessable via DMA by the controller.
+	 * and accessible via DMA by the controller.
 	 */
 	map = NULL; /* No additional information to store */
 	*vaddr = malloc(dmat->maxsize, M_DEVBUF, M_NOWAIT);

drivers/scsi/aic7xxx/aic7xxx_osm.c

@@ -1435,7 +1435,7 @@ ahc_dmamem_alloc(struct ahc_softc *ahc, bus_dma_tag_t dmat, void** vaddr,
 	 * At least in 2.2.14, malloc is a slab allocator so all
 	 * allocations are aligned.  We assume for these kernel versions
 	 * that all allocations will be bellow 4Gig, physically contiguous,
-	 * and accessable via DMA by the controller.
+	 * and accessible via DMA by the controller.
 	 */
 	map = NULL; /* No additional information to store */
 	*vaddr = malloc(dmat->maxsize, M_DEVBUF, M_NOWAIT);

drivers/scsi/psi_chip.h

@@ -108,7 +108,7 @@ typedef struct
 typedef struct
 	{
 	UCHAR		irq;			// interrupt request channel number
-	UCHAR		numDrives;		// Number of accessable drives
+	UCHAR		numDrives;		// Number of accessible drives
 	UCHAR		fastFormat;	 	// Boolean for fast format enable
 	}	CHIP_CONFIG_N;
 

include/asm-arm/arch-integrator/platform.h

@@ -466,7 +466,7 @@
 #define MAXSWINUM                       31
  
 /* ------------------------------------------------------------------------
- *  LED's - The header LED is not accessable via the uHAL API
+ *  LED's - The header LED is not accessible via the uHAL API
  * ------------------------------------------------------------------------
  * 
  */

include/asm-ia64/sn/pci/bridge.h

@@ -186,8 +186,8 @@ typedef volatile struct pic_widget_cfg_s {
 
 /*
  * BRIDGE, XBRIDGE, PIC register definitions.  NOTE: Prior to PIC, registers
- * were a 32bit quantity and double word aligned (and only accessable as a
- * 32bit word.  PIC registers are 64bits and accessable as words or double
+ * were a 32bit quantity and double word aligned (and only accessible as a
+ * 32bit word.  PIC registers are 64bits and accessible as words or double
  * words.  PIC registers that have valid bits (ie. not just reserved) in the
  * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit
  * bridgereg_t so we can access them both ways.

include/asm-ia64/sn/sn2/shub_md.h

@@ -133,7 +133,7 @@
 #define MD_DIMM_SIZE_MBYTES(_size, _2bk) (				 \
 	 	( (_size) == 7 ? 0 : ( 0x40L << (_size) ) << (_2bk)))  	 \
 
-/* The top 1/32 of each bank is directory memory, and not accessable
+/* The top 1/32 of each bank is directory memory, and not accessible
  * via normal reads and writes */
 #define MD_DIMM_USER_SIZE(_size)	((_size) * 31 / 32)
 

include/asm-parisc/pgtable.h

@@ -128,7 +128,7 @@ extern  void *vmalloc_start;
 #define _PAGE_PRESENT_BIT  22   /* (0x200) Software: translation valid */
 #define _PAGE_FLUSH_BIT    21   /* (0x400) Software: translation valid */
 				/*             for cache flushing only */
-#define _PAGE_USER_BIT     20   /* (0x800) Software: User accessable page */
+#define _PAGE_USER_BIT     20   /* (0x800) Software: User accessible page */
 
 /* N.B. The bits are defined in terms of a 32 bit word above, so the */
 /*      following macro is ok for both 32 and 64 bit.                */