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Merge branch 'completely-rework-mediatek-mt7530-binding' 

Arınç ÜNAL says:

====================
completely rework mediatek,mt7530 binding

This patch series brings complete rework of the mediatek,mt7530 binding.

The binding is checked with "make dt_binding_check
DT_SCHEMA_FILES=mediatek,mt7530.yaml".

If anyone knows the GIC bit for interrupt for multi-chip module MT7530 in
MT7623AI SoC, let me know. I'll add it to the examples.

If anyone got a Unielec U7623 or another MT7623AI board, please reach out.
====================

Link: https://lore.kernel.org/r/20220825082301.409450-1-arinc.unal@arinc9.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 146ecbac cd7e2b97
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Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
View file @ 1390d912
......@@ -4,67 +4,92 @@
$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT7530 Ethernet switch
title: Mediatek MT7530 and MT7531 Ethernet Switches
maintainers:
- Sean Wang <sean.wang@mediatek.com>
- Arınç ÜNAL <arinc.unal@arinc9.com>
- Landen Chao <Landen.Chao@mediatek.com>
- DENG Qingfang <dqfext@gmail.com>
- Sean Wang <sean.wang@mediatek.com>
description: |
Port 5 of mt7530 and mt7621 switch is muxed between:
1. GMAC5: GMAC5 can interface with another external MAC or PHY.
2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
of the SOC. Used in many setups where port 0/4 becomes the WAN port.
Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
connected to external component!
Port 5 modes/configurations:
1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
GMAC of the SOC.
In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
and RGMII delay.
3. Port 5 is muxed to GMAC5 and can interface to an external phy.
Port 5 becomes an extra switch port.
Only works on platform where external phy TX<->RX lines are swapped.
Like in the Ubiquiti ER-X-SFP.
4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
Currently a 2nd CPU port is not supported by DSA code.
Depending on how the external PHY is wired:
1. normal: The PHY can only connect to 2nd GMAC but not to the switch
2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
a ethernet port. But can't interface to the 2nd GMAC.
Based on the DT the port 5 mode is configured.
Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
phy-mode must be set, see also example 2 below!
* mt7621: phy-mode = "rgmii-txid";
* mt7623: phy-mode = "rgmii";
CPU-Ports need a phy-mode property:
Allowed values on mt7530 and mt7621:
- "rgmii"
- "trgmii"
On mt7531:
- "1000base-x"
- "2500base-x"
- "rgmii"
- "sgmii"
There are two versions of MT7530, standalone and in a multi-chip module.
MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs.
MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs
and the switch registers are directly mapped into SoC's memory map rather than
using MDIO. The DSA driver currently doesn't support this.
There is only the standalone version of MT7531.
Port 5 on MT7530 has got various ways of configuration.
For standalone MT7530:
- Port 5 can be used as a CPU port.
- PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC
which port 5 is wired to. Usually used for connecting the wan port
directly to the CPU to achieve 2 Gbps routing in total.
The driver looks up the reg on the ethernet-phy node which the phy-handle
property refers to on the gmac node to mux the specified phy.
The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
compatible string and the reg must be 1. So, for now, only gmac1 of an
MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
Check out example 5 for a similar configuration.
- Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
Check out example 7 for a similar configuration.
For multi-chip module MT7530:
- Port 5 can be used as a CPU port.
- PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC.
Usually used for connecting the wan port directly to the CPU to achieve 2
Gbps routing in total.
The driver looks up the reg on the ethernet-phy node which the phy-handle
property refers to on the gmac node to mux the specified phy.
For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
Check out example 5.
- In case of an external phy wired to gmac1 of the SoC, port 5 must not be
enabled.
In case of muxing PHY 0 or 4, the external phy must not be enabled.
For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
Check out example 6.
- Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave.
The external phy must be wired TX to TX to gmac1 of the SoC for this to
work. Ubiquiti EdgeRouter X SFP is wired this way.
Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX.
For the MT7621 SoCs, rgmii2 group must be claimed with gpio function.
Check out example 7.
properties:
compatible:
enum:
- mediatek,mt7530
- mediatek,mt7531
- mediatek,mt7621
oneOf:
- description:
Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC
const: mediatek,mt7530
- description:
Standalone MT7531
const: mediatek,mt7531
- description:
Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
const: mediatek,mt7621
reg:
maxItems: 1
......@@ -79,7 +104,7 @@ properties:
gpio-controller:
type: boolean
description:
if defined, MT7530's LED controller will run on GPIO mode.
If defined, MT7530's LED controller will run on GPIO mode.
"#interrupt-cells":
const: 1
......@@ -92,17 +117,21 @@ properties:
io-supply:
description:
Phandle to the regulator node necessary for the I/O power.
See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
for details for the regulator setup on these boards.
See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
details for the regulator setup on these boards.
mediatek,mcm:
type: boolean
description:
if defined, indicates that either MT7530 is the part on multi-chip
module belong to MT7623A has or the remotely standalone chip as the
function MT7623N reference board provided for.
Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530
switch is a part of the multi-chip module.
reset-gpios:
description:
GPIO to reset the switch. Use this if mediatek,mcm is not used.
This property is optional because some boards share the reset line with
other components which makes it impossible to probe the switch if the
reset line is used.
maxItems: 1
reset-names:
......@@ -110,8 +139,8 @@ properties:
resets:
description:
Phandle pointing to the system reset controller with line index for
the ethsys.
Phandle pointing to the system reset controller with line index for the
ethsys.
maxItems: 1
patternProperties:
......@@ -128,31 +157,97 @@ patternProperties:
properties:
reg:
description:
Port address described must be 5 or 6 for CPU port and from 0
to 5 for user ports.
Port address described must be 5 or 6 for CPU port and from 0 to 5
for user ports.
allOf:
- $ref: dsa-port.yaml#
- if:
properties:
label:
items:
- const: cpu
const: cpu
then:
required:
- reg
- phy-mode
properties:
reg:
enum:
- 5
- 6
required:
- compatible
- reg
$defs:
mt7530-dsa-port:
patternProperties:
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-9]+$":
if:
properties:
label:
const: cpu
then:
if:
properties:
reg:
const: 5
then:
properties:
phy-mode:
enum:
- gmii
- mii
- rgmii
else:
properties:
phy-mode:
enum:
- rgmii
- trgmii
mt7531-dsa-port:
patternProperties:
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-9]+$":
if:
properties:
label:
const: cpu
then:
if:
properties:
reg:
const: 5
then:
properties:
phy-mode:
enum:
- 1000base-x
- 2500base-x
- rgmii
- sgmii
else:
properties:
phy-mode:
enum:
- 1000base-x
- 2500base-x
- sgmii
allOf:
- $ref: "dsa.yaml#"
- $ref: dsa.yaml#
- if:
required:
- mediatek,mcm
then:
properties:
reset-gpios: false
required:
- resets
- reset-names
......@@ -163,52 +258,139 @@ allOf:
- if:
properties:
compatible:
items:
- const: mediatek,mt7530
const: mediatek,mt7530
then:
$ref: "#/$defs/mt7530-dsa-port"
required:
- core-supply
- io-supply
- if:
properties:
compatible:
const: mediatek,mt7531
then:
$ref: "#/$defs/mt7531-dsa-port"
properties:
mediatek,mcm: false
- if:
properties:
compatible:
const: mediatek,mt7621
then:
$ref: "#/$defs/mt7530-dsa-port"
required:
- mediatek,mcm
unevaluatedProperties: false
examples:
# Example 1: Standalone MT7530
- |
#include <dt-bindings/gpio/gpio.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7530";
reg = <0>;
reset-gpios = <&pio 33 0>;
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan1";
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan2";
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
# Example 2: MT7530 in MT7623AI SoC
- |
#include <dt-bindings/reset/mt2701-resets.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7530";
reg = <0>;
mediatek,mcm;
resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
reset-names = "mcm";
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
......@@ -219,85 +401,219 @@ examples:
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
# Example 3: Standalone MT7531
- |
//Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
ethernet {
mdio {
#address-cells = <1>;
#size-cells = <0>;
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
reset-gpios = <&pio 54 0>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
# Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7621";
reg = <0>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
gmac1: mac@1 {
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
# Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
ethernet {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii2_pins>;
mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii-txid";
phy-handle = <&phy4>;
phy-mode = "rgmii";
phy-handle = <&example5_ethphy4>;
};
mdio: mdio-bus {
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Internal phy */
phy4: ethernet-phy@4 {
/* MT7530's phy4 */
example5_ethphy4: ethernet-phy@4 {
reg = <4>;
};
mt7530: switch@1f {
switch@0 {
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
reg = <0>;
resets = <&rstctrl 2>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan1";
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan2";
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan3";
label = "lan4";
};
/* Commented out. Port 4 is handled by 2nd GMAC.
/* Commented out, phy4 is muxed to gmac1.
port@4 {
reg = <4>;
label = "lan4";
label = "wan";
};
*/
......@@ -305,7 +621,7 @@ examples:
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
......@@ -318,82 +634,171 @@ examples:
};
};
# Example 6: MT7621: mux external phy to SoC's gmac1
- |
//Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
ethernet {
#address-cells = <1>;
#size-cells = <0>;
gmac_0: mac@0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii2_pins>;
mac@1 {
compatible = "mediatek,eth-mac";
reg = <0>;
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&example6_ethphy7>;
};
fixed-link {
speed = <1000>;
full-duplex;
pause;
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* External PHY */
example6_ethphy7: ethernet-phy@7 {
reg = <7>;
phy-mode = "rgmii";
};
switch@0 {
compatible = "mediatek,mt7621";
reg = <0>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};
mdio0: mdio-bus {
# Example 7: MT7621: mux external phy to MT7530's port 5
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
ethernet {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii2_pins>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* External phy */
ephy5: ethernet-phy@7 {
/* External PHY */
example7_ethphy7: ethernet-phy@7 {
reg = <7>;
phy-mode = "rgmii";
};
switch@1f {
switch@0 {
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
reg = <0>;
resets = <&rstctrl 2>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan1";
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan2";
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan3";
label = "lan4";
};
port@4 {
reg = <4>;
label = "lan4";
label = "wan";
};
port@5 {
reg = <5>;
label = "lan5";
phy-mode = "rgmii";
phy-handle = <&ephy5>;
label = "extphy";
phy-mode = "rgmii-txid";
phy-handle = <&example7_ethphy7>;
};
cpu_port0: port@6 {
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac_0>;
phy-mode = "rgmii";
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
......
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