Skip to content

L
linux
Commit 14c04e57 authored by Sonic Zhang's avatar Sonic Zhang Committed by Bob Liu
Browse files
Options

bf60x: update bf60x anomaly list. 

Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarBob Liu <lliubbo@gmail.com>
parent e0a59310
Show whitespace changes
Inline Side-by-side
Showing with 56 additions and 88 deletions
arch/blackfin/mach-bf609/include/mach/anomaly.h
View file @ 14c04e57
...@@ -5,126 +5,94 @@ ...@@ -5,126 +5,94 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2011 Analog Devices Inc. * Copyright 2004-2012 Analog Devices Inc.
* Licensed under the Clear BSD license. * Licensed under the Clear BSD license.
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
*/ */
#if __SILICON_REVISION__ < 0 #if __SILICON_REVISION__ < 0
# error will not work on BF506 silicon version # error will not work on BF609 silicon version
#endif #endif
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
#define ANOMALY_05000074 (1) #define ANOMALY_16000003 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* The EPPI Data Enable (DEN) Signal is Not Functional */
#define ANOMALY_05000119 (1) #define ANOMALY_16000004 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Using L1 Instruction Cache with Parity Enabled is Unreliable */
#define ANOMALY_05000122 (1) #define ANOMALY_16000005 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ /* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
#define ANOMALY_05000245 (1) #define ANOMALY_16000006 (1)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ /* DDR2 Memory Reads May Fail Intermittently */
#define ANOMALY_05000254 (1) #define ANOMALY_16000007 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000265 (1) #define ANOMALY_16000008 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* TestSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000310 (1) #define ANOMALY_16000009 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_16000010 (1)
/* UART IrDA Receiver Fails on Extended Bit Pulses */
#define ANOMALY_05000447 (1)
/* False Hardware Error when RETI Points to Invalid Memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_16000011 (1)
/* PLL Latches Incorrect Settings During Reset */ /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000469 (1) #define ANOMALY_16000012 (1)
/* Incorrect Default MSEL Value in PLL_CTL */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000472 (1) #define ANOMALY_16000013 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000473 (1) #define ANOMALY_16000014 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000477 (1) #define ANOMALY_16000015 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ /* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000481 (1) #define ANOMALY_16000017 (1)
/* IFLUSH sucks at life */ /* RSI Boot Cleanup Routine Does Not Clear Registers */
#define ANOMALY_05000491 (1) #define ANOMALY_16000018 (1)
/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */ /* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
#define ANOMALY_05001001 (__SILICON_REVISION__ < 1) #define ANOMALY_16000019 (1)
/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
#define ANOMALY_16000020 (1)
/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
#define ANOMALY_16000021 (1)
/* Boot Code Fails to Enable Parity Fault Detection */
#define ANOMALY_16000022 (1)
/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
#define ANOMALY_16000027 (1)
/* Interrupted Core Reads of MMRs May Cause Data Loss */
#define ANOMALY_16000030 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0) #define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0) #define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0) #define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0) #define ANOMALY_05000281 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0) #define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0) #define ANOMALY_05000312 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000357 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000440 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000480 (0) #define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0) #define ANOMALY_05000481 (1)
/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
#define ANOMALY_05000491 ANOMALY_16000008
#define ANOMALY_05000477 ANOMALY_16000009
#define ANOMALY_05000443 ANOMALY_16000010
#define ANOMALY_05000461 ANOMALY_16000011
#define ANOMALY_05000426 ANOMALY_16000012
#define ANOMALY_05000310 ANOMALY_16000013
#define ANOMALY_05000245 ANOMALY_16000014
#define ANOMALY_05000074 ANOMALY_16000015
#define ANOMALY_05000416 ANOMALY_16000017
#endif #endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7