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Commit 1663b8fa authored by Martyn Welch's avatar Martyn Welch Committed by Greg Kroah-Hartman
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staging: VME: Remove PIO2 driver 

The PIO2 device is (as far as I know) no longer manufactured. I no longer
have access to the device and this seems unlikely to change. The only
changes to this driver in a long time have been as a result of API changes
else where. Time to remove it...
Signed-off-by: default avatarMartyn Welch <martyn.welch@collabora.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c40a45a4
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drivers/staging/vme/devices/Kconfig
View file @ 1663b8fa
......@@ -10,16 +10,3 @@ config VME_USER
To compile this driver as a module, choose M here. The module will
be called vme_user. If unsure, say N.
config VME_PIO2
tristate "GE PIO2 VME"
depends on STAGING && GPIOLIB
help
Say Y here to include support for the GE PIO2. The PIO2 is a 6U VME
slave card, implementing 32 solid-state relay switched IO lines, in
4 groups of 8. Each bank of IO lines is built to function as input,
output or both depending on the variant of the card.
To compile this driver as a module, choose M here. The module will
be called vme_pio2. If unsure, say N.
drivers/staging/vme/devices/Makefile
View file @ 1663b8fa
......@@ -3,6 +3,3 @@
#
obj-$(CONFIG_VME_USER) += vme_user.o
vme_pio2-objs := vme_pio2_cntr.o vme_pio2_gpio.o vme_pio2_core.o
obj-$(CONFIG_VME_PIO2) += vme_pio2.o
drivers/staging/vme/devices/vme_pio2.h deleted 100644 → 0
View file @ c40a45a4
#ifndef _VME_PIO2_H_
#define _VME_PIO2_H_
#define PIO2_CARDS_MAX 32
#define PIO2_VARIANT_LENGTH 5
#define PIO2_NUM_CHANNELS 32
#define PIO2_NUM_IRQS 11
#define PIO2_NUM_CNTRS 6
#define PIO2_REGS_SIZE 0x40
#define PIO2_REGS_DATA0 0x0
#define PIO2_REGS_DATA1 0x1
#define PIO2_REGS_DATA2 0x2
#define PIO2_REGS_DATA3 0x3
static const int PIO2_REGS_DATA[4] = { PIO2_REGS_DATA0, PIO2_REGS_DATA1,
PIO2_REGS_DATA2, PIO2_REGS_DATA3 };
#define PIO2_REGS_INT_STAT0 0x8
#define PIO2_REGS_INT_STAT1 0x9
#define PIO2_REGS_INT_STAT2 0xa
#define PIO2_REGS_INT_STAT3 0xb
static const int PIO2_REGS_INT_STAT[4] = { PIO2_REGS_INT_STAT0,
PIO2_REGS_INT_STAT1,
PIO2_REGS_INT_STAT2,
PIO2_REGS_INT_STAT3 };
#define PIO2_REGS_INT_STAT_CNTR 0xc
#define PIO2_REGS_INT_MASK0 0x10
#define PIO2_REGS_INT_MASK1 0x11
#define PIO2_REGS_INT_MASK2 0x12
#define PIO2_REGS_INT_MASK3 0x13
#define PIO2_REGS_INT_MASK4 0x14
#define PIO2_REGS_INT_MASK5 0x15
#define PIO2_REGS_INT_MASK6 0x16
#define PIO2_REGS_INT_MASK7 0x17
static const int PIO2_REGS_INT_MASK[8] = { PIO2_REGS_INT_MASK0,
PIO2_REGS_INT_MASK1,
PIO2_REGS_INT_MASK2,
PIO2_REGS_INT_MASK3,
PIO2_REGS_INT_MASK4,
PIO2_REGS_INT_MASK5,
PIO2_REGS_INT_MASK6,
PIO2_REGS_INT_MASK7 };
#define PIO2_REGS_CTRL 0x18
#define PIO2_REGS_VME_VECTOR 0x19
#define PIO2_REGS_CNTR0 0x20
#define PIO2_REGS_CNTR1 0x22
#define PIO2_REGS_CNTR2 0x24
#define PIO2_REGS_CTRL_WRD0 0x26
#define PIO2_REGS_CNTR3 0x28
#define PIO2_REGS_CNTR4 0x2a
#define PIO2_REGS_CNTR5 0x2c
#define PIO2_REGS_CTRL_WRD1 0x2e
#define PIO2_REGS_ID 0x30
/* PIO2_REGS_DATAx (0x0 - 0x3) */
static const int PIO2_CHANNEL_BANK[32] = { 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2,
3, 3, 3, 3, 3, 3, 3, 3 };
#define PIO2_CHANNEL0_BIT BIT(0)
#define PIO2_CHANNEL1_BIT BIT(1)
#define PIO2_CHANNEL2_BIT BIT(2)
#define PIO2_CHANNEL3_BIT BIT(3)
#define PIO2_CHANNEL4_BIT BIT(4)
#define PIO2_CHANNEL5_BIT BIT(5)
#define PIO2_CHANNEL6_BIT BIT(6)
#define PIO2_CHANNEL7_BIT BIT(7)
#define PIO2_CHANNEL8_BIT BIT(0)
#define PIO2_CHANNEL9_BIT BIT(1)
#define PIO2_CHANNEL10_BIT BIT(2)
#define PIO2_CHANNEL11_BIT BIT(3)
#define PIO2_CHANNEL12_BIT BIT(4)
#define PIO2_CHANNEL13_BIT BIT(5)
#define PIO2_CHANNEL14_BIT BIT(6)
#define PIO2_CHANNEL15_BIT BIT(7)
#define PIO2_CHANNEL16_BIT BIT(0)
#define PIO2_CHANNEL17_BIT BIT(1)
#define PIO2_CHANNEL18_BIT BIT(2)
#define PIO2_CHANNEL19_BIT BIT(3)
#define PIO2_CHANNEL20_BIT BIT(4)
#define PIO2_CHANNEL21_BIT BIT(5)
#define PIO2_CHANNEL22_BIT BIT(6)
#define PIO2_CHANNEL23_BIT BIT(7)
#define PIO2_CHANNEL24_BIT BIT(0)
#define PIO2_CHANNEL25_BIT BIT(1)
#define PIO2_CHANNEL26_BIT BIT(2)
#define PIO2_CHANNEL27_BIT BIT(3)
#define PIO2_CHANNEL28_BIT BIT(4)
#define PIO2_CHANNEL29_BIT BIT(5)
#define PIO2_CHANNEL30_BIT BIT(6)
#define PIO2_CHANNEL31_BIT BIT(7)
static const int PIO2_CHANNEL_BIT[32] = { PIO2_CHANNEL0_BIT, PIO2_CHANNEL1_BIT,
PIO2_CHANNEL2_BIT, PIO2_CHANNEL3_BIT,
PIO2_CHANNEL4_BIT, PIO2_CHANNEL5_BIT,
PIO2_CHANNEL6_BIT, PIO2_CHANNEL7_BIT,
PIO2_CHANNEL8_BIT, PIO2_CHANNEL9_BIT,
PIO2_CHANNEL10_BIT, PIO2_CHANNEL11_BIT,
PIO2_CHANNEL12_BIT, PIO2_CHANNEL13_BIT,
PIO2_CHANNEL14_BIT, PIO2_CHANNEL15_BIT,
PIO2_CHANNEL16_BIT, PIO2_CHANNEL17_BIT,
PIO2_CHANNEL18_BIT, PIO2_CHANNEL19_BIT,
PIO2_CHANNEL20_BIT, PIO2_CHANNEL21_BIT,
PIO2_CHANNEL22_BIT, PIO2_CHANNEL23_BIT,
PIO2_CHANNEL24_BIT, PIO2_CHANNEL25_BIT,
PIO2_CHANNEL26_BIT, PIO2_CHANNEL27_BIT,
PIO2_CHANNEL28_BIT, PIO2_CHANNEL29_BIT,
PIO2_CHANNEL30_BIT, PIO2_CHANNEL31_BIT
};
/* PIO2_REGS_INT_STAT_CNTR (0xc) */
#define PIO2_COUNTER0 BIT(0)
#define PIO2_COUNTER1 BIT(1)
#define PIO2_COUNTER2 BIT(2)
#define PIO2_COUNTER3 BIT(3)
#define PIO2_COUNTER4 BIT(4)
#define PIO2_COUNTER5 BIT(5)
static const int PIO2_COUNTER[6] = { PIO2_COUNTER0, PIO2_COUNTER1,
PIO2_COUNTER2, PIO2_COUNTER3,
PIO2_COUNTER4, PIO2_COUNTER5 };
/* PIO2_REGS_CTRL (0x18) */
#define PIO2_VME_INT_MASK 0x7
#define PIO2_LED BIT(6)
#define PIO2_LOOP BIT(7)
/* PIO2_REGS_VME_VECTOR (0x19) */
#define PIO2_VME_VECTOR_SPUR 0x0
#define PIO2_VME_VECTOR_BANK0 0x1
#define PIO2_VME_VECTOR_BANK1 0x2
#define PIO2_VME_VECTOR_BANK2 0x3
#define PIO2_VME_VECTOR_BANK3 0x4
#define PIO2_VME_VECTOR_CNTR0 0x5
#define PIO2_VME_VECTOR_CNTR1 0x6
#define PIO2_VME_VECTOR_CNTR2 0x7
#define PIO2_VME_VECTOR_CNTR3 0x8
#define PIO2_VME_VECTOR_CNTR4 0x9
#define PIO2_VME_VECTOR_CNTR5 0xa
#define PIO2_VME_VECTOR_MASK 0xf0
static const int PIO2_VECTOR_BANK[4] = { PIO2_VME_VECTOR_BANK0,
PIO2_VME_VECTOR_BANK1,
PIO2_VME_VECTOR_BANK2,
PIO2_VME_VECTOR_BANK3 };
static const int PIO2_VECTOR_CNTR[6] = { PIO2_VME_VECTOR_CNTR0,
PIO2_VME_VECTOR_CNTR1,
PIO2_VME_VECTOR_CNTR2,
PIO2_VME_VECTOR_CNTR3,
PIO2_VME_VECTOR_CNTR4,
PIO2_VME_VECTOR_CNTR5 };
/* PIO2_REGS_CNTRx (0x20 - 0x24 & 0x28 - 0x2c) */
static const int PIO2_CNTR_DATA[6] = { PIO2_REGS_CNTR0, PIO2_REGS_CNTR1,
PIO2_REGS_CNTR2, PIO2_REGS_CNTR3,
PIO2_REGS_CNTR4, PIO2_REGS_CNTR5 };
/* PIO2_REGS_CTRL_WRDx (0x26 & 0x2e) */
static const int PIO2_CNTR_CTRL[6] = { PIO2_REGS_CTRL_WRD0,
PIO2_REGS_CTRL_WRD0,
PIO2_REGS_CTRL_WRD0,
PIO2_REGS_CTRL_WRD1,
PIO2_REGS_CTRL_WRD1,
PIO2_REGS_CTRL_WRD1 };
#define PIO2_CNTR_SC_DEV0 0
#define PIO2_CNTR_SC_DEV1 (1 << 6)
#define PIO2_CNTR_SC_DEV2 (2 << 6)
#define PIO2_CNTR_SC_RDBACK (3 << 6)
static const int PIO2_CNTR_SC_DEV[6] = { PIO2_CNTR_SC_DEV0, PIO2_CNTR_SC_DEV1,
PIO2_CNTR_SC_DEV2, PIO2_CNTR_SC_DEV0,
PIO2_CNTR_SC_DEV1, PIO2_CNTR_SC_DEV2 };
#define PIO2_CNTR_RW_LATCH 0
#define PIO2_CNTR_RW_LSB (1 << 4)
#define PIO2_CNTR_RW_MSB (2 << 4)
#define PIO2_CNTR_RW_BOTH (3 << 4)
#define PIO2_CNTR_MODE0 0
#define PIO2_CNTR_MODE1 (1 << 1)
#define PIO2_CNTR_MODE2 (2 << 1)
#define PIO2_CNTR_MODE3 (3 << 1)
#define PIO2_CNTR_MODE4 (4 << 1)
#define PIO2_CNTR_MODE5 (5 << 1)
#define PIO2_CNTR_BCD 1
enum pio2_bank_config { NOFIT, INPUT, OUTPUT, BOTH };
enum pio2_int_config { NONE = 0, LOW2HIGH = 1, HIGH2LOW = 2, EITHER = 4 };
/* Bank configuration structure */
struct pio2_io_bank {
enum pio2_bank_config config;
u8 value;
enum pio2_int_config irq[8];
};
/* Counter configuration structure */
struct pio2_cntr {
int mode;
int count;
};
struct pio2_card {
int id;
int bus;
long base;
int irq_vector;
int irq_level;
char variant[6];
int led;
struct vme_dev *vdev;
struct vme_resource *window;
struct gpio_chip gc;
struct pio2_io_bank bank[4];
struct pio2_cntr cntr[6];
};
int pio2_cntr_reset(struct pio2_card *card);
int pio2_gpio_reset(struct pio2_card *card);
int pio2_gpio_init(struct pio2_card *card);
void pio2_gpio_exit(struct pio2_card *card);
#endif /* _VME_PIO2_H_ */
drivers/staging/vme/devices/vme_pio2_cntr.c deleted 100644 → 0
View file @ c40a45a4
/*
* GE PIO2 Counter Driver
*
* Author: Martyn Welch <martyn.welch@ge.com>
* Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* The PIO-2 has 6 counters, currently this code just disables the interrupts
* and leaves them alone.
*
*/
#include <linux/device.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/vme.h>
#include "vme_pio2.h"
static int pio2_cntr_irq_set(struct pio2_card *card, int id)
{
int retval;
u8 data;
data = PIO2_CNTR_SC_DEV[id] | PIO2_CNTR_RW_BOTH | card->cntr[id].mode;
retval = vme_master_write(card->window, &data, 1, PIO2_CNTR_CTRL[id]);
if (retval < 0)
return retval;
data = card->cntr[id].count & 0xFF;
retval = vme_master_write(card->window, &data, 1, PIO2_CNTR_DATA[id]);
if (retval < 0)
return retval;
data = (card->cntr[id].count >> 8) & 0xFF;
retval = vme_master_write(card->window, &data, 1, PIO2_CNTR_DATA[id]);
if (retval < 0)
return retval;
return 0;
}
int pio2_cntr_reset(struct pio2_card *card)
{
int i, retval = 0;
u8 reg;
/* Clear down all timers */
for (i = 0; i < 6; i++) {
card->cntr[i].mode = PIO2_CNTR_MODE5;
card->cntr[i].count = 0;
retval = pio2_cntr_irq_set(card, i);
if (retval < 0)
return retval;
}
/* Ensure all counter interrupts are cleared */
do {
retval = vme_master_read(card->window, &reg, 1,
PIO2_REGS_INT_STAT_CNTR);
if (retval < 0)
return retval;
} while (reg != 0);
return retval;
}
drivers/staging/vme/devices/vme_pio2_core.c deleted 100644 → 0
View file @ c40a45a4
/*
* GE PIO2 6U VME I/O Driver
*
* Author: Martyn Welch <martyn.welch@ge.com>
* Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/ctype.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/vme.h>
#include "vme_pio2.h"
static const char driver_name[] = "pio2";
static int bus[PIO2_CARDS_MAX];
static int bus_num;
static long base[PIO2_CARDS_MAX];
static int base_num;
static int vector[PIO2_CARDS_MAX];
static int vector_num;
static int level[PIO2_CARDS_MAX];
static int level_num;
static char *variant[PIO2_CARDS_MAX];
static int variant_num;
static bool loopback;
static int pio2_match(struct vme_dev *);
static int pio2_probe(struct vme_dev *);
static int pio2_remove(struct vme_dev *);
static int pio2_get_led(struct pio2_card *card)
{
/* Can't read hardware, state saved in structure */
return card->led;
}
static int pio2_set_led(struct pio2_card *card, int state)
{
u8 reg;
int retval;
reg = card->irq_level;
/* Register state inverse of led state */
if (!state)
reg |= PIO2_LED;
if (loopback)
reg |= PIO2_LOOP;
retval = vme_master_write(card->window, &reg, 1, PIO2_REGS_CTRL);
if (retval < 0)
return retval;
card->led = state ? 1 : 0;
return 0;
}
static void pio2_int(int level, int vector, void *ptr)
{
int vec, i, channel, retval;
u8 reg;
struct pio2_card *card = ptr;
vec = vector & ~PIO2_VME_VECTOR_MASK;
switch (vec) {
case 0:
dev_warn(&card->vdev->dev, "Spurious Interrupt\n");
break;
case 1:
case 2:
case 3:
case 4:
/* Channels 0 to 7 */
retval = vme_master_read(card->window, &reg, 1,
PIO2_REGS_INT_STAT[vec - 1]);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to read IRQ status register\n");
return;
}
for (i = 0; i < 8; i++) {
channel = ((vec - 1) * 8) + i;
if (reg & PIO2_CHANNEL_BIT[channel])
dev_info(&card->vdev->dev,
"Interrupt on I/O channel %d\n",
channel);
}
break;
case 5:
case 6:
case 7:
case 8:
case 9:
case 10:
/* Counters are dealt with by their own handler */
dev_err(&card->vdev->dev,
"Counter interrupt\n");
break;
}
}
/*
* We return whether this has been successful - this is used in the probe to
* ensure we have a valid card.
*/
static int pio2_reset_card(struct pio2_card *card)
{
int retval = 0;
u8 data = 0;
/* Clear main register*/
retval = vme_master_write(card->window, &data, 1, PIO2_REGS_CTRL);
if (retval < 0)
return retval;
/* Clear VME vector */
retval = vme_master_write(card->window, &data, 1, PIO2_REGS_VME_VECTOR);
if (retval < 0)
return retval;
/* Reset GPIO */
retval = pio2_gpio_reset(card);
if (retval < 0)
return retval;
/* Reset counters */
retval = pio2_cntr_reset(card);
if (retval < 0)
return retval;
return 0;
}
static struct vme_driver pio2_driver = {
.name = driver_name,
.match = pio2_match,
.probe = pio2_probe,
.remove = pio2_remove,
};
static int __init pio2_init(void)
{
if (bus_num == 0) {
pr_err("No cards, skipping registration\n");
return -ENODEV;
}
if (bus_num > PIO2_CARDS_MAX) {
pr_err("Driver only able to handle %d PIO2 Cards\n",
PIO2_CARDS_MAX);
bus_num = PIO2_CARDS_MAX;
}
/* Register the PIO2 driver */
return vme_register_driver(&pio2_driver, bus_num);
}
static int pio2_match(struct vme_dev *vdev)
{
if (vdev->num >= bus_num) {
dev_err(&vdev->dev,
"The enumeration of the VMEbus to which the board is connected must be specified\n");
return 0;
}
if (vdev->num >= base_num) {
dev_err(&vdev->dev,
"The VME address for the cards registers must be specified\n");
return 0;
}
if (vdev->num >= vector_num) {
dev_err(&vdev->dev,
"The IRQ vector used by the card must be specified\n");
return 0;
}
if (vdev->num >= level_num) {
dev_err(&vdev->dev,
"The IRQ level used by the card must be specified\n");
return 0;
}
if (vdev->num >= variant_num) {
dev_err(&vdev->dev, "The variant of the card must be specified\n");
return 0;
}
return 1;
}
static int pio2_probe(struct vme_dev *vdev)
{
struct pio2_card *card;
int retval;
int i;
u8 reg;
int vec;
card = devm_kzalloc(&vdev->dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->id = vdev->num;
card->bus = bus[card->id];
card->base = base[card->id];
card->irq_vector = vector[card->id];
card->irq_level = level[card->id] & PIO2_VME_INT_MASK;
strncpy(card->variant, variant[card->id], PIO2_VARIANT_LENGTH);
card->vdev = vdev;
for (i = 0; i < PIO2_VARIANT_LENGTH; i++) {
if (!isdigit(card->variant[i])) {
dev_err(&card->vdev->dev, "Variant invalid\n");
return -EINVAL;
}
}
/*
* Bottom 4 bits of VME interrupt vector used to determine source,
* provided vector should only use upper 4 bits.
*/
if (card->irq_vector & ~PIO2_VME_VECTOR_MASK) {
dev_err(&card->vdev->dev,
"Invalid VME IRQ Vector, vector must not use lower 4 bits\n");
return -EINVAL;
}
/*
* There is no way to determine the build variant or whether each bank
* is input, output or both at run time. The inputs are also inverted
* if configured as both.
*
* We pass in the board variant and use that to determine the
* configuration of the banks.
*/
for (i = 1; i < PIO2_VARIANT_LENGTH; i++) {
switch (card->variant[i]) {
case '0':
card->bank[i - 1].config = NOFIT;
break;
case '1':
case '2':
case '3':
case '4':
card->bank[i - 1].config = INPUT;
break;
case '5':
card->bank[i - 1].config = OUTPUT;
break;
case '6':
case '7':
case '8':
case '9':
card->bank[i - 1].config = BOTH;
break;
}
}
/* Get a master window and position over regs */
card->window = vme_master_request(vdev, VME_A24, VME_SCT, VME_D16);
if (!card->window) {
dev_err(&card->vdev->dev,
"Unable to assign VME master resource\n");
return -EIO;
}
retval = vme_master_set(card->window, 1, card->base, 0x10000, VME_A24,
VME_SCT | VME_USER | VME_DATA, VME_D16);
if (retval) {
dev_err(&card->vdev->dev,
"Unable to configure VME master resource\n");
goto err_set;
}
/*
* There is also no obvious register which we can probe to determine
* whether the provided base is valid. If we can read the "ID Register"
* offset and the reset function doesn't error, assume we have a valid
* location.
*/
retval = vme_master_read(card->window, &reg, 1, PIO2_REGS_ID);
if (retval < 0) {
dev_err(&card->vdev->dev, "Unable to read from device\n");
goto err_read;
}
dev_dbg(&card->vdev->dev, "ID Register:%x\n", reg);
/*
* Ensure all the I/O is cleared. We can't read back the states, so
* this is the only method we have to ensure that the I/O is in a known
* state.
*/
retval = pio2_reset_card(card);
if (retval) {
dev_err(&card->vdev->dev,
"Failed to reset card, is location valid?\n");
retval = -ENODEV;
goto err_reset;
}
/* Configure VME Interrupts */
reg = card->irq_level;
if (pio2_get_led(card))
reg |= PIO2_LED;
if (loopback)
reg |= PIO2_LOOP;
retval = vme_master_write(card->window, &reg, 1, PIO2_REGS_CTRL);
if (retval < 0)
return retval;
/* Set VME vector */
retval = vme_master_write(card->window, &card->irq_vector, 1,
PIO2_REGS_VME_VECTOR);
if (retval < 0)
return retval;
/* Attach spurious interrupt handler. */
vec = card->irq_vector | PIO2_VME_VECTOR_SPUR;
retval = vme_irq_request(vdev, card->irq_level, vec,
&pio2_int, card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to attach VME interrupt vector0x%x, level 0x%x\n",
vec, card->irq_level);
goto err_irq;
}
/* Attach GPIO interrupt handlers. */
for (i = 0; i < 4; i++) {
vec = card->irq_vector | PIO2_VECTOR_BANK[i];
retval = vme_irq_request(vdev, card->irq_level, vec,
&pio2_int, card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to attach VME interrupt vector0x%x, level 0x%x\n",
vec, card->irq_level);
goto err_gpio_irq;
}
}
/* Attach counter interrupt handlers. */
for (i = 0; i < 6; i++) {
vec = card->irq_vector | PIO2_VECTOR_CNTR[i];
retval = vme_irq_request(vdev, card->irq_level, vec,
&pio2_int, card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to attach VME interrupt vector0x%x, level 0x%x\n",
vec, card->irq_level);
goto err_cntr_irq;
}
}
/* Register IO */
retval = pio2_gpio_init(card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to register with GPIO framework\n");
goto err_gpio;
}
/* Set LED - This also sets interrupt level */
retval = pio2_set_led(card, 0);
if (retval < 0) {
dev_err(&card->vdev->dev, "Unable to set LED\n");
goto err_led;
}
dev_set_drvdata(&card->vdev->dev, card);
dev_info(&card->vdev->dev,
"PIO2 (variant %s) configured at 0x%lx\n", card->variant,
card->base);
return 0;
err_led:
pio2_gpio_exit(card);
err_gpio:
i = 6;
err_cntr_irq:
while (i > 0) {
i--;
vec = card->irq_vector | PIO2_VECTOR_CNTR[i];
vme_irq_free(vdev, card->irq_level, vec);
}
i = 4;
err_gpio_irq:
while (i > 0) {
i--;
vec = card->irq_vector | PIO2_VECTOR_BANK[i];
vme_irq_free(vdev, card->irq_level, vec);
}
vec = (card->irq_vector & PIO2_VME_VECTOR_MASK) | PIO2_VME_VECTOR_SPUR;
vme_irq_free(vdev, card->irq_level, vec);
err_irq:
pio2_reset_card(card);
err_reset:
err_read:
vme_master_set(card->window, 0, 0, 0, VME_A16, 0, VME_D16);
err_set:
vme_master_free(card->window);
return retval;
}
static int pio2_remove(struct vme_dev *vdev)
{
int vec;
int i;
struct pio2_card *card = dev_get_drvdata(&vdev->dev);
pio2_gpio_exit(card);
for (i = 0; i < 6; i++) {
vec = card->irq_vector | PIO2_VECTOR_CNTR[i];
vme_irq_free(vdev, card->irq_level, vec);
}
for (i = 0; i < 4; i++) {
vec = card->irq_vector | PIO2_VECTOR_BANK[i];
vme_irq_free(vdev, card->irq_level, vec);
}
vec = (card->irq_vector & PIO2_VME_VECTOR_MASK) | PIO2_VME_VECTOR_SPUR;
vme_irq_free(vdev, card->irq_level, vec);
pio2_reset_card(card);
vme_master_set(card->window, 0, 0, 0, VME_A16, 0, VME_D16);
vme_master_free(card->window);
return 0;
}
static void __exit pio2_exit(void)
{
vme_unregister_driver(&pio2_driver);
}
/* These are required for each board */
MODULE_PARM_DESC(bus, "Enumeration of VMEbus to which the board is connected");
module_param_hw_array(bus, int, other, &bus_num, 0444);
MODULE_PARM_DESC(base, "Base VME address for PIO2 Registers");
module_param_hw_array(base, long, other, &base_num, 0444);
MODULE_PARM_DESC(vector, "VME IRQ Vector (Lower 4 bits masked)");
module_param_hw_array(vector, int, other, &vector_num, 0444);
MODULE_PARM_DESC(level, "VME IRQ Level");
module_param_hw_array(level, int, other, &level_num, 0444);
MODULE_PARM_DESC(variant, "Last 4 characters of PIO2 board variant");
module_param_array(variant, charp, &variant_num, 0444);
/* This is for debugging */
MODULE_PARM_DESC(loopback, "Enable loopback mode on all cards");
module_param(loopback, bool, 0444);
MODULE_DESCRIPTION("GE PIO2 6U VME I/O Driver");
MODULE_AUTHOR("Martyn Welch <martyn.welch@ge.com");
MODULE_LICENSE("GPL");
module_init(pio2_init);
module_exit(pio2_exit);
drivers/staging/vme/devices/vme_pio2_gpio.c deleted 100644 → 0
View file @ c40a45a4
/*
* GE PIO2 GPIO Driver
*
* Author: Martyn Welch <martyn.welch@ge.com>
* Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/ctype.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/vme.h>
#include "vme_pio2.h"
static const char driver_name[] = "pio2_gpio";
static int pio2_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
u8 reg;
int retval;
struct pio2_card *card = gpiochip_get_data(chip);
if ((card->bank[PIO2_CHANNEL_BANK[offset]].config == OUTPUT) |
(card->bank[PIO2_CHANNEL_BANK[offset]].config == NOFIT)) {
dev_err(&card->vdev->dev, "Channel not available as input\n");
return 0;
}
retval = vme_master_read(card->window, &reg, 1,
PIO2_REGS_DATA[PIO2_CHANNEL_BANK[offset]]);
if (retval < 0) {
dev_err(&card->vdev->dev, "Unable to read from GPIO\n");
return 0;
}
/*
* Remember, input on channels configured as both input and output
* are inverted!
*/
if (reg & PIO2_CHANNEL_BIT[offset]) {
if (card->bank[PIO2_CHANNEL_BANK[offset]].config != BOTH)
return 0;
return 1;
}
if (card->bank[PIO2_CHANNEL_BANK[offset]].config != BOTH)
return 1;
return 0;
}
static void pio2_gpio_set(struct gpio_chip *chip,
unsigned int offset, int value)
{
u8 reg;
int retval;
struct pio2_card *card = gpiochip_get_data(chip);
if ((card->bank[PIO2_CHANNEL_BANK[offset]].config == INPUT) |
(card->bank[PIO2_CHANNEL_BANK[offset]].config == NOFIT)) {
dev_err(&card->vdev->dev, "Channel not available as output\n");
return;
}
if (value)
reg = card->bank[PIO2_CHANNEL_BANK[offset]].value |
PIO2_CHANNEL_BIT[offset];
else
reg = card->bank[PIO2_CHANNEL_BANK[offset]].value &
~PIO2_CHANNEL_BIT[offset];
retval = vme_master_write(card->window, &reg, 1,
PIO2_REGS_DATA[PIO2_CHANNEL_BANK[offset]]);
if (retval < 0) {
dev_err(&card->vdev->dev, "Unable to write to GPIO\n");
return;
}
card->bank[PIO2_CHANNEL_BANK[offset]].value = reg;
}
/* Directionality configured at board build - send appropriate response */
static int pio2_gpio_dir_in(struct gpio_chip *chip, unsigned int offset)
{
int data;
struct pio2_card *card = gpiochip_get_data(chip);
if ((card->bank[PIO2_CHANNEL_BANK[offset]].config == OUTPUT) |
(card->bank[PIO2_CHANNEL_BANK[offset]].config == NOFIT)) {
dev_err(&card->vdev->dev,
"Channel directionality not configurable at runtime\n");
data = -EINVAL;
} else {
data = 0;
}
return data;
}
/* Directionality configured at board build - send appropriate response */
static int pio2_gpio_dir_out(struct gpio_chip *chip,
unsigned int offset, int value)
{
int data;
struct pio2_card *card = gpiochip_get_data(chip);
if ((card->bank[PIO2_CHANNEL_BANK[offset]].config == INPUT) |
(card->bank[PIO2_CHANNEL_BANK[offset]].config == NOFIT)) {
dev_err(&card->vdev->dev,
"Channel directionality not configurable at runtime\n");
data = -EINVAL;
} else {
data = 0;
}
return data;
}
/*
* We return whether this has been successful - this is used in the probe to
* ensure we have a valid card.
*/
int pio2_gpio_reset(struct pio2_card *card)
{
int retval = 0;
int i, j;
u8 data = 0;
/* Zero output registers */
for (i = 0; i < 4; i++) {
retval = vme_master_write(card->window, &data, 1,
PIO2_REGS_DATA[i]);
if (retval < 0)
return retval;
card->bank[i].value = 0;
}
/* Set input interrupt masks */
for (i = 0; i < 4; i++) {
retval = vme_master_write(card->window, &data, 1,
PIO2_REGS_INT_MASK[i * 2]);
if (retval < 0)
return retval;
retval = vme_master_write(card->window, &data, 1,
PIO2_REGS_INT_MASK[(i * 2) + 1]);
if (retval < 0)
return retval;
for (j = 0; j < 8; j++)
card->bank[i].irq[j] = NONE;
}
/* Ensure all I/O interrupts are cleared */
for (i = 0; i < 4; i++) {
do {
retval = vme_master_read(card->window, &data, 1,
PIO2_REGS_INT_STAT[i]);
if (retval < 0)
return retval;
} while (data != 0);
}
return 0;
}
int pio2_gpio_init(struct pio2_card *card)
{
int retval = 0;
char *label;
label = kasprintf(GFP_KERNEL,
"%s@%s", driver_name, dev_name(&card->vdev->dev));
if (!label)
return -ENOMEM;
card->gc.label = label;
card->gc.ngpio = PIO2_NUM_CHANNELS;
/* Dynamic allocation of base */
card->gc.base = -1;
/* Setup pointers to chip functions */
card->gc.direction_input = pio2_gpio_dir_in;
card->gc.direction_output = pio2_gpio_dir_out;
card->gc.get = pio2_gpio_get;
card->gc.set = pio2_gpio_set;
/* This function adds a memory mapped GPIO chip */
retval = gpiochip_add_data(&card->gc, card);
if (retval) {
dev_err(&card->vdev->dev, "Unable to register GPIO\n");
kfree(card->gc.label);
}
return retval;
};
void pio2_gpio_exit(struct pio2_card *card)
{
const char *label = card->gc.label;
gpiochip_remove(&card->gc);
kfree(label);
}
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