Commit 17e4732d authored by Conor Dooley's avatar Conor Dooley

dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible

The l2 cache on PolarFire SoC is cross between that of the fu540 and
the fu740. It has the extra interrupt from the fu740 but the lower
number of cache-sets. Add a specific compatible to avoid the likes
of:

mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long

Fixes: 34fc9cc3 ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 1709c70c
...@@ -17,9 +17,6 @@ description: ...@@ -17,9 +17,6 @@ description:
acts as directory-based coherency manager. acts as directory-based coherency manager.
All the properties in ePAPR/DeviceTree specification applies for this platform. All the properties in ePAPR/DeviceTree specification applies for this platform.
allOf:
- $ref: /schemas/cache-controller.yaml#
select: select:
properties: properties:
compatible: compatible:
...@@ -33,11 +30,16 @@ select: ...@@ -33,11 +30,16 @@ select:
properties: properties:
compatible: compatible:
items: oneOf:
- items:
- enum: - enum:
- sifive,fu540-c000-ccache - sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache - sifive,fu740-c000-ccache
- const: cache - const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
cache-block-size: cache-block-size:
const: 64 const: 64
...@@ -72,30 +74,47 @@ properties: ...@@ -72,30 +74,47 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt. The reserved memory node should be defined as per the bindings in reserved-memory.txt.
if: allOf:
- $ref: /schemas/cache-controller.yaml#
- if:
properties: properties:
compatible: compatible:
contains: contains:
const: sifive,fu540-c000-ccache enum:
- sifive,fu740-c000-ccache
- microchip,mpfs-ccache
then: then:
properties: properties:
interrupts: interrupts:
description: | description: |
Must contain entries for DirError, DataError and DataFail signals. Must contain entries for DirError, DataError, DataFail, DirFail signals.
maxItems: 3 minItems: 4
cache-sets:
const: 1024
else: else:
properties: properties:
interrupts: interrupts:
description: | description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals. Must contain entries for DirError, DataError and DataFail signals.
minItems: 4 maxItems: 3
- if:
properties:
compatible:
contains:
const: sifive,fu740-c000-ccache
then:
properties:
cache-sets: cache-sets:
const: 2048 const: 2048
else:
properties:
cache-sets:
const: 1024
additionalProperties: false additionalProperties: false
required: required:
......
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