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Commit 1839533f authored by Tero Kristo's avatar Tero Kristo Committed by Tony Lindgren
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ARM: dts: dra7: add clkctrl nodes 

Add clkctrl nodes for DRA7 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.

This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 460c4961
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Showing with 261 additions and 736 deletions
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View file @ 1839533f
...@@ -554,7 +554,7 @@ &pcie1_ep { ...@@ -554,7 +554,7 @@ &pcie1_ep {
&mcasp3 { &mcasp3 {
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>; assigned-clock-parents = <&sys_clkin2>;
status = "okay"; status = "okay";
......
arch/arm/boot/dts/dra7-evm-common.dtsi
View file @ 1839533f
...@@ -204,7 +204,7 @@ &usb2 { ...@@ -204,7 +204,7 @@ &usb2 {
&atl { &atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>, assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>, <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>, <&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>, <&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>; <&atl_clkin2_ck>;
...@@ -222,7 +222,7 @@ atl2 { ...@@ -222,7 +222,7 @@ atl2 {
&mcasp3 { &mcasp3 {
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>; assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay"; status = "okay";
......
arch/arm/boot/dts/dra7.dtsi
View file @ 1839533f
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h> #include <dt-bindings/pinctrl/dra.h>
#include <dt-bindings/clock/dra7.h>
#define MAX_SOURCES 400 #define MAX_SOURCES 400
...@@ -887,7 +888,7 @@ timer1: timer@4ae18000 { ...@@ -887,7 +888,7 @@ timer1: timer@4ae18000 {
ti,hwmods = "timer1"; ti,hwmods = "timer1";
ti,timer-alwon; ti,timer-alwon;
clock-names = "fck"; clock-names = "fck";
clocks = <&timer1_gfclk_mux>; clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
}; };
timer2: timer@48032000 { timer2: timer@48032000 {
...@@ -1370,7 +1371,7 @@ qspi: qspi@4b300000 { ...@@ -1370,7 +1371,7 @@ qspi: qspi@4b300000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
ti,hwmods = "qspi"; ti,hwmods = "qspi";
clocks = <&qspi_gfclk_div>; clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
clock-names = "fck"; clock-names = "fck";
num-cs = <4>; num-cs = <4>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
...@@ -1392,7 +1393,8 @@ sata_phy: phy@4A096000 { ...@@ -1392,7 +1393,8 @@ sata_phy: phy@4A096000 {
<0x4A096800 0x40>; /* pll_ctrl */ <0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl"; reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>; syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin1>, <&sata_ref_clk>; clocks = <&sys_clkin1>,
<&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk"; clock-names = "sysclk", "refclk";
syscon-pllreset = <&scm_conf 0x3fc>; syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>; #phy-cells = <0>;
...@@ -1407,9 +1409,9 @@ pcie1_phy: pciephy@4a094000 { ...@@ -1407,9 +1409,9 @@ pcie1_phy: pciephy@4a094000 {
syscon-pcs = <&scm_conf_pcie 0x10>; syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>, clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>, <&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>, <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
<&optfclk_pciephy1_clk>, <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
<&optfclk_pciephy1_div_clk>, <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
<&optfclk_pciephy_div>, <&optfclk_pciephy_div>,
<&sys_clkin1>; <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2", clock-names = "dpll_ref", "dpll_ref_m2",
...@@ -1427,9 +1429,9 @@ pcie2_phy: pciephy@4a095000 { ...@@ -1427,9 +1429,9 @@ pcie2_phy: pciephy@4a095000 {
syscon-pcs = <&scm_conf_pcie 0x10>; syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>, clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>, <&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>, <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
<&optfclk_pciephy2_clk>, <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
<&optfclk_pciephy2_div_clk>, <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
<&optfclk_pciephy_div>, <&optfclk_pciephy_div>,
<&sys_clkin1>; <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2", clock-names = "dpll_ref", "dpll_ref_m2",
...@@ -1446,7 +1448,7 @@ sata: sata@4a141100 { ...@@ -1446,7 +1448,7 @@ sata: sata@4a141100 {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>; phys = <&sata_phy>;
phy-names = "sata-phy"; phy-names = "sata-phy";
clocks = <&sata_ref_clk>; clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
ti,hwmods = "sata"; ti,hwmods = "sata";
ports-implemented = <0x1>; ports-implemented = <0x1>;
}; };
...@@ -1474,7 +1476,7 @@ usb2_phy1: phy@4a084000 { ...@@ -1474,7 +1476,7 @@ usb2_phy1: phy@4a084000 {
reg = <0x4a084000 0x400>; reg = <0x4a084000 0x400>;
syscon-phy-power = <&scm_conf 0x300>; syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>, clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>; <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", clock-names = "wkupclk",
"refclk"; "refclk";
#phy-cells = <0>; #phy-cells = <0>;
...@@ -1486,7 +1488,7 @@ usb2_phy2: phy@4a085000 { ...@@ -1486,7 +1488,7 @@ usb2_phy2: phy@4a085000 {
reg = <0x4a085000 0x400>; reg = <0x4a085000 0x400>;
syscon-phy-power = <&scm_conf 0xe74>; syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>, clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>; <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
clock-names = "wkupclk", clock-names = "wkupclk",
"refclk"; "refclk";
#phy-cells = <0>; #phy-cells = <0>;
...@@ -1501,7 +1503,7 @@ usb3_phy1: phy@4a084400 { ...@@ -1501,7 +1503,7 @@ usb3_phy1: phy@4a084400 {
syscon-phy-power = <&scm_conf 0x370>; syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>, clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>, <&sys_clkin1>,
<&usb_otg_ss1_refclk960m>; <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", clock-names = "wkupclk",
"sysclk", "sysclk",
"refclk"; "refclk";
...@@ -1648,7 +1650,7 @@ atl: atl@4843c000 { ...@@ -1648,7 +1650,7 @@ atl: atl@4843c000 {
ti,hwmods = "atl"; ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>; <&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>; clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clock-names = "fck"; clock-names = "fck";
status = "disabled"; status = "disabled";
}; };
...@@ -1664,8 +1666,8 @@ mcasp1: mcasp@48460000 { ...@@ -1664,8 +1666,8 @@ mcasp1: mcasp@48460000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
<&mcasp1_ahclkr_mux>; <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr"; clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled"; status = "disabled";
}; };
...@@ -1681,8 +1683,9 @@ mcasp2: mcasp@48464000 { ...@@ -1681,8 +1683,9 @@ mcasp2: mcasp@48464000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
<&mcasp2_ahclkr_mux>; <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
<&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr"; clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled"; status = "disabled";
}; };
...@@ -1698,7 +1701,8 @@ mcasp3: mcasp@48468000 { ...@@ -1698,7 +1701,8 @@ mcasp3: mcasp@48468000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
}; };
...@@ -1714,7 +1718,8 @@ mcasp4: mcasp@4846c000 { ...@@ -1714,7 +1718,8 @@ mcasp4: mcasp@4846c000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
}; };
...@@ -1730,7 +1735,8 @@ mcasp5: mcasp@48470000 { ...@@ -1730,7 +1735,8 @@ mcasp5: mcasp@48470000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
}; };
...@@ -1746,7 +1752,8 @@ mcasp6: mcasp@48474000 { ...@@ -1746,7 +1752,8 @@ mcasp6: mcasp@48474000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
}; };
...@@ -1762,7 +1769,8 @@ mcasp7: mcasp@48478000 { ...@@ -1762,7 +1769,8 @@ mcasp7: mcasp@48478000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
}; };
...@@ -1778,7 +1786,8 @@ mcasp8: mcasp@4847c000 { ...@@ -1778,7 +1786,8 @@ mcasp8: mcasp@4847c000 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
}; };
...@@ -1800,7 +1809,7 @@ crossbar_mpu: crossbar@4a002a48 { ...@@ -1800,7 +1809,7 @@ crossbar_mpu: crossbar@4a002a48 {
mac: ethernet@48484000 { mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw"; compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac"; ti,hwmods = "gmac";
clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
clock-names = "fck", "cpts"; clock-names = "fck", "cpts";
cpdma_channels = <8>; cpdma_channels = <8>;
ale_entries = <1024>; ale_entries = <1024>;
...@@ -1870,7 +1879,7 @@ dcan1: can@481cc000 { ...@@ -1870,7 +1879,7 @@ dcan1: can@481cc000 {
reg = <0x4ae3c000 0x2000>; reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&scm_conf 0x558 0>; syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcan1_sys_clk_mux>; clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
status = "disabled"; status = "disabled";
}; };
...@@ -1901,7 +1910,7 @@ dispc@58001000 { ...@@ -1901,7 +1910,7 @@ dispc@58001000 {
reg = <0x58001000 0x1000>; reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc"; ti,hwmods = "dss_dispc";
clocks = <&dss_dss_clk>; clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck"; clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */ /* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>; syscon-pol = <&scm_conf 0x534>;
...@@ -1917,7 +1926,8 @@ hdmi: encoder@58060000 { ...@@ -1917,7 +1926,8 @@ hdmi: encoder@58060000 {
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
ti,hwmods = "dss_hdmi"; ti,hwmods = "dss_hdmi";
clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk"; clock-names = "fck", "sys_clk";
}; };
}; };
...@@ -2101,4 +2111,4 @@ &cpu_crit { ...@@ -2101,4 +2111,4 @@ &cpu_crit {
temperature = <120000>; /* milli Celsius */ temperature = <120000>; /* milli Celsius */
}; };
/include/ "dra7xx-clocks.dtsi" #include "dra7xx-clocks.dtsi"
arch/arm/boot/dts/dra72-evm-common.dtsi
View file @ 1839533f
...@@ -514,7 +514,7 @@ hdmi_out: endpoint { ...@@ -514,7 +514,7 @@ hdmi_out: endpoint {
&atl { &atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>, assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>, <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>, <&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>, <&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>; <&atl_clkin2_ck>;
...@@ -532,7 +532,7 @@ atl2 { ...@@ -532,7 +532,7 @@ atl2 {
&mcasp3 { &mcasp3 {
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>; assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay"; status = "okay";
......
arch/arm/boot/dts/dra72x.dtsi
View file @ 1839533f
...@@ -25,8 +25,8 @@ &dss { ...@@ -25,8 +25,8 @@ &dss {
<0x58004300 0x20>; <0x58004300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1"; reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_dss_clk>, clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_video1_clk>; <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>;
clock-names = "fck", "video1_clk"; clock-names = "fck", "video1_clk";
}; };
......
arch/arm/boot/dts/dra74x.dtsi
View file @ 1839533f
...@@ -93,9 +93,9 @@ &dss { ...@@ -93,9 +93,9 @@ &dss {
reg-names = "dss", "pll1_clkctrl", "pll1", reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2"; "pll2_clkctrl", "pll2";
clocks = <&dss_dss_clk>, clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_video1_clk>, <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
<&dss_video2_clk>; <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
clock-names = "fck", "video1_clk", "video2_clk"; clock-names = "fck", "video1_clk", "video2_clk";
}; };
......
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file @ 1839533f
...@@ -11,25 +11,25 @@ &cm_core_aon_clocks { ...@@ -11,25 +11,25 @@ &cm_core_aon_clocks {
atl_clkin0_ck: atl_clkin0_ck { atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,dra7-atl-clock"; compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>; clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
}; };
atl_clkin1_ck: atl_clkin1_ck { atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,dra7-atl-clock"; compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>; clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
}; };
atl_clkin2_ck: atl_clkin2_ck { atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,dra7-atl-clock"; compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>; clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
}; };
atl_clkin3_ck: atl_clkin3_ck { atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,dra7-atl-clock"; compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>; clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
}; };
hdmi_clkin_ck: hdmi_clkin_ck { hdmi_clkin_ck: hdmi_clkin_ck {
...@@ -809,70 +809,6 @@ ipu1_gfclk_mux: ipu1_gfclk_mux@520 { ...@@ -809,70 +809,6 @@ ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
assigned-clock-parents = <&dpll_core_h22x2_ck>; assigned-clock-parents = <&dpll_core_h22x2_ck>;
}; };
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x0550>;
};
mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x0550>;
};
mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x0550>;
};
timer5_gfclk_mux: timer5_gfclk_mux@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0558>;
};
timer6_gfclk_mux: timer6_gfclk_mux@560 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0560>;
};
timer7_gfclk_mux: timer7_gfclk_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0568>;
};
timer8_gfclk_mux: timer8_gfclk_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
ti,bit-shift = <24>;
reg = <0x0570>;
};
uart6_gfclk_mux: uart6_gfclk_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x0580>;
};
dummy_ck: dummy_ck { dummy_ck: dummy_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -1188,39 +1124,8 @@ wkupaon_iclk_mux: wkupaon_iclk_mux@108 { ...@@ -1188,39 +1124,8 @@ wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
clocks = <&sys_clkin1>, <&abe_lp_clk_div>; clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>; reg = <0x0108>;
}; };
gpio1_dbclk: gpio1_dbclk@1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1838>;
};
dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
ti,bit-shift = <24>;
reg = <0x1888>;
};
timer1_gfclk_mux: timer1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1840>;
};
uart10_gfclk_mux: uart10_gfclk_mux@1880 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1880>;
};
}; };
&cm_core_clocks { &cm_core_clocks {
dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>; #clock-cells = <0>;
...@@ -1255,22 +1160,6 @@ apll_pcie_ck: apll_pcie_ck@21c { ...@@ -1255,22 +1160,6 @@ apll_pcie_ck: apll_pcie_ck@21c {
reg = <0x021c>, <0x0220>; reg = <0x021c>, <0x0220>;
}; };
optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <8>;
};
optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <8>;
};
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock"; compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>; clocks = <&apll_pcie_ck>;
...@@ -1281,38 +1170,6 @@ optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { ...@@ -1281,38 +1170,6 @@ optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
ti,max-div = <2>; ti,max-div = <2>;
}; };
optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <9>;
};
optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <9>;
};
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <10>;
};
optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <10>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
...@@ -1541,167 +1398,6 @@ l3init_960m_gfclk: l3init_960m_gfclk@6c0 { ...@@ -1541,167 +1398,6 @@ l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
reg = <0x06c0>; reg = <0x06c0>;
}; };
dss_32khz_clk: dss_32khz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <11>;
reg = <0x1120>;
};
dss_48mhz_clk: dss_48mhz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
ti,bit-shift = <9>;
reg = <0x1120>;
};
dss_dss_clk: dss_dss_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
ti,bit-shift = <8>;
reg = <0x1120>;
ti,set-rate-parent;
};
dss_hdmi_clk: dss_hdmi_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
ti,bit-shift = <10>;
reg = <0x1120>;
};
dss_video1_clk: dss_video1_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
ti,bit-shift = <12>;
reg = <0x1120>;
};
dss_video2_clk: dss_video2_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
ti,bit-shift = <13>;
reg = <0x1120>;
};
gpio2_dbclk: gpio2_dbclk@1760 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1760>;
};
gpio3_dbclk: gpio3_dbclk@1768 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1768>;
};
gpio4_dbclk: gpio4_dbclk@1770 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1770>;
};
gpio5_dbclk: gpio5_dbclk@1778 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1778>;
};
gpio6_dbclk: gpio6_dbclk@1780 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1780>;
};
gpio7_dbclk: gpio7_dbclk@1810 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1810>;
};
gpio8_dbclk: gpio8_dbclk@1818 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1818>;
};
mmc1_clk32k: mmc1_clk32k@1328 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1328>;
};
mmc2_clk32k: mmc2_clk32k@1330 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1330>;
};
mmc3_clk32k: mmc3_clk32k@1820 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1820>;
};
mmc4_clk32k: mmc4_clk32k@1828 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1828>;
};
sata_ref_clk: sata_ref_clk@1388 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
ti,bit-shift = <8>;
reg = <0x1388>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x13f0>;
};
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x1340>;
};
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,gate-clock"; compatible = "ti,gate-clock";
...@@ -1726,38 +1422,6 @@ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { ...@@ -1726,38 +1422,6 @@ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
reg = <0x0698>; reg = <0x0698>;
}; };
atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
ti,bit-shift = <24>;
reg = <0x0c00>;
};
atl_gfclk_mux: atl_gfclk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
ti,bit-shift = <26>;
reg = <0x0c00>;
};
rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
};
gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
ti,bit-shift = <25>;
reg = <0x13d0>;
};
gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,mux-clock";
...@@ -1787,432 +1451,283 @@ l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { ...@@ -1787,432 +1451,283 @@ l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
ti,dividers = <8>, <16>, <32>; ti,dividers = <8>, <16>, <32>;
}; };
mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 { vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>;
reg = <0x1860>;
};
mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>; ti,bit-shift = <24>;
reg = <0x1860>; reg = <0x1020>;
}; };
mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 { vip2_gclk_mux: vip2_gclk_mux@1028 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <22>; ti,bit-shift = <24>;
reg = <0x1860>; reg = <0x1028>;
}; };
mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 { vip3_gclk_mux: vip3_gclk_mux@1030 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>; ti,bit-shift = <24>;
reg = <0x1868>; reg = <0x1030>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&abe_24m_fclk>;
}; };
};
mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 { &cm_core_clockdomains {
#clock-cells = <0>; coreaon_clkdm: coreaon_clkdm {
compatible = "ti,mux-clock"; compatible = "ti,clockdomain";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; clocks = <&dpll_usb_ck>;
ti,bit-shift = <22>;
reg = <0x1868>;
}; };
};
mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 { &scm_conf_clocks {
dss_deshdcp_clk: dss_deshdcp_clk@558 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,gate-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; clocks = <&l3_iclk_div>;
ti,bit-shift = <24>; ti,bit-shift = <0>;
reg = <0x1898>; reg = <0x558>;
}; };
mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 { ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,gate-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>; ti,bit-shift = <20>;
reg = <0x1898>; reg = <0x0558>;
}; };
mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 { ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,gate-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; clocks = <&l4_root_clk_div>;
ti,bit-shift = <24>; ti,bit-shift = <21>;
reg = <0x1878>; reg = <0x0558>;
}; };
mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 { ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,gate-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>; ti,bit-shift = <22>;
reg = <0x1878>; reg = <0x0558>;
}; };
mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 { sys_32k_ck: sys_32k_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
ti,bit-shift = <24>; ti,bit-shift = <8>;
reg = <0x1904>; reg = <0x6c4>;
}; };
};
mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 { &cm_core_aon {
#clock-cells = <0>; mpu_cm: mpu_cm@300 {
compatible = "ti,mux-clock"; compatible = "ti,omap4-cm";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; reg = <0x300 0x100>;
ti,bit-shift = <22>; #address-cells = <1>;
reg = <0x1904>; #size-cells = <1>;
}; ranges = <0 0x300 0x100>;
mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 { mpu_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0x4>;
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1908>;
}; };
mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
ti,bit-shift = <22>;
reg = <0x1908>;
}; };
mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 { ipu_cm: ipu_cm@500 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0x500 0x100>;
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; #address-cells = <1>;
ti,bit-shift = <22>; #size-cells = <1>;
reg = <0x1890>; ranges = <0 0x500 0x100>;
};
mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 { ipu_clkctrl: clk@40 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x40 0x44>;
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1890>;
}; };
mmc1_fclk_mux: mmc1_fclk_mux@1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1328>;
}; };
mmc1_fclk_div: mmc1_fclk_div@1328 { rtc_cm: rtc_cm@700 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,divider-clock"; reg = <0x700 0x100>;
clocks = <&mmc1_fclk_mux>; #address-cells = <1>;
ti,bit-shift = <25>; #size-cells = <1>;
ti,max-div = <4>; ranges = <0 0x700 0x100>;
reg = <0x1328>;
ti,index-power-of-two;
};
mmc2_fclk_mux: mmc2_fclk_mux@1330 { rtc_clkctrl: clk@40 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x40 0x8>;
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1330>;
}; };
mmc2_fclk_div: mmc2_fclk_div@1330 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1330>;
ti,index-power-of-two;
}; };
mmc3_gfclk_mux: mmc3_gfclk_mux@1820 { };
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1820>;
};
mmc3_gfclk_div: mmc3_gfclk_div@1820 { &cm_core {
#clock-cells = <0>; coreaon_cm: coreaon_cm@600 {
compatible = "ti,divider-clock"; compatible = "ti,omap4-cm";
clocks = <&mmc3_gfclk_mux>; reg = <0x600 0x100>;
ti,bit-shift = <25>; #address-cells = <1>;
ti,max-div = <4>; #size-cells = <1>;
reg = <0x1820>; ranges = <0 0x600 0x100>;
ti,index-power-of-two;
};
mmc4_gfclk_mux: mmc4_gfclk_mux@1828 { coreaon_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0x1c>;
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1828>;
}; };
mmc4_gfclk_div: mmc4_gfclk_div@1828 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1828>;
ti,index-power-of-two;
}; };
qspi_gfclk_mux: qspi_gfclk_mux@1838 { l3main1_cm: l3main1_cm@700 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0x700 0x100>;
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x1838>; ranges = <0 0x700 0x100>;
};
qspi_gfclk_div: qspi_gfclk_div@1838 { l3main1_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,divider-clock"; reg = <0x20 0x74>;
clocks = <&qspi_gfclk_mux>; #clock-cells = <2>;
ti,bit-shift = <25>;
ti,max-div = <4>;
reg = <0x1838>;
ti,index-power-of-two;
}; };
timer10_gfclk_mux: timer10_gfclk_mux@1728 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1728>;
}; };
timer11_gfclk_mux: timer11_gfclk_mux@1730 { dma_cm: dma_cm@a00 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0xa00 0x100>;
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x1730>; ranges = <0 0xa00 0x100>;
};
timer13_gfclk_mux: timer13_gfclk_mux@17c8 { dma_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0x4>;
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x17c8>;
}; };
timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x17d0>;
}; };
timer15_gfclk_mux: timer15_gfclk_mux@17d8 { emif_cm: emif_cm@b00 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0xb00 0x100>;
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x17d8>; ranges = <0 0xb00 0x100>;
};
timer16_gfclk_mux: timer16_gfclk_mux@1830 { emif_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0x4>;
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1830>;
}; };
timer2_gfclk_mux: timer2_gfclk_mux@1738 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1738>;
}; };
timer3_gfclk_mux: timer3_gfclk_mux@1740 { atl_cm: atl_cm@c00 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0xc00 0x100>;
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x1740>; ranges = <0 0xc00 0x100>;
};
timer4_gfclk_mux: timer4_gfclk_mux@1748 { atl_clkctrl: clk@0 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x0 0x4>;
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1748>;
}; };
timer9_gfclk_mux: timer9_gfclk_mux@1750 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
ti,bit-shift = <24>;
reg = <0x1750>;
}; };
uart1_gfclk_mux: uart1_gfclk_mux@1840 { l4cfg_cm: l4cfg_cm@d00 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0xd00 0x100>;
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x1840>; ranges = <0 0xd00 0x100>;
};
uart2_gfclk_mux: uart2_gfclk_mux@1848 { l4cfg_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0x84>;
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1848>;
}; };
uart3_gfclk_mux: uart3_gfclk_mux@1850 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x1850>;
}; };
uart4_gfclk_mux: uart4_gfclk_mux@1858 { l3instr_cm: l3instr_cm@e00 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0xe00 0x100>;
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x1858>; ranges = <0 0xe00 0x100>;
};
uart5_gfclk_mux: uart5_gfclk_mux@1870 { l3instr_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0xc>;
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1870>;
}; };
uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
reg = <0x18d0>;
}; };
uart8_gfclk_mux: uart8_gfclk_mux@18e0 { dss_cm: dss_cm@1100 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0x1100 0x100>;
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x18e0>; ranges = <0 0x1100 0x100>;
};
uart9_gfclk_mux: uart9_gfclk_mux@18e8 { dss_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0x14>;
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x18e8>;
}; };
vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1020>;
}; };
vip2_gclk_mux: vip2_gclk_mux@1028 { l3init_cm: l3init_cm@1300 {
#clock-cells = <0>; compatible = "ti,omap4-cm";
compatible = "ti,mux-clock"; reg = <0x1300 0x100>;
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; #address-cells = <1>;
ti,bit-shift = <24>; #size-cells = <1>;
reg = <0x1028>; ranges = <0 0x1300 0x100>;
};
vip3_gclk_mux: vip3_gclk_mux@1030 { l3init_clkctrl: clk@20 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,mux-clock"; reg = <0x20 0xd4>;
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; #clock-cells = <2>;
ti,bit-shift = <24>;
reg = <0x1030>;
}; };
};
&cm_core_clockdomains {
coreaon_clkdm: coreaon_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_usb_ck>;
}; };
};
&scm_conf_clocks { l4per_cm: l4per_cm@1700 {
dss_deshdcp_clk: dss_deshdcp_clk@558 { compatible = "ti,omap4-cm";
#clock-cells = <0>; reg = <0x1700 0x300>;
compatible = "ti,gate-clock"; #address-cells = <1>;
clocks = <&l3_iclk_div>; #size-cells = <1>;
ti,bit-shift = <0>; ranges = <0 0x1700 0x300>;
reg = <0x558>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk@558 { l4per_clkctrl: clk@0 {
#clock-cells = <0>; compatible = "ti,clkctrl";
compatible = "ti,gate-clock"; reg = <0x0 0x20c>;
clocks = <&l4_root_clk_div>; #clock-cells = <2>;
ti,bit-shift = <20>;
reg = <0x0558>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk@558 { assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
#clock-cells = <0>; assigned-clock-parents = <&abe_24m_fclk>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <21>;
reg = <0x0558>;
}; };
ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>;
reg = <0x0558>;
}; };
sys_32k_ck: sys_32k_ck { };
#clock-cells = <0>;
compatible = "ti,mux-clock"; &prm {
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; wkupaon_cm: wkupaon_cm@1800 {
ti,bit-shift = <8>; compatible = "ti,omap4-cm";
reg = <0x6c4>; reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1800 0x100>;
wkupaon_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
}; };
}; };
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