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Commit 18857d8e authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk 

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 73b5d164 cd594a3b
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Showing with 7869 additions and 578 deletions
Documentation/fb/pxafb.txt 0 → 100644
View file @ 18857d8e
Driver for PXA25x LCD controller
================================
The driver supports the following options, either via
options=<OPTIONS> when modular or video=pxafb:<OPTIONS> when built in.
For example:
modprobe pxafb options=mode:640x480-8,passive
or on the kernel command line
video=pxafb:mode:640x480-8,passive
mode:XRESxYRES[-BPP]
XRES == LCCR1_PPL + 1
YRES == LLCR2_LPP + 1
The resolution of the display in pixels
BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16.
pixclock:PIXCLOCK
Pixel clock in picoseconds
left:LEFT == LCCR1_BLW + 1
right:RIGHT == LCCR1_ELW + 1
hsynclen:HSYNC == LCCR1_HSW + 1
upper:UPPER == LCCR2_BFW
lower:LOWER == LCCR2_EFR
vsynclen:VSYNC == LCCR2_VSW + 1
Display margins and sync times
color | mono => LCCR0_CMS
umm...
active | passive => LCCR0_PAS
Active (TFT) or Passive (STN) display
single | dual => LCCR0_SDS
Single or dual panel passive display
4pix | 8pix => LCCR0_DPD
4 or 8 pixel monochrome single panel data
hsync:HSYNC
vsync:VSYNC
Horizontal and vertical sync. 0 => active low, 1 => active
high.
dpc:DPC
Double pixel clock. 1=>true, 0=>false
outputen:POLARITY
Output Enable Polarity. 0 => active low, 1 => active high
pixclockpol:POLARITY
pixel clock polarity
0 => falling edge, 1 => rising edge
arch/arm/Kconfig
View file @ 18857d8e
......@@ -111,6 +111,9 @@ config ARCH_INTEGRATOR
config ARCH_IOP3XX
bool "IOP3xx-based"
config ARCH_IXP4XX
bool "IXP4xx-based"
config ARCH_L7200
bool "LinkUp-L7200"
help
......@@ -170,6 +173,8 @@ source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop3xx/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"
......@@ -222,7 +227,7 @@ config FORCE_MAX_ZONEORDER
config DMABOUNCE
bool
depends on SA1111
depends on SA1111 || ARCH_IXP4XX
default y
source arch/arm/mm/Kconfig
......@@ -252,7 +257,7 @@ config DISCONTIGMEM
# Now handle the bus types
config PCI
bool "PCI support" if ARCH_INTEGRATOR_AP
default y if ARCH_FTVPCI || ARCH_SHARK || FOOTBRIDGE_HOST || ARCH_IOP3XX
default y if ARCH_FTVPCI || ARCH_SHARK || FOOTBRIDGE_HOST || ARCH_IOP3XX || ARCH_IXP4XX
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
......@@ -791,8 +796,8 @@ config DEBUG_S3C2410_PORT
before it is used.
config DEBUG_S3C2410_UART
int
depends on DEBUG_LL && ARCH_S3C2410
int "S3C2410 UART to use for low-level debug"
default "0"
help
Choice for UART for kernel low-level using S3C2410 UARTS,
......
arch/arm/Makefile
View file @ 18857d8e
......@@ -92,6 +92,7 @@ textaddr-$(CONFIG_ARCH_CLPS711X) := 0xc0028000
textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000
machine-$(CONFIG_ARCH_IOP3XX) := iop3xx
machine-$(CONFIG_ARCH_ADIFCC) := adifcc
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
......
arch/arm/boot/Makefile
View file @ 18857d8e
......@@ -51,6 +51,8 @@ initrd_phys-$(CONFIG_ARCH_SA1100) := 0xc0800000
params_phys-$(CONFIG_ARCH_IOP3XX) := 0xa0000100
zreladdr-$(CONFIG_ARCH_ADIFCC) := 0xc0008000
params_phys-$(CONFIG_ARCH_ADIFCC) := 0xc0000100
zreladdr-$(CONFIG_ARCH_IXP4XX) := 0x00008000
params-phys-$(CONFIG_ARCH_IXP4XX) := 0x00000100
zreladdr-$(CONFIG_ARCH_OMAP) := 0x10008000
params_phys-$(CONFIG_ARCH_OMAP) := 0x10000100
initrd_phys-$(CONFIG_ARCH_OMAP) := 0x10800000
......
arch/arm/boot/compressed/head.S
View file @ 18857d8e
......@@ -73,6 +73,12 @@
.macro writeb, rb
str \rb, [r3, #0x14] @ UTDR
.endm
#elif defined(CONFIG_ARCH_IXP4XX)
.macro loadsp, rb
mov \rb, #0xc8000000
.endm
.macro writeb, rb
str \rb, [r3, #0]
#elif defined(CONFIG_ARCH_LH7A40X)
.macro loadsp, rb
ldr \rb, =0x80000700 @ UART2 UARTBASE
......@@ -176,7 +182,7 @@ not_angel:
ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
subs r0, r0, r1 @ calculate the delta offset
@ if delta is zero, we're
@ if delta is zero, we are
beq not_relocated @ running at the address we
@ were linked at.
......
arch/arm/configs/ixp4xx_defconfig 0 → 100644
View file @ 18857d8e
#
# Automatically generated make config: don't edit
#
CONFIG_ARM=y
CONFIG_MMU=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_STANDALONE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODULE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y
#
# System Type
#
# CONFIG_ARCH_ADIFCC is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set
CONFIG_ARCH_IXP4XX=y
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_VERSATILE_PB is not set
#
# CLPS711X/EP721X Implementations
#
#
# Epxa10db
#
#
# Footbridge Implementations
#
#
# IOP3xx Implementation Options
#
# CONFIG_ARCH_IOP310 is not set
# CONFIG_ARCH_IOP321 is not set
#
# IOP3xx Chipset Features
#
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
#
# Intel IXP4xx Implementation Options
#
#
# IXP4xx Platforms
#
CONFIG_ARCH_IXDP425=y
CONFIG_ARCH_IXCDP1100=y
CONFIG_ARCH_PRPMC1100=y
CONFIG_ARCH_ADI_COYOTE=y
# CONFIG_ARCH_AVILA is not set
CONFIG_ARCH_IXDP4XX=y
#
# IXP4xx Options
#
# CONFIG_IXP4XX_INDIRECT_PCI is not set
#
# Intel PXA250/210 Implementations
#
#
# SA11x0 Implementations
#
#
# TI OMAP Implementations
#
#
# OMAP Core Type
#
#
# OMAP Board Type
#
#
# OMAP Feature Selections
#
#
# S3C2410 Implementations
#
#
# LH7A40X Implementations
#
CONFIG_DMABOUNCE=y
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_XSCALE=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5T=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_MINICACHE=y
#
# Processor Features
#
# CONFIG_ARM_THUMB is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_XSCALE_PMU=y
#
# General setup
#
CONFIG_PCI=y
# CONFIG_ZBOOT_ROM is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_PCI_LEGACY_PROC=y
CONFIG_PCI_NAMES=y
#
# At least one math emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Generic Driver Options
#
# CONFIG_DEBUG_DRIVER is not set
CONFIG_PM=y
# CONFIG_PREEMPT is not set
CONFIG_APM=y
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp root=/dev/nfs"
CONFIG_ALIGNMENT_TRAP=y
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_REDBOOT_PARTS=y
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
CONFIG_MTD_IXP4XX=y
# CONFIG_MTD_EDB7312 is not set
# CONFIG_MTD_PCI is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
#
# NAND Flash Device Drivers
#
CONFIG_MTD_NAND=m
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
CONFIG_MTD_NAND_IDS=m
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_CARMEL is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_INITRD=y
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=m
CONFIG_PACKET_MMAP=y
CONFIG_NETLINK_DEV=m
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_FWMARK=y
CONFIG_IP_ROUTE_NAT=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_TOS=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
#
# IP: Virtual Server Configuration
#
CONFIG_IP_VS=m
CONFIG_IP_VS_DEBUG=y
CONFIG_IP_VS_TAB_BITS=12
#
# IPVS transport protocol load balancing support
#
# CONFIG_IP_VS_PROTO_TCP is not set
# CONFIG_IP_VS_PROTO_UDP is not set
# CONFIG_IP_VS_PROTO_ESP is not set
# CONFIG_IP_VS_PROTO_AH is not set
#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
# CONFIG_IP_VS_SED is not set
# CONFIG_IP_VS_NQ is not set
#
# IPVS application helper
#
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_BRIDGE_NETFILTER=y
#
# IP: Netfilter Configuration
#
CONFIG_IP_NF_CONNTRACK=m
CONFIG_IP_NF_FTP=m
CONFIG_IP_NF_IRC=m
# CONFIG_IP_NF_TFTP is not set
# CONFIG_IP_NF_AMANDA is not set
CONFIG_IP_NF_QUEUE=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_LIMIT=m
# CONFIG_IP_NF_MATCH_IPRANGE is not set
CONFIG_IP_NF_MATCH_MAC=m
# CONFIG_IP_NF_MATCH_PKTTYPE is not set
CONFIG_IP_NF_MATCH_MARK=m
CONFIG_IP_NF_MATCH_MULTIPORT=m
CONFIG_IP_NF_MATCH_TOS=m
# CONFIG_IP_NF_MATCH_RECENT is not set
# CONFIG_IP_NF_MATCH_ECN is not set
# CONFIG_IP_NF_MATCH_DSCP is not set
CONFIG_IP_NF_MATCH_AH_ESP=m
CONFIG_IP_NF_MATCH_LENGTH=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_MATCH_TCPMSS=m
# CONFIG_IP_NF_MATCH_HELPER is not set
CONFIG_IP_NF_MATCH_STATE=m
# CONFIG_IP_NF_MATCH_CONNTRACK is not set
CONFIG_IP_NF_MATCH_OWNER=m
# CONFIG_IP_NF_MATCH_PHYSDEV is not set
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_REDIRECT=m
# CONFIG_IP_NF_TARGET_NETMAP is not set
# CONFIG_IP_NF_TARGET_SAME is not set
CONFIG_IP_NF_NAT_LOCAL=y
CONFIG_IP_NF_NAT_SNMP_BASIC=m
CONFIG_IP_NF_NAT_IRC=m
CONFIG_IP_NF_NAT_FTP=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_TOS=m
# CONFIG_IP_NF_TARGET_ECN is not set
# CONFIG_IP_NF_TARGET_DSCP is not set
CONFIG_IP_NF_TARGET_MARK=m
# CONFIG_IP_NF_TARGET_CLASSIFY is not set
CONFIG_IP_NF_TARGET_LOG=m
CONFIG_IP_NF_TARGET_ULOG=m
CONFIG_IP_NF_TARGET_TCPMSS=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
# CONFIG_IP_NF_ARP_MANGLE is not set
CONFIG_IP_NF_COMPAT_IPCHAINS=m
CONFIG_IP_NF_COMPAT_IPFWADM=m
# CONFIG_IP_NF_RAW is not set
#
# Bridge: Netfilter Configuration
#
# CONFIG_BRIDGE_NF_EBTABLES is not set
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
# CONFIG_ATM_CLIP_NO_ICMP is not set
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
# CONFIG_DECNET is not set
CONFIG_LLC=m
# CONFIG_LLC2 is not set
CONFIG_IPX=m
# CONFIG_IPX_INTERN is not set
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=y
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_IPDDP_DECAP=y
CONFIG_X25=m
CONFIG_LAPB=m
# CONFIG_NET_DIVERT is not set
CONFIG_ECONET=m
CONFIG_ECONET_AUNUDP=y
CONFIG_ECONET_NATIVE=y
CONFIG_WAN_ROUTER=m
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
# CONFIG_NET_SCH_HFSC is not set
CONFIG_NET_SCH_CSZ=m
# CONFIG_NET_SCH_ATM is not set
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
# CONFIG_NET_SCH_DELAY is not set
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_QOS=y
CONFIG_NET_ESTIMATOR=y
CONFIG_NET_CLS=y
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_ROUTE=y
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_POLICE=y
#
# Network testing
#
CONFIG_NET_PKTGEN=m
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
CONFIG_EEPRO100=y
# CONFIG_EEPRO100_PIO is not set
# CONFIG_E100 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
CONFIG_NET_RADIO=y
#
# Obsolete Wireless cards support (pre-802.11)
#
# CONFIG_STRIP is not set
#
# Wireless 802.11b ISA/PCI cards support
#
# CONFIG_AIRO is not set
CONFIG_HERMES=y
# CONFIG_PLX_HERMES is not set
# CONFIG_TMD_HERMES is not set
CONFIG_PCI_HERMES=y
# CONFIG_ATMEL is not set
#
# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
#
CONFIG_NET_WIRELESS=y
#
# Wan interfaces
#
CONFIG_WAN=y
# CONFIG_DSCC4 is not set
# CONFIG_LANMEDIA is not set
# CONFIG_SYNCLINK_SYNCPPP is not set
CONFIG_HDLC=m
CONFIG_HDLC_RAW=y
# CONFIG_HDLC_RAW_ETH is not set
CONFIG_HDLC_CISCO=y
CONFIG_HDLC_FR=y
CONFIG_HDLC_PPP=y
CONFIG_HDLC_X25=y
# CONFIG_PCI200SYN is not set
# CONFIG_WANXL is not set
# CONFIG_PC300 is not set
# CONFIG_FARSYNC is not set
CONFIG_DLCI=m
CONFIG_DLCI_COUNT=24
CONFIG_DLCI_MAX=8
CONFIG_WAN_ROUTER_DRIVERS=y
# CONFIG_CYCLADES_SYNC is not set
# CONFIG_LAPBETHER is not set
# CONFIG_X25_ASY is not set
#
# ATM drivers
#
CONFIG_ATM_TCP=m
# CONFIG_ATM_LANAI is not set
# CONFIG_ATM_ENI is not set
# CONFIG_ATM_FIRESTREAM is not set
# CONFIG_ATM_ZATM is not set
# CONFIG_ATM_NICSTAR is not set
# CONFIG_ATM_IDT77252 is not set
# CONFIG_ATM_AMBASSADOR is not set
# CONFIG_ATM_HORIZON is not set
# CONFIG_ATM_IA is not set
# CONFIG_ATM_FORE200E_MAYBE is not set
# CONFIG_ATM_HE is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
#
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_IDEDISK_STROKE is not set
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_IDE_TASK_IOCTL is not set
# CONFIG_IDE_TASKFILE_IO is not set
#
# IDE chipset support/bugfixes
#
CONFIG_IDE_GENERIC=y
CONFIG_BLK_DEV_IDEPCI=y
# CONFIG_IDEPCI_SHARE_IRQ is not set
# CONFIG_BLK_DEV_OFFBOARD is not set
# CONFIG_BLK_DEV_GENERIC is not set
# CONFIG_BLK_DEV_OPTI621 is not set
# CONFIG_BLK_DEV_SL82C105 is not set
CONFIG_BLK_DEV_IDEDMA_PCI=y
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
# CONFIG_IDEDMA_PCI_AUTO is not set
CONFIG_BLK_DEV_ADMA=y
# CONFIG_BLK_DEV_AEC62XX is not set
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_BLK_DEV_AMD74XX is not set
CONFIG_BLK_DEV_CMD64X=y
# CONFIG_BLK_DEV_TRIFLEX is not set
# CONFIG_BLK_DEV_CY82C693 is not set
# CONFIG_BLK_DEV_CS5520 is not set
# CONFIG_BLK_DEV_CS5530 is not set
# CONFIG_BLK_DEV_HPT34X is not set
CONFIG_BLK_DEV_HPT366=y
# CONFIG_BLK_DEV_SC1200 is not set
# CONFIG_BLK_DEV_PIIX is not set
# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
CONFIG_BLK_DEV_PDC202XX_NEW=y
# CONFIG_PDC202XX_FORCE is not set
# CONFIG_BLK_DEV_SVWKS is not set
# CONFIG_BLK_DEV_SIIMAGE is not set
# CONFIG_BLK_DEV_SLC90E66 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_VIA82CXXX is not set
CONFIG_BLK_DEV_IDEDMA=y
# CONFIG_IDEDMA_IVB is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
# CONFIG_SERIO is not set
# CONFIG_SERIO_I8042 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_IXP4XX_WATCHDOG=y
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
#
# I2C Hardware Bus support
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_I810 is not set
# CONFIG_I2C_ISA is not set
CONFIG_I2C_IXP4XX=y
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_PROSAVAGE is not set
# CONFIG_I2C_SAVAGE4 is not set
# CONFIG_SCx200_ACB is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
# CONFIG_I2C_VOODOO3 is not set
#
# Hardware Sensors Chip support
#
CONFIG_I2C_SENSOR=y
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_FSCHER is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83627HF is not set
#
# Other I2C Chip support
#
CONFIG_SENSORS_EEPROM=y
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
# CONFIG_EXT2_FS_SECURITY is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
# CONFIG_EXT3_FS_SECURITY is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVPTS_FS_XATTR is not set
CONFIG_TMPFS=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_NAND is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_NEC98_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# Misc devices
#
#
# USB support
#
# CONFIG_USB is not set
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# Kernel hacking
#
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_INFO is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SLAB is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_WAITQ is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_DEBUG_BDI2000_XSCALE is not set
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/arm/configs/smdk2410_defconfig 0 → 100644
View file @ 18857d8e
#
# Automatically generated make config: don't edit
#
CONFIG_ARM=y
CONFIG_MMU=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_STANDALONE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# System Type
#
# CONFIG_ARCH_ADIFCC is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_SHARK is not set
CONFIG_ARCH_S3C2410=y
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_VERSATILE_PB is not set
#
# CLPS711X/EP721X Implementations
#
#
# Epxa10db
#
#
# Footbridge Implementations
#
#
# IOP3xx Implementation Options
#
# CONFIG_ARCH_IOP310 is not set
# CONFIG_ARCH_IOP321 is not set
#
# IOP3xx Chipset Features
#
#
# Intel PXA250/210 Implementations
#
#
# SA11x0 Implementations
#
#
# TI OMAP Implementations
#
#
# OMAP Core Type
#
#
# OMAP Board Type
#
#
# OMAP Feature Selections
#
#
# S3C2410 Implementations
#
# CONFIG_ARCH_BAST is not set
# CONFIG_ARCH_H1940 is not set
CONFIG_ARCH_SMDK2410=y
# CONFIG_MACH_VR1000 is not set
#
# LH7A40X Implementations
#
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_ARM920T=y
CONFIG_CPU_32v4=y
CONFIG_CPU_ABRT_EV4T=y
CONFIG_CPU_CACHE_V4WT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
#
# General setup
#
# CONFIG_ZBOOT_ROM is not set
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
#
# At least one math emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_AOUT=y
# CONFIG_BINFMT_MISC is not set
#
# Generic Driver Options
#
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_PM is not set
# CONFIG_PREEMPT is not set
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE="root=1f04 mem=32M"
CONFIG_ALIGNMENT_TRAP=y
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_PARTITIONS is not set
# CONFIG_MTD_CONCAT is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_EDB7312 is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
#
# NAND Flash Device Drivers
#
# CONFIG_MTD_NAND is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_INITRD is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_PACKET is not set
# CONFIG_NETLINK_DEV is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_NETFILTER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
#
# Ethernet (1000 Mbit)
#
#
# Ethernet (10000 Mbit)
#
#
# Token Ring devices
#
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_S3C2410=y
CONFIG_SERIAL_S3C2410_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
CONFIG_ROMFS_FS=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
# CONFIG_MSDOS_PARTITION is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_NEC98_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Graphics support
#
CONFIG_FB=y
CONFIG_FB_VIRTUAL=y
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_PCI_CONSOLE=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
#
# Logo configuration
#
# CONFIG_LOGO is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# Misc devices
#
#
# USB support
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# Kernel hacking
#
CONFIG_FRAME_POINTER=y
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_INFO is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SLAB is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_WAITQ is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
CONFIG_DEBUG_LL_PRINTK=y
CONFIG_DEBUG_S3C2410_PORT=y
CONFIG_DEBUG_S3C2410_UART=0
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_CRC32=y
CONFIG_LIBCRC32C=y
arch/arm/kernel/bios32.c
View file @ 18857d8e
......@@ -155,6 +155,30 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
}
}
/*
* Same as above. The PrPMC800 carrier board for the PrPMC1100
* card maps the host-bridge @ 00:01:00 for some reason and it
* ends up getting scanned. Note that we only want to do this
* fixup when we find the IXP4xx on a PrPMC system, which is why
* we check the machine type. We could be running on a board
* with an IXP4xx target device and we don't want to kill the
* resources in that case.
*/
static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
{
int i;
if (machine_is_prpmc1100()) {
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
dev->resource[i].flags = 0;
}
}
}
/*
* PCI IDE controllers use non-standard I/O port decoding, respect it.
*/
......@@ -273,6 +297,10 @@ struct pci_fixup pcibios_fixups[] = {
PCI_FIXUP_HEADER,
PCI_ANY_ID, PCI_ANY_ID,
pci_fixup_ide_bases
}, {
PCI_FIXUP_HEADER,
PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX,
pci_fixup_prpmc1100
}, { 0 }
};
......
arch/arm/kernel/debug.S
View file @ 18857d8e
......@@ -465,13 +465,53 @@
beq 1001b
.endm
#elif defined(CONFIG_ARCH_IXP4XX)
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0xc8000000
movne \rx, #0xff000000
add \rx,\rx,#3 @ Uart regs are at off set of 3 if
@ byte writes used - Big Endian.
.endm
.macro senduart,rd,rx
strb \rd, [\rx]
.endm
.macro waituart,rd,rx
1002: ldrb \rd, [\rx, #0x14]
and \rd, \rd, #0x60 @ check THRE and TEMT bits
teq \rd, #0x60
bne 1002b
.endm
.macro busyuart,rd,rx
.endm
#elif defined(CONFIG_ARCH_OMAP)
#include <asm/arch/serial.h>
#ifdef CONFIG_ARCH_OMAP730
#define OMAP_SERIAL_REG_SHIFT 0
#else
#define OMAP_SERIAL_REG_SHIFT 2
#endif
/* See also __create_page_tables in head.S */
.macro addruart,rx
mov \rx, #0xff000000
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0xff000000 @ physical base address
movne \rx, #0xfe000000 @ virtual base
orr \rx, \rx, #0x00fb0000
#ifdef CONFIG_OMAP_LL_DEBUG_UART3
orr \rx, \rx, #0x00009000 @ UART 3
#endif
#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
orr \rx, \rx, #0x00000800 @ UART 2 & 3
#endif
.endm
.macro senduart,rd,rx
......@@ -486,9 +526,6 @@
.endm
.macro waituart,rd,rx
1001: ldrb \rd, [\rx, #(0x6 << OMAP_SERIAL_REG_SHIFT)]
tst \rd, #0x10
beq 1001b
.endm
#elif defined(CONFIG_ARCH_S3C2410)
......@@ -551,7 +588,7 @@
.endm
#elif defined(CONFIG_ARCH_LH7A40X)
@ It isn't known if this will be appropriate for every 40x
@ It is not known if this will be appropriate for every 40x
@ board.
.macro addruart,rx
......
arch/arm/kernel/entry-armv.S
View file @ 18857d8e
......@@ -623,10 +623,15 @@ ENTRY(soft_irq_mask)
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifdef CONFIG_PXA27x
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
#else
mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR
#endif
ands \irqnr, \irqstat, \irqnr
beq 1001f
rsb \irqstat, \irqnr, #0
......@@ -639,6 +644,34 @@ ENTRY(soft_irq_mask)
.macro irq_prio_table
.endm
#elif defined (CONFIG_ARCH_IXP4XX)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
ldr \irqstat, [\irqstat] @ get interrupts
cmp \irqstat, #0
beq 1002f
clz \irqnr, \irqstat
mov \base, #31
subs \irqnr, \base, \irqnr
/*
1001: tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tsteq \irqnr, #32
beq 1001b
teq \irqnr, #32
*/
1002:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_OMAP)
.macro disable_fiq
......@@ -1219,7 +1252,7 @@ ENTRY(ret_from_exception)
/*
* Register switch for ARMv3 and ARMv4 processors
* r0 = previous thread_info, r1 = next thread_info
* r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
* previous and next are guaranteed not to be the same.
*/
ENTRY(__switch_to)
......
arch/arm/mach-ixp4xx/Kconfig 0 → 100644
View file @ 18857d8e
config ARCH_SUPPORTS_BIG_ENDIAN
bool
depends on ARCH_IXP4XX
default y
menu "Intel IXP4xx Implementation Options"
comment "IXP4xx Platforms"
config ARCH_IXDP425
bool "Support for Intel IXDP425 (Richfield) Development Platform"
depends on ARCH_IXP4XX
help
#
# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
# number from the bootloader due to marketing monkeys, so we just enable it
# by default if IXDP425 is enabled.
#
config ARCH_IXCDP1100
bool
depends on ARCH_IXDP425
default y
config ARCH_PRPMC1100
bool "Support for Motorola PrPMC 1100 Platform"
depends on ARCH_IXP4XX
config ARCH_ADI_COYOTE
bool "Support for ADI Engineering Coyote Gateway Reference Platform"
depends on ARCH_IXP4XX
config ARCH_AVILA
bool "Support for Gateworks Avila Network Platform"
depends on ARCH_IXP4XX
#
# Avila and IXDP share the same source for now. Will change in future
#
config ARCH_IXDP4XX
bool
depends on ARCH_IXDP425 || ARCH_AVILA
default y
comment "IXP4xx Options"
config IXP4XX_INDIRECT_PCI
bool "Use indirect PCI memory access"
depends on ARCH_IXP4XX
help
IXP4xx provides two methods of accessing PCI memory space:
1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
To access PCI via this space, we simply ioremap() the BAR
into the kernel and we can use the standard read[bwl]/write[bwl]
macros. This is the preffered method due to speed but it
limits the system to just 64MB of PCI memory. This can be
problamatic if using video cards and other memory-heavy devices.
2) If > 64MB of memory space is required, the IXP4xx can be
configured to use indirect registers to access PCI This allows
for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
The disadvantadge of this is that every PCI access requires
three local register accesses plus a spinlock, but in some
cases the performance hit is acceptable. In addition, you cannot
mmap() PCI devices in this case due to the indirect nature
of the PCI window.
By default, the direct method is used. Choose this option if you
need to use the indirect method instead. If you don't know
what you need, leave this option unselected.
endmenu
arch/arm/mach-ixp4xx/Makefile 0 → 100644
View file @ 18857d8e
#
# Makefile for the linux kernel.
#
obj-y += common.o common-pci.o
obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o ixdp425-setup.o
obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o coyote-setup.o
obj-$(CONFIG_ARCH_PRPMC1100) += prpmc1100-pci.o prpmc1100-setup.o
arch/arm/mach-ixp4xx/common-pci.c 0 → 100644
View file @ 18857d8e
/*
* arch/arm/mach-ixp4xx/common-pci.c
*
* IXP4XX PCI routines for all platforms
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <asm/dma-mapping.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <asm/system.h>
#include <asm/mach/pci.h>
#include <asm/hardware.h>
#include <asm/sizes.h>
/*
* IXP4xx PCI read function is dependent on whether we are
* running A0 or B0 (AppleGate) silicon.
*/
int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
/*
* Base address for PCI regsiter region
*/
unsigned long ixp4xx_pci_reg_base = 0;
/*
* PCI cfg an I/O routines are done by programming a
* command/byte enable register, and then read/writing
* the data from a data regsiter. We need to ensure
* these transactions are atomic or we will end up
* with corrupt data on the bus or in a driver.
*/
static spinlock_t ixp4xx_pci_lock = SPIN_LOCK_UNLOCKED;
/*
* Read from PCI config space
*/
static void crp_read(u32 ad_cbe, u32 *data)
{
unsigned long flags;
spin_lock_irqsave(&ixp4xx_pci_lock, flags);
*PCI_CRP_AD_CBE = ad_cbe;
*data = *PCI_CRP_RDATA;
spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
}
/*
* Write to PCI config space
*/
static void crp_write(u32 ad_cbe, u32 data)
{
unsigned long flags;
spin_lock_irqsave(&ixp4xx_pci_lock, flags);
*PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
*PCI_CRP_WDATA = data;
spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
}
static inline int check_master_abort(void)
{
/* check Master Abort bit after access */
unsigned long isr = *PCI_ISR;
if (isr & PCI_ISR_PFE) {
/* make sure the Master Abort bit is reset */
*PCI_ISR = PCI_ISR_PFE;
pr_debug("%s failed\n", __FUNCTION__);
return 1;
}
return 0;
}
int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
{
unsigned long flags;
int retval = 0;
int i;
spin_lock_irqsave(&ixp4xx_pci_lock, flags);
*PCI_NP_AD = addr;
/*
* PCI workaround - only works if NP PCI space reads have
* no side effects!!! Read 8 times. last one will be good.
*/
for (i = 0; i < 8; i++) {
*PCI_NP_CBE = cmd;
*data = *PCI_NP_RDATA;
*data = *PCI_NP_RDATA;
}
if(check_master_abort())
retval = 1;
spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
return retval;
}
int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
{
unsigned long flags;
int retval = 0;
spin_lock_irqsave(&ixp4xx_pci_lock, flags);
*PCI_NP_AD = addr;
/* set up and execute the read */
*PCI_NP_CBE = cmd;
/* the result of the read is now in NP_RDATA */
*data = *PCI_NP_RDATA;
if(check_master_abort())
retval = 1;
spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
return retval;
}
int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
{
unsigned long flags;
int retval = 0;
spin_lock_irqsave(&ixp4xx_pci_lock, flags);
*PCI_NP_AD = addr;
/* set up the write */
*PCI_NP_CBE = cmd;
/* execute the write by writing to NP_WDATA */
*PCI_NP_WDATA = data;
if(check_master_abort())
retval = 1;
spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
return retval;
}
static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
{
u32 addr;
if (!bus_num) {
/* type 0 */
addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
(where & ~3);
} else {
/* type 1 */
addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
}
return addr;
}
/*
* Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
* 0 and 3 are not valid indexes...
*/
static u32 bytemask[] = {
/*0*/ 0,
/*1*/ 0xff,
/*2*/ 0xffff,
/*3*/ 0,
/*4*/ 0xffffffff,
};
static u32 local_byte_lane_enable_bits(u32 n, int size)
{
if (size == 1)
return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
if (size == 2)
return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
if (size == 4)
return 0;
return 0xffffffff;
}
static int local_read_config(int where, int size, u32 *value)
{
u32 n, data;
pr_debug("local_read_config from %d size %d\n", where, size);
n = where % 4;
crp_read(where & ~3, &data);
*value = (data >> (8*n)) & bytemask[size];
pr_debug("local_read_config read %#x\n", *value);
return PCIBIOS_SUCCESSFUL;
}
static int local_write_config(int where, int size, u32 value)
{
u32 n, byte_enables, data;
pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
n = where % 4;
byte_enables = local_byte_lane_enable_bits(n, size);
if (byte_enables == 0xffffffff)
return PCIBIOS_BAD_REGISTER_NUMBER;
data = value << (8*n);
crp_write((where & ~3) | byte_enables, data);
return PCIBIOS_SUCCESSFUL;
}
static u32 byte_lane_enable_bits(u32 n, int size)
{
if (size == 1)
return (0xf & ~BIT(n)) << 4;
if (size == 2)
return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
if (size == 4)
return 0;
return 0xffffffff;
}
static int read_config(u8 bus_num, u16 devfn, int where, int size, u32 *value)
{
u32 n, byte_enables, addr, data;
pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
*value = 0xffffffff;
n = where % 4;
byte_enables = byte_lane_enable_bits(n, size);
if (byte_enables == 0xffffffff)
return PCIBIOS_BAD_REGISTER_NUMBER;
addr = ixp4xx_config_addr(bus_num, devfn, where);
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
*value = (data >> (8*n)) & bytemask[size];
pr_debug("read_config_byte read %#x\n", *value);
return PCIBIOS_SUCCESSFUL;
}
static int write_config(u8 bus_num, u16 devfn, int where, int size, u32 value)
{
u32 n, byte_enables, addr, data;
pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
n = where % 4;
byte_enables = byte_lane_enable_bits(n, size);
if (byte_enables == 0xffffffff)
return PCIBIOS_BAD_REGISTER_NUMBER;
addr = ixp4xx_config_addr(bus_num, devfn, where);
data = value << (8*n);
if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
/*
* Generalized PCI config access functions.
*/
static int ixp4xx_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *value)
{
if (bus->number && !PCI_SLOT(devfn))
return local_read_config(where, size, value);
return read_config(bus->number, devfn, where, size, value);
}
static int ixp4xx_write_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 value)
{
if (bus->number && !PCI_SLOT(devfn))
return local_write_config(where, size, value);
return write_config(bus->number, devfn, where, size, value);
}
struct pci_ops ixp4xx_ops = {
.read = ixp4xx_read_config,
.write = ixp4xx_write_config,
};
/*
* PCI abort handler
*/
static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
u32 isr, status;
isr = *PCI_ISR;
local_read_config(PCI_STATUS, 2, &status);
pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
"status = %#x\n", addr, isr, status);
/* make sure the Master Abort bit is reset */
*PCI_ISR = PCI_ISR_PFE;
status |= PCI_STATUS_REC_MASTER_ABORT;
local_write_config(PCI_STATUS, 2, status);
/*
* If it was an imprecise abort, then we need to correct the
* return address to be _after_ the instruction.
*/
if (fsr & (1 << 10))
regs->ARM_pc += 4;
return 0;
}
/*
* Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
*/
static int ixp4xx_pci_platform_notify(struct device *dev)
{
if(dev->bus == &pci_bus_type) {
*dev->dma_mask = SZ_64M - 1;
dev->coherent_dma_mask = SZ_64M - 1;
dmabounce_register_dev(dev, 2048, 4096);
}
return 0;
}
static int ixp4xx_pci_platform_notify_remove(struct device *dev)
{
if(dev->bus == &pci_bus_type) {
dmabounce_unregister_dev(dev);
}
return 0;
}
int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
{
return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
}
void __init ixp4xx_pci_preinit(void)
{
unsigned long processor_id;
asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
/*
* Determine which PCI read method to use
*/
if (!(processor_id & 0xf)) {
printk("PCI: IXP4xx A0 silicon detected - "
"PCI Non-Prefetch Workaround Enabled\n");
ixp4xx_pci_read = ixp4xx_pci_read_errata;
} else
ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
/* hook in our fault handler for PCI errors */
hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");
pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
/*
* We use identity AHB->PCI address translation
* in the 0x48000000 to 0x4bffffff address space
*/
*PCI_PCIMEMBASE = 0x48494A4B;
/*
* We also use identity PCI->AHB address translation
* in 4 16MB BARs that begin at the physical memory start
*/
*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
((PHYS_OFFSET & 0xFF000000) >> 8) +
((PHYS_OFFSET & 0xFF000000) >> 16) +
((PHYS_OFFSET & 0xFF000000) >> 24) +
0x00010203;
if (*PCI_CSR & PCI_CSR_HOST) {
printk("PCI: IXP4xx is host\n");
pr_debug("setup BARs in controller\n");
/*
* We configure the PCI inbound memory windows to be
* 1:1 mapped to SDRAM
*/
local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);
local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);
local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);
local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);
/*
* Enable CSR window at 0xff000000.
*/
local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);
/*
* Enable the IO window to be way up high, at 0xfffffc00
*/
local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
} else {
printk("PCI: IXP4xx is target - No bus scan performed\n");
}
printk("PCI: IXP4xx Using %s access for memory space\n",
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
"direct"
#else
"indirect"
#endif
);
pr_debug("clear error bits in ISR\n");
*PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
/*
* Set Initialize Complete in PCI Control Register: allow IXP4XX to
* respond to PCI configuration cycles. Specify that the AHB bus is
* operating in big endian mode. Set up byte lane swapping between
* little-endian PCI and the big-endian AHB bus
*/
#ifdef __ARMEB__
*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
#else
*PCI_CSR = PCI_CSR_IC;
#endif
pr_debug("DONE\n");
}
int ixp4xx_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
if (nr >= 1)
return 0;
res = kmalloc(sizeof(*res) * 2, GFP_KERNEL);
if (res == NULL) {
/*
* If we're out of memory this early, something is wrong,
* so we might as well catch it here.
*/
panic("PCI: unable to allocate resources?\n");
}
memset(res, 0, sizeof(*res) * 2);
local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
res[0].name = "PCI I/O Space";
res[0].start = 0x00001000;
res[0].end = 0xffff0000;
res[0].flags = IORESOURCE_IO;
res[1].name = "PCI Memory Space";
res[1].start = 0x48000000;
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
res[1].end = 0x4bffffff;
#else
res[1].end = 0x4fffffff;
#endif
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
platform_notify = ixp4xx_pci_platform_notify;
platform_notify_remove = ixp4xx_pci_platform_notify_remove;
return 1;
}
struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
}
/*
* We override these so we properly do dmabounce otherwise drivers
* are able to set the dma_mask to 0xffffffff and we can no longer
* trap bounces. :(
*
* We just return true on everyhing except for < 64MB in which case
* we will fail miseralby and die since we can't handle that case.
*/
int
pci_set_dma_mask(struct pci_dev *dev, u64 mask)
{
if (mask >= SZ_64M - 1 )
return 0;
return -EIO;
}
int
pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask)
{
if (mask >= SZ_64M - 1 )
return 0;
return -EIO;
}
int
pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
{
if (mask >= SZ_64M - 1 )
return 0;
return -EIO;
}
EXPORT_SYMBOL(pci_set_dma_mask);
EXPORT_SYMBOL(pci_dac_set_dma_mask);
EXPORT_SYMBOL(pci_set_consistent_dma_mask);
arch/arm/mach-ixp4xx/common.c 0 → 100644
View file @ 18857d8e
/*
* arch/arm/mach-ixp4xx/common.c
*
* Generic code shared across all IXP4XX platforms
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2002 (c) Intel Corporation
* Copyright 2003-2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/bootmem.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <asm/hardware.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
/*************************************************************************
* GPIO acces functions
*************************************************************************/
/*
* Configure GPIO line for input, interrupt, or output operation
*
* TODO: Enable/disable the irq_desc based on interrupt or output mode.
* TODO: Should these be named ixp4xx_gpio_?
*/
void gpio_line_config(u8 line, u32 style)
{
u32 enable;
volatile u32 *int_reg;
u32 int_style;
enable = *IXP4XX_GPIO_GPOER;
if (style & IXP4XX_GPIO_OUT) {
enable &= ~((1) << line);
} else if (style & IXP4XX_GPIO_IN) {
enable |= ((1) << line);
switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
{
case (IXP4XX_GPIO_ACTIVE_HIGH):
int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
break;
case (IXP4XX_GPIO_ACTIVE_LOW):
int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
break;
case (IXP4XX_GPIO_RISING_EDGE):
int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
break;
case (IXP4XX_GPIO_FALLING_EDGE):
int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
break;
case (IXP4XX_GPIO_TRANSITIONAL):
int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
break;
default:
int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
break;
}
if (line >= 8) { /* pins 8-15 */
line -= 8;
int_reg = IXP4XX_GPIO_GPIT2R;
}
else { /* pins 0-7 */
int_reg = IXP4XX_GPIO_GPIT1R;
}
/* Clear the style for the appropriate pin */
*int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
(line * IXP4XX_GPIO_STYLE_SIZE));
/* Set the new style */
*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
}
*IXP4XX_GPIO_GPOER = enable;
}
EXPORT_SYMBOL(gpio_line_config);
/*************************************************************************
* IXP4xx chipset I/O mapping
*************************************************************************/
static struct map_desc ixp4xx_io_desc[] __initdata = {
{ /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
.virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
.physical = IXP4XX_PERIPHERAL_BASE_PHYS,
.length = IXP4XX_PERIPHERAL_REGION_SIZE,
.type = MT_DEVICE
}, { /* Expansion Bus Config Registers */
.virtual = IXP4XX_EXP_CFG_BASE_VIRT,
.physical = IXP4XX_EXP_CFG_BASE_PHYS,
.length = IXP4XX_EXP_CFG_REGION_SIZE,
.type = MT_DEVICE
}, { /* PCI Registers */
.virtual = IXP4XX_PCI_CFG_BASE_VIRT,
.physical = IXP4XX_PCI_CFG_BASE_PHYS,
.length = IXP4XX_PCI_CFG_REGION_SIZE,
.type = MT_DEVICE
}
};
void __init ixp4xx_map_io(void)
{
iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
}
/*************************************************************************
* IXP4xx chipset IRQ handling
*
* TODO: GPIO IRQs should be marked invalid until the user of the IRQ
* (be it PCI or something else) configures that GPIO line
* as an IRQ. Also, we should use a different chip structure for
* level-based GPIO vs edge-based GPIO. Currently nobody needs this as
* all HW that's publically available uses level IRQs, so we'll
* worry about it if/when we have HW to test.
**************************************************************************/
static void ixp4xx_irq_mask(unsigned int irq)
{
*IXP4XX_ICMR &= ~(1 << irq);
}
static void ixp4xx_irq_mask_ack(unsigned int irq)
{
ixp4xx_irq_mask(irq);
}
static void ixp4xx_irq_unmask(unsigned int irq)
{
static int irq2gpio[NR_IRQS] = {
-1, -1, -1, -1, -1, -1, 0, 1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11, 12, -1, -1,
};
int line = irq2gpio[irq];
/*
* This only works for LEVEL gpio IRQs as per the IXP4xx developer's
* manual. If edge-triggered, need to move it to the mask_ack.
* Nobody seems to be using the edge-triggered mode on the GPIOs.
*/
if (line > 0)
gpio_line_isr_clear(line);
*IXP4XX_ICMR |= (1 << irq);
}
static struct irqchip ixp4xx_irq_chip = {
.ack = ixp4xx_irq_mask_ack,
.mask = ixp4xx_irq_mask,
.unmask = ixp4xx_irq_unmask,
};
void __init ixp4xx_init_irq(void)
{
int i = 0;
/* Route all sources to IRQ instead of FIQ */
*IXP4XX_ICLR = 0x0;
/* Disable all interrupt */
*IXP4XX_ICMR = 0x0;
for(i = 0; i < NR_IRQS; i++)
{
set_irq_chip(i, &ixp4xx_irq_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID);
}
}
/*************************************************************************
* IXP4xx timer tick
* We use OS timer1 on the CPU for the timer tick and the timestamp
* counter as a source of real clock ticks to account for missed jiffies.
*************************************************************************/
static unsigned volatile last_jiffy_time;
#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC)
/* IRQs are disabled before entering here from do_gettimeofday() */
static unsigned long ixp4xx_gettimeoffset(void)
{
u32 elapsed;
elapsed = *IXP4XX_OSTS - last_jiffy_time;
return elapsed / CLOCK_TICKS_PER_USEC;
}
static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
/* Clear Pending Interrupt by writing '1' to it */
*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
/*
* Catch up with the real idea of time
*/
do {
do_timer(regs);
last_jiffy_time += LATCH;
} while((*IXP4XX_OSTS - last_jiffy_time) > LATCH);
return IRQ_HANDLED;
}
extern unsigned long (*gettimeoffset)(void);
static struct irqaction timer_irq = {
.name = "IXP4xx Timer Tick",
.flags = SA_INTERRUPT
};
void __init time_init(void)
{
gettimeoffset = ixp4xx_gettimeoffset;
timer_irq.handler = ixp4xx_timer_interrupt;
/* Clear Pending Interrupt by writing '1' to it */
*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
/* Setup the Timer counter value */
*IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
/* Reset time-stamp counter */
*IXP4XX_OSTS = 0;
last_jiffy_time = 0;
/* Connect the interrupt handler and enable the interrupt */
setup_irq(IRQ_IXP4XX_TIMER1, &timer_irq);
}
arch/arm/mach-ixp4xx/coyote-pci.c 0 → 100644
View file @ 18857d8e
/*
* arch/arch/mach-ixp4xx/coyote-pci.c
*
* PCI setup routines for ADI Engineering Coyote platform
*
* Copyright (C) 2002 Jungo Software Technologies.
* Copyright (C) 2003 MontaVista Softwrae, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
extern void ixp4xx_pci_preinit(void);
extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
void __init coyote_pci_preinit(void)
{
gpio_line_config(COYOTE_PCI_SLOT0_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_config(COYOTE_PCI_SLOT1_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN);
gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN);
ixp4xx_pci_preinit();
}
static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == COYOTE_PCI_SLOT0_DEVID)
return IRQ_COYOTE_PCI_SLOT0;
else if (slot == COYOTE_PCI_SLOT1_DEVID)
return IRQ_COYOTE_PCI_SLOT1;
else return -1;
}
struct hw_pci coyote_pci __initdata = {
.nr_controllers = 1,
.preinit = coyote_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = coyote_map_irq,
};
int __init coyote_pci_init(void)
{
if (machine_is_adi_coyote())
pci_common_init(&coyote_pci);
return 0;
}
subsys_initcall(coyote_pci_init);
arch/arm/mach-ixp4xx/coyote-setup.c 0 → 100644
View file @ 18857d8e
/*
* arch/arm/mach-ixp4xx/coyote-setup.c
*
* ADI Engineering Coyote board-setup
*
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#ifdef __ARMEB__
#define REG_OFFSET 3
#else
#define REG_OFFSET 0
#endif
/*
* Only one serial port is connected on the Coyote.
*/
static struct uart_port coyote_serial_port = {
.membase = (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
.mapbase = (IXP4XX_UART2_BASE_PHYS),
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
.line = 0,
.type = PORT_XSCALE,
.fifosize = 32
};
void __init coyote_map_io(void)
{
early_serial_setup(&coyote_serial_port);
ixp4xx_map_io();
}
static struct flash_platform_data coyote_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource coyote_flash_resource = {
.start = COYOTE_FLASH_BASE,
.end = COYOTE_FLASH_BASE + COYOTE_FLASH_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device coyote_flash_device = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &coyote_flash_data,
},
.num_resources = 1,
.resource = &coyote_flash_resource,
};
static void __init coyote_init(void)
{
platform_add_device(&coyote_flash_device);
}
MACHINE_START(ADI_COYOTE, "ADI Engineering IXP4XX Coyote Development Platform")
MAINTAINER("MontaVista Software, Inc.")
BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
IXP4XX_PERIPHERAL_BASE_VIRT)
MAPIO(coyote_map_io)
INITIRQ(ixp4xx_init_irq)
BOOT_PARAMS(0x0100)
INIT_MACHINE(coyote_init)
MACHINE_END
arch/arm/mach-ixp4xx/ixdp425-pci.c 0 → 100644
View file @ 18857d8e
/*
* arch/arm/mach-ixp4xx/ixdp425-pci.c
*
* IXDP425 board-level PCI initialization
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/config.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/mach/pci.h>
#include <asm/irq.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
void __init ixdp425_pci_preinit(void)
{
gpio_line_config(IXDP425_PCI_INTA_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_config(IXDP425_PCI_INTB_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_config(IXDP425_PCI_INTC_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_config(IXDP425_PCI_INTD_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_isr_clear(IXDP425_PCI_INTA_PIN);
gpio_line_isr_clear(IXDP425_PCI_INTB_PIN);
gpio_line_isr_clear(IXDP425_PCI_INTC_PIN);
gpio_line_isr_clear(IXDP425_PCI_INTD_PIN);
ixp4xx_pci_preinit();
}
static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = {
IRQ_IXDP425_PCI_INTA,
IRQ_IXDP425_PCI_INTB,
IRQ_IXDP425_PCI_INTC,
IRQ_IXDP425_PCI_INTD
};
int irq = -1;
if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV &&
pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) {
irq = pci_irq_table[(slot + pin - 2) % 4];
}
return irq;
}
struct hw_pci ixdp425_pci __initdata = {
.nr_controllers = 1,
.preinit = ixdp425_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = ixdp425_map_irq,
};
int __init ixdp425_pci_init(void)
{
if (machine_is_ixdp425() ||
machine_is_ixcdp1100() ||
machine_is_avila())
pci_common_init(&ixdp425_pci);
return 0;
}
subsys_initcall(ixdp425_pci_init);
arch/arm/mach-ixp4xx/ixdp425-setup.c 0 → 100644
View file @ 18857d8e
/*
* arch/arm/mach-ixp4xx/ixdp425-setup.c
*
* IXDP425/IXCDP1100 board-setup
*
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#ifdef __ARMEB__
#define REG_OFFSET 3
#else
#define REG_OFFSET 0
#endif
/*
* IXDP425 uses both chipset serial ports
*/
static struct uart_port ixdp425_serial_ports[] = {
{
.membase = (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET),
.mapbase = (IXP4XX_UART1_BASE_PHYS),
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
.line = 0,
.type = PORT_XSCALE,
.fifosize = 32
} , {
.membase = (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
.mapbase = (IXP4XX_UART2_BASE_PHYS),
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
.line = 1,
.type = PORT_XSCALE,
.fifosize = 32
}
};
void __init ixdp425_map_io(void)
{
early_serial_setup(&ixdp425_serial_ports[0]);
early_serial_setup(&ixdp425_serial_ports[1]);
ixp4xx_map_io();
}
static struct flash_platform_data ixdp425_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource ixdp425_flash_resource = {
.start = IXDP425_FLASH_BASE,
.end = IXDP425_FLASH_BASE + IXDP425_FLASH_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device ixdp425_flash_device = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &ixdp425_flash_data,
},
.num_resources = 1,
.resource = &ixdp425_flash_resource,
};
static struct ixp4xx_i2c_pins ixdp425_i2c_gpio_pins = {
.sda_pin = IXDP425_SDA_PIN,
.scl_pin = IXDP425_SCL_PIN,
};
static struct platform_device ixdp425_i2c_controller = {
.name = "IXP4XX-I2C",
.id = 0,
.dev = {
.platform_data = &ixdp425_i2c_gpio_pins,
},
.num_resources = 0
};
static void __init ixdp425_init(void)
{
platform_add_device(&ixdp425_flash_device);
platform_add_device(&ixdp425_i2c_controller);
}
MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
MAINTAINER("MontaVista Software, Inc.")
BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
IXP4XX_PERIPHERAL_BASE_VIRT)
MAPIO(ixdp425_map_io)
INITIRQ(ixp4xx_init_irq)
BOOT_PARAMS(0x0100)
INIT_MACHINE(ixdp425_init)
MACHINE_END
MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
MAINTAINER("MontaVista Software, Inc.")
BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
IXP4XX_PERIPHERAL_BASE_VIRT)
MAPIO(ixdp425_map_io)
INITIRQ(ixp4xx_init_irq)
BOOT_PARAMS(0x0100)
INIT_MACHINE(ixdp425_init)
MACHINE_END
/*
* Avila is functionally equivalent to IXDP425 except that it adds
* a CF IDE slot hanging off the expansion bus. When we have a
* driver for IXP4xx CF IDE with driver model support we'll move
* Avila to it's own setup file.
*/
#ifdef CONFIG_ARCH_AVILA
MACHINE_START(AVILA, "Gateworks Avila Network Platform")
MAINTAINER("Deepak Saxena <dsaxena@plexity.net>")
BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
IXP4XX_PERIPHERAL_BASE_VIRT)
MAPIO(ixdp425_map_io)
INITIRQ(ixp4xx_init_irq)
BOOT_PARAMS(0x0100)
INIT_MACHINE(ixdp425_init)
MACHINE_END
#endif
arch/arm/mach-ixp4xx/prpmc1100-pci.c 0 → 100644
View file @ 18857d8e
/*
* arch/arm/mach-ixp4xx/prpmc1100-pci.c
*
* PrPMC1100 PCI initialization
*
* Copyright (C) 2003-2004 MontaVista Sofwtare, Inc.
* Based on IXDP425 code originally (C) Intel Corporation
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* PrPMC1100 PCI init code. GPIO usage is similar to that on
* IXDP425, but the IRQ routing is completely different and
* depends on what carrier you are using. This code is written
* to work on the Motorola PrPMC800 ATX carrier board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/config.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/hardware.h>
#include <asm/mach/pci.h>
void __init prpmc1100_pci_preinit(void)
{
gpio_line_config(PRPMC1100_PCI_INTA_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_config(PRPMC1100_PCI_INTB_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_config(PRPMC1100_PCI_INTC_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_config(PRPMC1100_PCI_INTD_PIN,
IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
gpio_line_isr_clear(PRPMC1100_PCI_INTA_PIN);
gpio_line_isr_clear(PRPMC1100_PCI_INTB_PIN);
gpio_line_isr_clear(PRPMC1100_PCI_INTC_PIN);
gpio_line_isr_clear(PRPMC1100_PCI_INTD_PIN);
ixp4xx_pci_preinit();
}
static int __init prpmc1100_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = -1;
static int pci_irq_table[][4] = {
{ /* IDSEL 16 - PMC A1 */
IRQ_PRPMC1100_PCI_INTD,
IRQ_PRPMC1100_PCI_INTA,
IRQ_PRPMC1100_PCI_INTB,
IRQ_PRPMC1100_PCI_INTC
}, { /* IDSEL 17 - PRPMC-A-B */
IRQ_PRPMC1100_PCI_INTD,
IRQ_PRPMC1100_PCI_INTA,
IRQ_PRPMC1100_PCI_INTB,
IRQ_PRPMC1100_PCI_INTC
}, { /* IDSEL 18 - PMC A1-B */
IRQ_PRPMC1100_PCI_INTA,
IRQ_PRPMC1100_PCI_INTB,
IRQ_PRPMC1100_PCI_INTC,
IRQ_PRPMC1100_PCI_INTD
}, { /* IDSEL 19 - Unused */
0, 0, 0, 0
}, { /* IDSEL 20 - P2P Bridge */
IRQ_PRPMC1100_PCI_INTA,
IRQ_PRPMC1100_PCI_INTB,
IRQ_PRPMC1100_PCI_INTC,
IRQ_PRPMC1100_PCI_INTD
}, { /* IDSEL 21 - PMC A2 */
IRQ_PRPMC1100_PCI_INTC,
IRQ_PRPMC1100_PCI_INTD,
IRQ_PRPMC1100_PCI_INTA,
IRQ_PRPMC1100_PCI_INTB
}, { /* IDSEL 22 - PMC A2-B */
IRQ_PRPMC1100_PCI_INTD,
IRQ_PRPMC1100_PCI_INTA,
IRQ_PRPMC1100_PCI_INTB,
IRQ_PRPMC1100_PCI_INTC
},
};
if (slot >= PRPMC1100_PCI_MIN_DEVID && slot <= PRPMC1100_PCI_MAX_DEVID
&& pin >= 1 && pin <= PRPMC1100_PCI_IRQ_LINES) {
irq = pci_irq_table[slot - PRPMC1100_PCI_MIN_DEVID][pin - 1];
}
return irq;
}
struct hw_pci prpmc1100_pci __initdata = {
.nr_controllers = 1,
.preinit = prpmc1100_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = prpmc1100_map_irq,
};
int __init prpmc1100_pci_init(void)
{
if (machine_is_prpmc1100())
pci_common_init(&prpmc1100_pci);
return 0;
}
subsys_initcall(prpmc1100_pci_init);
arch/arm/mach-ixp4xx/prpmc1100-setup.c 0 → 100644
View file @ 18857d8e
/*
* arch/arm/mach-ixp4xx/prpmc1100-setup.c
*
* Motorola PrPMC1100 board setup
*
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#ifdef __ARMEB__
#define REG_OFFSET 3
#else
#define REG_OFFSET 0
#endif
/*
* Only one serial port is connected on the PrPMC1100
*/
static struct uart_port prpmc1100_serial_port = {
.membase = (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET),
.mapbase = (IXP4XX_UART1_BASE_PHYS),
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
.line = 0,
.type = PORT_XSCALE,
.fifosize = 32
};
void __init prpmc1100_map_io(void)
{
early_serial_setup(&prpmc1100_serial_port);
ixp4xx_map_io();
}
static struct flash_platform_data prpmc1100_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource prpmc1100_flash_resource = {
.start = PRPMC1100_FLASH_BASE,
.end = PRPMC1100_FLASH_BASE + PRPMC1100_FLASH_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device prpmc1100_flash_device = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &prpmc1100_flash_data,
},
.num_resources = 1,
.resource = &prpmc1100_flash_resource,
};
static void __init prpmc1100_init(void)
{
platform_add_device(&prpmc1100_flash_device);
}
MACHINE_START(PRPMC1100, "Motorola PrPMC1100")
MAINTAINER("MontaVista Software, Inc.")
BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
IXP4XX_PERIPHERAL_BASE_VIRT)
MAPIO(prpmc1100_map_io)
INITIRQ(ixp4xx_init_irq)
BOOT_PARAMS(0x0100)
INIT_MACHINE(prpmc1100_init)
MACHINE_END
arch/arm/mach-omap/innovator1510.c deleted 100644 → 0
View file @ 73b5d164
/*
* linux/arch/arm/mach-omap/innovator1510.c
*
* Board specific inits for OMAP-1510 Innovator
*
* Copyright (C) 2001 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* Copyright (C) 2002 MontaVista Software, Inc.
*
* Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
* Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/hardware.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/clocks.h>
#include <asm/arch/gpio.h>
#include <asm/arch/fpga.h>
#include "common.h"
extern int omap_gpio_init(void);
void innovator_init_irq(void)
{
omap_init_irq();
omap_gpio_init();
fpga_init_irq();
}
static struct resource smc91x_resources[] = {
[0] = {
.start = OMAP1510P1_FPGA_ETHR_START, /* Physical */
.end = OMAP1510P1_FPGA_ETHR_START + 16,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_ETHER,
.end = INT_ETHER,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct platform_device *devices[] __initdata = {
&smc91x_device,
};
static void __init innovator_init(void)
{
if (!machine_is_innovator())
return;
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc innovator_io_desc[] __initdata = {
{ OMAP1510P1_FPGA_BASE, OMAP1510P1_FPGA_START, OMAP1510P1_FPGA_SIZE,
MT_DEVICE },
};
static void __init innovator_map_io(void)
{
omap_map_io();
iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc));
/* Dump the Innovator FPGA rev early - useful info for support. */
printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
fpga_read(OMAP1510P1_FPGA_REV_HIGH),
fpga_read(OMAP1510P1_FPGA_REV_LOW),
fpga_read(OMAP1510P1_FPGA_BOARD_REV));
}
MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1510")
MAINTAINER("MontaVista Software, Inc.")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_PARAMS(0x10000100)
MAPIO(innovator_map_io)
INITIRQ(innovator_init_irq)
INIT_MACHINE(innovator_init)
MACHINE_END
arch/arm/mach-omap/innovator1610.c deleted 100644 → 0
View file @ 73b5d164
/*
* linux/arch/arm/mach-omap/innovator1610.c
*
* This file contains Innovator-specific code.
*
* Copyright (C) 2002 MontaVista Software, Inc.
*
* Copyright (C) 2001 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/hardware.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/irqs.h>
#include "common.h"
void
innovator_init_irq(void)
{
omap_init_irq();
}
static struct resource smc91x_resources[] = {
[0] = {
.start = OMAP1610_ETHR_START, /* Physical */
.end = OMAP1610_ETHR_START + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0, /* Really GPIO 0 */
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct platform_device *devices[] __initdata = {
&smc91x_device,
};
static void __init innovator_init(void)
{
if (!machine_is_innovator())
return;
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
static struct map_desc innovator_io_desc[] __initdata = {
{ OMAP1610_ETHR_BASE, OMAP1610_ETHR_START, OMAP1610_ETHR_SIZE,MT_DEVICE },
{ OMAP1610_NOR_FLASH_BASE, OMAP1610_NOR_FLASH_START, OMAP1610_NOR_FLASH_SIZE,
MT_DEVICE },
};
static void __init innovator_map_io(void)
{
omap_map_io();
iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc));
}
MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1610")
MAINTAINER("MontaVista Software, Inc.")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_PARAMS(0x10000100)
MAPIO(innovator_map_io)
INITIRQ(innovator_init_irq)
INIT_MACHINE(innovator_init)
MACHINE_END
arch/arm/mach-omap/omap-generic.c deleted 100644 → 0
View file @ 73b5d164
/*
* linux/arch/arm/mach-omap/generic.c
*
* Modified from innovator.c
*
* Code for generic OMAP board. Should work on many OMAP systems where
* the device drivers take care of all the necessary hardware initialization.
* Do not put any board specific code to this file; create a new machine
* type if you need custom low-level initializations.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/hardware.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/clocks.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include "common.h"
static void __init omap_generic_init_irq(void)
{
omap_init_irq();
}
/*
* Muxes the serial ports on
*/
static void __init omap_early_serial_init(void)
{
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
omap_cfg_reg(UART2_TX);
omap_cfg_reg(UART2_RTS);
omap_cfg_reg(UART3_TX);
omap_cfg_reg(UART3_RX);
}
static void __init omap_generic_init(void)
{
if (!machine_is_omap_generic())
return;
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
if (cpu_is_omap1510()) {
omap_early_serial_init();
}
}
static void __init omap_generic_map_io(void)
{
omap_map_io();
}
MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610")
MAINTAINER("Tony Lindgren <tony@atomide.com>")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_PARAMS(0x10000100)
MAPIO(omap_generic_map_io)
INITIRQ(omap_generic_init_irq)
INIT_MACHINE(omap_generic_init)
MACHINE_END
arch/arm/mach-omap/omap-perseus2.c deleted 100644 → 0
View file @ 73b5d164
/*
* linux/arch/arm/mach-omap/omap-perseus2.c
*
* Modified from omap-generic.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/hardware.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/clocks.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include <asm/arch/omap-perseus2.h>
#include "common.h"
void omap_perseus2_init_irq(void)
{
omap_init_irq();
}
static struct resource smc91x_resources[] = {
[0] = {
.start = OMAP730_FPGA_ETHR_START, /* Physical */
.end = OMAP730_FPGA_ETHR_START + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0,
.end = 0,
.flags = INT_ETHER,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct platform_device *devices[] __initdata = {
&smc91x_device,
};
static void __init omap_perseus2_init(void)
{
if (!machine_is_omap_perseus2())
return;
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_perseus2_io_desc[] __initdata = {
{OMAP730_FPGA_BASE, OMAP730_FPGA_START, OMAP730_FPGA_SIZE,
MT_DEVICE},
};
static void __init omap_perseus2_map_io(void)
{
omap_map_io();
iotable_init(omap_perseus2_io_desc,
ARRAY_SIZE(omap_perseus2_io_desc));
/* Early, board-dependent init */
/*
* Hold GSM Reset until needed
*/
*DSP_M_CTL &= ~1;
/*
* UARTs -> done automagically by 8250 driver
*/
/*
* CSx timings, GPIO Mux ... setup
*/
/* Flash: CS0 timings setup */
*((volatile __u32 *) OMAP_FLASH_CFG_0) = 0x0000fff3;
*((volatile __u32 *) OMAP_FLASH_ACFG_0) = 0x00000088;
/*
* Ethernet support trough the debug board
* CS1 timings setup
*/
*((volatile __u32 *) OMAP_FLASH_CFG_1) = 0x0000fff3;
*((volatile __u32 *) OMAP_FLASH_ACFG_1) = 0x00000000;
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
*((volatile __u32 *) PERSEUS2_IO_CONF_9) &= 0x1FFFFFFF;
}
MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
MAINTAINER("Kevin Hilman <k-hilman@ti.com>")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_PARAMS(0x10000100)
MAPIO(omap_perseus2_map_io)
INITIRQ(omap_perseus2_init_irq)
INIT_MACHINE(omap_perseus2_init)
MACHINE_END
arch/arm/mach-pxa/Kconfig
View file @ 18857d8e
menu "Intel PXA250/210 Implementations"
menu "Intel PXA2xx Implementations"
config ARCH_LUBBOCK
bool "Intel DBPXA250 Development Platform"
depends on ARCH_PXA
select PXA25x
config ARCH_PXA_IDP
bool "Accelent Xscale IDP"
depends on ARCH_PXA
select PXA25x
endmenu
config PXA25x
bool
help
Select code specific to PXA21x/25x/26x variants
config PXA27x
bool
help
Select code specific to PXA27x variants
arch/arm/mach-pxa/Makefile
View file @ 18857d8e
......@@ -4,6 +4,8 @@
# Common support (must be linked before board specific support)
obj-y += generic.o irq.o dma.o
obj-$(CONFIG_PXA25x) += pxa25x.o
obj-$(CONFIG_PXA27x) += pxa27x.o
# Specific board support
obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
......
arch/arm/mach-pxa/dma.c
View file @ 18857d8e
......@@ -28,7 +28,7 @@ static struct dma_channel {
char *name;
void (*irq_handler)(int, void *, struct pt_regs *);
void *data;
} dma_channels[16];
} dma_channels[PXA_DMA_CHANNELS];
int pxa_request_dma (char *name, pxa_dma_prio prio,
......@@ -45,7 +45,7 @@ int pxa_request_dma (char *name, pxa_dma_prio prio,
local_irq_save(flags);
/* try grabbing a DMA channel with the requested priority */
for (i = prio; i < prio + (prio == DMA_PRIO_LOW) ? 8 : 4; i++) {
for (i = prio; i < prio + PXA_DMA_NBCH(prio); i++) {
if (!dma_channels[i].name) {
found = 1;
break;
......@@ -97,7 +97,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
{
int i, dint = DINT;
for (i = 0; i < 16; i++) {
for (i = 0; i < PXA_DMA_CHANNELS; i++) {
if (dint & (1 << i)) {
struct dma_channel *channel = &dma_channels[i];
if (channel->name && channel->irq_handler) {
......
arch/arm/mach-pxa/generic.c
View file @ 18857d8e
......@@ -31,76 +31,10 @@
#include <asm/mach/map.h>
#include <asm/arch/udc.h>
#include <asm/arch/pxafb.h>
#include "generic.h"
/*
* Various clock factors driven by the CCCR register.
*/
/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
/* Crystal clock */
#define BASE_CLK 3686400
/*
* Get the clock frequency as reflected by CCCR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*/
unsigned int get_clk_frequency_khz(int info)
{
unsigned long cccr, turbo;
unsigned int l, L, m, M, n2, N;
cccr = CCCR;
asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
l = L_clk_mult[(cccr >> 0) & 0x1f];
m = M_clk_mult[(cccr >> 5) & 0x03];
n2 = N2_clk_mult[(cccr >> 7) & 0x07];
L = l * BASE_CLK;
M = m * L;
N = n2 * M / 2;
if(info)
{
L += 5000;
printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
L / 1000000, (L % 1000000) / 10000, l );
M += 5000;
printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
M / 1000000, (M % 1000000) / 10000, m );
N += 5000;
printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
(turbo & 1) ? "" : "in" );
}
return (turbo & 1) ? (N/1000) : (M/1000);
}
EXPORT_SYMBOL(get_clk_frequency_khz);
/*
* Return the current lclk requency in units of 10kHz
*/
unsigned int get_lclk_frequency_10khz(void)
{
return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
}
EXPORT_SYMBOL(get_lclk_frequency_10khz);
/*
* Handy function to set GPIO alternate functions
*/
......@@ -125,16 +59,21 @@ void pxa_gpio_mode(int gpio_mode)
EXPORT_SYMBOL(pxa_gpio_mode);
/*
* Note that 0xfffe0000-0xffffffff is reserved for the vector table and
* cache flush area.
* Intel PXA2xx internal register mapping.
*
* Note 1: not all PXA2xx variants implement all those addresses.
*
* Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
* and cache flush area.
*/
static struct map_desc standard_io_desc[] __initdata = {
/* virtual physical length type */
{ 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */
{ 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */
{ 0xf8000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */
{ 0xfa000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
{ 0xfc000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
{ 0xf2000000, 0x40000000, 0x01800000, MT_DEVICE }, /* Devs */
{ 0xf4000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
{ 0xf6000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
{ 0xf8000000, 0x4c000000, 0x00100000, MT_DEVICE }, /* USB host */
{ 0xfa000000, 0x50000000, 0x00100000, MT_DEVICE }, /* Camera */
{ 0xfe000000, 0x58000000, 0x00100000, MT_DEVICE }, /* IMem ctl */
{ 0xff000000, 0x00000000, 0x00100000, MT_DEVICE } /* UNCACHED_PHYS_0 */
};
......@@ -205,9 +144,45 @@ static struct platform_device udc_device = {
}
};
static struct pxafb_mach_info pxa_fb_info;
void __init set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info)
{
memcpy(&pxa_fb_info,hard_pxa_fb_info,sizeof(struct pxafb_mach_info));
}
EXPORT_SYMBOL(set_pxa_fb_info);
static struct resource pxafb_resources[] = {
[0] = {
.start = 0x44000000,
.end = 0x4400ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD,
.end = IRQ_LCD,
.flags = IORESOURCE_IRQ,
},
};
static u64 fb_dma_mask = ~(u64)0;
static struct platform_device pxafb_device = {
.name = "pxafb",
.id = 0,
.dev = {
.platform_data = &pxa_fb_info,
.dma_mask = &fb_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxafb_resources),
.resource = pxafb_resources,
};
static struct platform_device *devices[] __initdata = {
&pxamci_device,
&udc_device,
&pxafb_device,
};
static int __init pxa_init(void)
......
arch/arm/mach-pxa/pm.c
View file @ 18857d8e
......@@ -32,6 +32,11 @@ extern void pxa_cpu_resume(void);
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
#define RESTORE_GPLEVEL(n) do { \
GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
} while (0)
/*
* List of global PXA peripheral registers to preserve.
* More ones like CP and general purpose register values are preserved
......@@ -42,16 +47,13 @@ enum { SLEEP_SAVE_START = 0,
SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L,
SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U,
SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR,
SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR,
SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,
SLEEP_SAVE_ICMR,
SLEEP_SAVE_CKEN,
......@@ -74,21 +76,6 @@ static int pxa_pm_enter(u32 state)
/* preserve current time */
delta = xtime.tv_sec - RCNR;
/*
* Temporary solution. This won't be necessary once
* we move pxa support into the serial driver
* Save the FF UART
*/
SAVE(FFIER);
SAVE(FFLCR);
SAVE(FFMCR);
SAVE(FFSPR);
SAVE(FFISR);
FFLCR |= 0x80;
SAVE(FFDLL);
SAVE(FFDLH);
FFLCR &= 0xef;
/* save vital registers */
SAVE(OSCR);
SAVE(OSMR0);
......@@ -97,6 +84,7 @@ static int pxa_pm_enter(u32 state)
SAVE(OSMR3);
SAVE(OIER);
SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
......@@ -146,14 +134,15 @@ static int pxa_pm_enter(u32 state)
PSPR = 0;
/* restore registers */
RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
RESTORE(GAFR0_L); RESTORE(GAFR0_U);
RESTORE(GAFR1_L); RESTORE(GAFR1_U);
RESTORE(GAFR2_L); RESTORE(GAFR2_U);
RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
PSSR = PSSR_PH;
PSSR = PSSR_RDH | PSSR_PH;
RESTORE(OSMR0);
RESTORE(OSMR1);
......@@ -168,22 +157,6 @@ static int pxa_pm_enter(u32 state)
ICCR = 1;
RESTORE(ICMR);
/*
* Temporary solution. This won't be necessary once
* we move pxa support into the serial driver.
* Restore the FF UART.
*/
RESTORE(FFMCR);
RESTORE(FFSPR);
RESTORE(FFLCR);
FFLCR |= 0x80;
RESTORE(FFDLH);
RESTORE(FFDLL);
RESTORE(FFLCR);
RESTORE(FFISR);
FFFCR = 0x07;
RESTORE(FFIER);
/* restore current time */
xtime.tv_sec = RCNR + delta;
......
arch/arm/mach-pxa/pxa25x.c 0 → 100644
View file @ 18857d8e
/*
* linux/arch/arm/mach-pxa/pxa25x.c
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* Code specific to PXA21x/25x/26x variants.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Since this file should be linked before any other machine specific file,
* the __initcall() here will be executed first. This serves as default
* initialization stuff for PXA machines which can be overridden later if
* need be.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <asm/hardware.h>
#include "generic.h"
/*
* Various clock factors driven by the CCCR register.
*/
/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
/* Crystal clock */
#define BASE_CLK 3686400
/*
* Get the clock frequency as reflected by CCCR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*/
unsigned int get_clk_frequency_khz(int info)
{
unsigned long cccr, turbo;
unsigned int l, L, m, M, n2, N;
cccr = CCCR;
asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
l = L_clk_mult[(cccr >> 0) & 0x1f];
m = M_clk_mult[(cccr >> 5) & 0x03];
n2 = N2_clk_mult[(cccr >> 7) & 0x07];
L = l * BASE_CLK;
M = m * L;
N = n2 * M / 2;
if(info)
{
L += 5000;
printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
L / 1000000, (L % 1000000) / 10000, l );
M += 5000;
printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
M / 1000000, (M % 1000000) / 10000, m );
N += 5000;
printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
(turbo & 1) ? "" : "in" );
}
return (turbo & 1) ? (N/1000) : (M/1000);
}
EXPORT_SYMBOL(get_clk_frequency_khz);
/*
* Return the current lclk requency in units of 10kHz
*/
unsigned int get_lclk_frequency_10khz(void)
{
return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
}
EXPORT_SYMBOL(get_lclk_frequency_10khz);
arch/arm/mach-pxa/pxa27x.c 0 → 100644
View file @ 18857d8e
/*
* linux/arch/arm/mach-pxa/pxa27x.c
*
* Author: Nicolas Pitre
* Created: Nov 05, 2002
* Copyright: MontaVista Software Inc.
*
* Code specific to PXA27x aka Bulverde.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <asm/hardware.h>
#include "generic.h"
/* Crystal clock : 13-MHZ*/
#define BASE_CLK 13000000
/*
* Get the clock frequency as reflected by CCSR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*
* For more details, refer to Bulverde Manual, section 3.8.2.1
*/
unsigned int get_clk_frequency_khz( int info)
{
unsigned long ccsr, turbo, b, ht;
unsigned int l, L, m, M, n2, N, S, cccra;
ccsr = CCSR;
cccra = CCCR & (0x1 << 25);
/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
b = (turbo & (0x1 << 3));
ht = (turbo & (0x1 << 2));
l = ccsr & 0x1f;
n2 = (ccsr>>7) & 0xf;
if (l == 31) {
/* The calculation from the Yellow Book is incorrect:
it says M=4 for L=21-30 (which is easy to calculate
by subtracting 1 and then dividing by 10, but not
with 31, so we'll do it manually */
m = 1 << 2;
} else {
m = 1 << ((l-1)/10);
}
L = l * BASE_CLK;
N = (n2 * L) / 2;
S = (b) ? L : (L/2);
if (cccra == 0)
M = L/m;
else
M = (b) ? L : (L/2);
if (info) {
printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
L / 1000000, (L % 1000000) / 10000, l );
printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
M / 1000000, (M % 1000000) / 10000, m );
printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
(turbo & 1) ? "" : "in" );
printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
S / 1000000, (S % 1000000) / 10000 );
}
return (turbo & 1) ? (N/1000) : (L/1000);
}
/*
* Return the current mem clock frequency in units of 10kHz as
* reflected by CCCR[A], B, and L
*/
unsigned int get_lclk_frequency_10khz(void)
{
unsigned long ccsr, clkcfg, b;
unsigned int l, L, m, M, cccra;
cccra = CCCR & (0x1 << 25);
/* Read clkcfg register to obtain b */
asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
b = (clkcfg & (0x1 << 3));
ccsr = CCSR;
l = ccsr & 0x1f;
if (l == 31) {
/* The calculation from the Yellow Book is incorrect:
it says M=4 for L=21-30 (which is easy to calculate
by subtracting 1 and then dividing by 10, but not
with 31, so we'll do it manually */
m = 1 << 2;
} else {
m = 1 << ((l-1)/10);
}
L = l * BASE_CLK;
if (cccra == 0)
M = L/m;
else
M = (b) ? L : L/2;
return (M / 10000);
}
EXPORT_SYMBOL(get_clk_frequency_khz);
EXPORT_SYMBOL(get_lclk_frequency_10khz);
arch/arm/mach-s3c2410/Kconfig
View file @ 18857d8e
......@@ -16,6 +16,13 @@ config ARCH_H1940
Say Y here if you are using the HP IPAQ H1940
<http://www.handhelds.org/projects/h1940.html>.
config ARCH_SMDK2410
bool "SMDK2410/A9M2410"
depends on ARCH_S3C2410
help
Say Y here if you are using the SMDK2410 or the derived module A9M2410
<http://www.fsforth.de>
config MACH_VR1000
bool "Simtec VR1000"
depends on ARCH_S3C2410
......
arch/arm/mach-s3c2410/Makefile
View file @ 18857d8e
......@@ -12,6 +12,7 @@ obj- :=
obj-$(CONFIG_ARCH_BAST) += mach-bast.o
obj-$(CONFIG_MACH_H1940) += mach-h1940.o
obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o
#obj-$(CONFIG_PCI) +=$(pci-y)
......
arch/arm/mach-s3c2410/mach-smdk2410.c 0 → 100644
View file @ 18857d8e
/***********************************************************************
*
* linux/arch/arm/mach-s3c2410/mach-smdk2410.c
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH
* All rights reserved.
*
* $Id: mach-smdk2410.c,v 1.1 2004/05/11 14:15:38 mpietrek Exp $
* @Author: Jonas Dietsche
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* @History:
* derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
* Ben Dooks <ben@simtec.co.uk>
***********************************************************************/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/arch/regs-serial.h>
#include "s3c2410.h"
static struct map_desc smdk2410_iodesc[] __initdata = {
/* nothing here yet */
};
#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
/* base baud rate for all our UARTs */
static unsigned long smdk2410_serial_clock = 24*1000*1000;
static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
[0] = {
.hwport = 0,
.flags = 0,
.clock = &smdk2410_serial_clock,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[1] = {
.hwport = 1,
.flags = 0,
.clock = &smdk2410_serial_clock,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[2] = {
.hwport = 2,
.flags = 0,
.clock = &smdk2410_serial_clock,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
}
};
void __init smdk2410_map_io(void)
{
s3c2410_map_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
s3c2410_uartcfgs = smdk2410_uartcfgs;
}
void __init smdk2410_init_irq(void)
{
s3c2410_init_irq();
}
MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
* to SMDK2410 */
MAINTAINER("Jonas Dietsche")
BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
MAPIO(smdk2410_map_io)
INITIRQ(smdk2410_init_irq)
MACHINE_END
arch/arm/mm/Kconfig
View file @ 18857d8e
......@@ -220,7 +220,7 @@ config CPU_SA1100
# XScale
config CPU_XSCALE
bool
depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA
depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA || ARCH_IXP4XX
default y
select CPU_32v5
select CPU_ABRT_EV5T
......
arch/arm/mm/blockops.c
View file @ 18857d8e
......@@ -133,7 +133,7 @@ static int __init blockops_check(void)
unsigned int cache_type;
int i;
asm("mcr p15, 0, %0, c0, c0, 1" : "=r" (cache_type));
asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_type));
printk("Checking V6 block cache operations:\n");
register_undef_hook(&blockops_hook);
......
arch/arm/mm/cache-v6.S
View file @ 18857d8e
......@@ -151,6 +151,7 @@ ENTRY(v6_dma_inv_range)
add r0, r0, #D_CACHE_LINE_SIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
......@@ -188,6 +189,7 @@ ENTRY(v6_dma_flush_range)
mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
#endif
add r0, r0, #D_CACHE_LINE_SIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
......
arch/arm/mm/mm-armv.c
View file @ 18857d8e
......@@ -305,27 +305,27 @@ static struct mem_types mem_types[] __initdata = {
[MT_DEVICE] = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_WRITE,
.prot_l1 = PMD_TYPE_TABLE | PMD_BIT4,
.prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
PMD_SECT_AP_WRITE,
.domain = DOMAIN_IO,
},
[MT_CACHECLEAN] = {
.prot_sect = PMD_TYPE_SECT | PMD_BIT4,
.prot_sect = PMD_TYPE_SECT,
.domain = DOMAIN_KERNEL,
},
[MT_MINICLEAN] = {
.prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE,
.domain = DOMAIN_KERNEL,
},
[MT_VECTORS] = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_EXEC,
.prot_l1 = PMD_TYPE_TABLE | PMD_BIT4,
.prot_l1 = PMD_TYPE_TABLE,
.domain = DOMAIN_USER,
},
[MT_MEMORY] = {
.prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
.domain = DOMAIN_KERNEL,
}
};
......@@ -353,6 +353,15 @@ static void __init build_mem_type_table(void)
ecc_mask = 0;
}
if (cpu_arch <= CPU_ARCH_ARMv5) {
mem_types[MT_DEVICE].prot_l1 |= PMD_BIT4;
mem_types[MT_DEVICE].prot_sect |= PMD_BIT4;
mem_types[MT_CACHECLEAN].prot_sect |= PMD_BIT4;
mem_types[MT_MINICLEAN].prot_sect |= PMD_BIT4;
mem_types[MT_VECTORS].prot_l1 |= PMD_BIT4;
mem_types[MT_MEMORY].prot_sect |= PMD_BIT4;
}
/*
* ARMv6 and above have extended page tables.
*/
......@@ -482,6 +491,7 @@ void setup_mm_for_reboot(char mode)
pgd_t *pgd;
pmd_t *pmd;
int i;
int cpu_arch = cpu_architecture();
if (current->mm && current->mm->pgd)
pgd = current->mm->pgd;
......@@ -491,7 +501,9 @@ void setup_mm_for_reboot(char mode)
for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) {
pmdval = (i << PGDIR_SHIFT) |
PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
PMD_BIT4 | PMD_TYPE_SECT;
PMD_TYPE_SECT;
if (cpu_arch <= CPU_ARCH_ARMv5)
pmdval |= PMD_BIT4;
pmd = pmd_offset(pgd + i, i << PGDIR_SHIFT);
set_pmd(pmd, __pmd(pmdval));
}
......
arch/arm/mm/proc-xscale.S
View file @ 18857d8e
......@@ -298,7 +298,7 @@ ENTRY(xscale_dma_inv_range)
add r0, r0, #CACHELINESIZE
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 1 @ Drain Write (& Fill) Buffer
mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr
/*
......@@ -315,7 +315,7 @@ ENTRY(xscale_dma_clean_range)
add r0, r0, #CACHELINESIZE
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 1 @ Drain Write (& Fill) Buffer
mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr
/*
......@@ -333,7 +333,7 @@ ENTRY(xscale_dma_flush_range)
add r0, r0, #CACHELINESIZE
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 1 @ Drain Write (& Fill) Buffer
mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr
ENTRY(xscale_cache_fns)
......@@ -647,6 +647,11 @@ cpu_pxa210_name:
.asciz "XScale-PXA210"
.size cpu_pxa210_name, . - cpu_pxa210_name
.type cpu_ixp42x_name, #object
cpu_ixp42x_name:
.asciz "XScale-IXP42x Family"
.size cpu_ixp42x_name, . - cpu_ixp42x_name
.type cpu_pxa255_name, #object
cpu_pxa255_name:
.asciz "XScale-PXA255"
......@@ -725,6 +730,22 @@ __pxa210_proc_info:
.long xscale_cache_fns
.size __pxa210_proc_info, . - __pxa210_proc_info
.type __ixp42x_proc_info, #object
__ixp42x_proc_info:
.long 0x690541c0
.long 0xffffffc0
.long 0x00000c0e
b __xscale_setup
.long cpu_arch_name
.long cpu_elf_name
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
.long cpu_ixp42x_name
.long xscale_processor_functions
.long v4wbi_tlb_fns
.long xscale_mc_user_fns
.long xscale_cache_fns
.size __ixp42x_proc_info, . - __ixp42x_proc_info
.type __pxa255_proc_info,#object
__pxa255_proc_info:
.long 0x69052d00
......
drivers/video/Kconfig
View file @ 18857d8e
......@@ -923,6 +923,37 @@ config FB_68328
Say Y here if you want to support the built-in frame buffer of
the Motorola 68328 CPU family.
config FB_PXA
tristate "PXA LCD framebuffer support"
depends on FB && ARCH_PXA
---help---
Frame buffer driver for the built-in LCD controller in the Intel
PXA2x0 processor.
This driver is also available as a module ( = code which can be
inserted and removed from the running kernel whenever you want). The
module will be called vfb. If you want to compile it as a module,
say M here and read <file:Documentation/modules.txt>.
If unsure, say N.
config FB_PXA_PARAMETERS
bool "PXA LCD command line parameters"
default n
depends on FB_PXA
---help---
Enable the use of kernel command line or module parameters
to configure the physical properties of the LCD panel when
using the PXA LCD driver.
This option allows you to override the panel parameters
supplied by the platform in order to support multiple
different models of flatpanel. If you will only be using a
single model of flatpanel then you can safely leave this
option disabled.
Documentation/fb/pxafb.txt describes the available parameters.
config FB_VIRTUAL
tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
depends on FB
......
drivers/video/Makefile
View file @ 18857d8e
......@@ -89,4 +89,4 @@ obj-$(CONFIG_FB_TCX) += tcx.o sbuslib.o cfbimgblt.o cfbcopyarea.o
cfbfillrect.o
obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o cfbimgblt.o cfbcopyarea.o \
cfbfillrect.o
obj-$(CONFIG_FB_PXA) += pxafb.o cfbimgblt.o cfbcopyarea.o cfbfillrect.o
drivers/video/fbmem.c
View file @ 18857d8e
......@@ -114,6 +114,8 @@ extern int valkyriefb_setup(char*);
extern int chips_init(void);
extern int g364fb_init(void);
extern int sa1100fb_init(void);
extern int pxafb_init(void);
extern int pxafb_setup(char*);
extern int fm2fb_init(void);
extern int fm2fb_setup(char*);
extern int q40fb_init(void);
......@@ -345,6 +347,9 @@ static struct {
#ifdef CONFIG_FB_SA1100
{ "sa1100fb", sa1100fb_init, NULL },
#endif
#ifdef CONFIG_FB_PXA
{ "pxafb", pxafb_init, pxafb_setup },
#endif
#ifdef CONFIG_FB_SUN3
{ "sun3fb", sun3fb_init, sun3fb_setup },
#endif
......
drivers/video/pxafb.c 0 → 100644
View file @ 18857d8e
/*
* linux/drivers/video/pxafb.c
*
* Copyright (C) 1999 Eric A. Thomas.
* Copyright (C) 2004 Jean-Frederic Clere.
* Copyright (C) 2004 Ian Campbell.
* Copyright (C) 2004 Jeff Lackey.
* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
* which in turn is
* Based on acornfb.c Copyright (C) Russell King.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Intel PXA250/210 LCD Controller Frame Buffer Driver
*
* Please direct your questions and comments on this driver to the following
* email address:
*
* linux-arm-kernel@lists.arm.linux.org.uk
*
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/uaccess.h>
#include <asm/arch/bitfield.h>
#include <asm/arch/pxafb.h>
/*
* Complain if VAR is out of range.
*/
#define DEBUG_VAR 1
#include "pxafb.h"
/* Bits which should not be set in machine configuration structures */
#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
static void (*pxafb_backlight_power)(int);
static void (*pxafb_lcd_power)(int);
static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
#ifdef CONFIG_FB_PXA_PARAMETERS
#define PXAFB_OPTIONS_SIZE 256
static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
#endif
static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
{
unsigned long flags;
local_irq_save(flags);
/*
* We need to handle two requests being made at the same time.
* There are two important cases:
* 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
* We must perform the unblanking, which will do our REENABLE for us.
* 2. When we are blanking, but immediately unblank before we have
* blanked. We do the "REENABLE" thing here as well, just to be sure.
*/
if (fbi->task_state == C_ENABLE && state == C_REENABLE)
state = (u_int) -1;
if (fbi->task_state == C_DISABLE && state == C_ENABLE)
state = C_REENABLE;
if (state != (u_int)-1) {
fbi->task_state = state;
schedule_work(&fbi->task);
}
local_irq_restore(flags);
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int
pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct pxafb_info *fbi = (struct pxafb_info *)info;
u_int val, ret = 1;
if (regno < fbi->palette_size) {
val = ((red >> 0) & 0xf800);
val |= ((green >> 5) & 0x07e0);
val |= ((blue >> 11) & 0x001f);
fbi->palette_cpu[regno] = val;
ret = 0;
}
return ret;
}
static int
pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct pxafb_info *fbi = (struct pxafb_info *)info;
unsigned int val;
int ret = 1;
/*
* If inverse mode was selected, invert all the colours
* rather than the register number. The register number
* is what you poke into the framebuffer to produce the
* colour you requested.
*/
if (fbi->cmap_inverse) {
red = 0xffff - red;
green = 0xffff - green;
blue = 0xffff - blue;
}
/*
* If greyscale is true, then we convert the RGB value
* to greyscale no matter what visual we are using.
*/
if (fbi->fb.var.grayscale)
red = green = blue = (19595 * red + 38470 * green +
7471 * blue) >> 16;
switch (fbi->fb.fix.visual) {
case FB_VISUAL_TRUECOLOR:
/*
* 12 or 16-bit True Colour. We encode the RGB value
* according to the RGB bitfield information.
*/
if (regno <= 16) {
u32 *pal = fbi->fb.pseudo_palette;
val = chan_to_field(red, &fbi->fb.var.red);
val |= chan_to_field(green, &fbi->fb.var.green);
val |= chan_to_field(blue, &fbi->fb.var.blue);
pal[regno] = val;
ret = 0;
}
break;
case FB_VISUAL_STATIC_PSEUDOCOLOR:
case FB_VISUAL_PSEUDOCOLOR:
ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
break;
}
return ret;
}
/*
* pxafb_bpp_to_lccr3():
* Convert a bits per pixel value to the correct bit pattern for LCCR3
*/
static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
{
int ret = 0;
switch (var->bits_per_pixel) {
case 1: ret = LCCR3_1BPP; break;
case 2: ret = LCCR3_2BPP; break;
case 4: ret = LCCR3_4BPP; break;
case 8: ret = LCCR3_8BPP; break;
case 16: ret = LCCR3_16BPP; break;
}
return ret;
}
#ifdef CONFIG_CPU_FREQ
/*
* pxafb_display_dma_period()
* Calculate the minimum period (in picoseconds) between two DMA
* requests for the LCD controller. If we hit this, it means we're
* doing nothing but LCD DMA.
*/
static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
{
/*
* Period = pixclock * bits_per_byte * bytes_per_transfer
* / memory_bits_per_pixel;
*/
return var->pixclock * 8 * 16 / var->bits_per_pixel;
}
extern unsigned int get_clk_frequency_khz(int info);
#endif
/*
* pxafb_check_var():
* Get the video params out of 'var'. If a value doesn't fit, round it up,
* if it's too big, return -EINVAL.
*
* Round up in the following order: bits_per_pixel, xres,
* yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
* bitfields, horizontal timing, vertical timing.
*/
static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct pxafb_info *fbi = (struct pxafb_info *)info;
if (var->xres < MIN_XRES)
var->xres = MIN_XRES;
if (var->yres < MIN_YRES)
var->yres = MIN_YRES;
if (var->xres > fbi->max_xres)
var->xres = fbi->max_xres;
if (var->yres > fbi->max_yres)
var->yres = fbi->max_yres;
var->xres_virtual =
max(var->xres_virtual, var->xres);
var->yres_virtual =
max(var->yres_virtual, var->yres);
/*
* Setup the RGB parameters for this display.
*
* The pixel packing format is described on page 7-11 of the
* PXA2XX Developer's Manual.
*/
if ( var->bits_per_pixel == 16 ) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = var->transp.length = 0;
} else {
var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.length = 0;
}
#ifdef CONFIG_CPU_FREQ
DPRINTK("dma period = %d ps, clock = %d kHz\n",
pxafb_display_dma_period(var),
get_clk_frequency_khz(0));
#endif
return 0;
}
static inline void pxafb_set_truecolor(u_int is_true_color)
{
DPRINTK("true_color = %d\n", is_true_color);
// do your machine-specific setup if needed
}
/*
* pxafb_set_par():
* Set the user defined part of the display for the specified console
*/
static int pxafb_set_par(struct fb_info *info)
{
struct pxafb_info *fbi = (struct pxafb_info *)info;
struct fb_var_screeninfo *var = &info->var;
unsigned long palette_mem_size;
DPRINTK("set_par\n");
if (var->bits_per_pixel == 16)
fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
else if (!fbi->cmap_static)
fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
else {
/*
* Some people have weird ideas about wanting static
* pseudocolor maps. I suspect their user space
* applications are broken.
*/
fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
}
fbi->fb.fix.line_length = var->xres_virtual *
var->bits_per_pixel / 8;
fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
palette_mem_size = fbi->palette_size * sizeof(u16);
DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
/*
* Set (any) board control register to handle new color depth
*/
pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
pxafb_activate_var(var, fbi);
return 0;
}
/*
* Formal definition of the VESA spec:
* On
* This refers to the state of the display when it is in full operation
* Stand-By
* This defines an optional operating state of minimal power reduction with
* the shortest recovery time
* Suspend
* This refers to a level of power management in which substantial power
* reduction is achieved by the display. The display can have a longer
* recovery time from this state than from the Stand-by state
* Off
* This indicates that the display is consuming the lowest level of power
* and is non-operational. Recovery from this state may optionally require
* the user to manually power on the monitor
*
* Now, the fbdev driver adds an additional state, (blank), where they
* turn off the video (maybe by colormap tricks), but don't mess with the
* video itself: think of it semantically between on and Stand-By.
*
* So here's what we should do in our fbdev blank routine:
*
* VESA_NO_BLANKING (mode 0) Video on, front/back light on
* VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
* VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
* VESA_POWERDOWN (mode 3) Video off, front/back light off
*
* This will match the matrox implementation.
*/
/*
* pxafb_blank():
* Blank the display by setting all palette values to zero. Note, the
* 12 and 16 bpp modes don't really use the palette, so this will not
* blank the display in all modes.
*/
static int pxafb_blank(int blank, struct fb_info *info)
{
struct pxafb_info *fbi = (struct pxafb_info *)info;
int i;
DPRINTK("pxafb_blank: blank=%d\n", blank);
switch (blank) {
case VESA_POWERDOWN:
case VESA_VSYNC_SUSPEND:
case VESA_HSYNC_SUSPEND:
if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
for (i = 0; i < fbi->palette_size; i++)
pxafb_setpalettereg(i, 0, 0, 0, 0, info);
pxafb_schedule_work(fbi, C_DISABLE);
//TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
break;
case VESA_NO_BLANKING:
//TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
fb_set_cmap(&fbi->fb.cmap, 1, info);
pxafb_schedule_work(fbi, C_ENABLE);
}
return 0;
}
static struct fb_ops pxafb_ops = {
.owner = THIS_MODULE,
.fb_check_var = pxafb_check_var,
.fb_set_par = pxafb_set_par,
.fb_setcolreg = pxafb_setcolreg,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_blank = pxafb_blank,
.fb_cursor = soft_cursor,
};
/*
* Calculate the PCD value from the clock rate (in picoseconds).
* We take account of the PPCR clock setting.
* From PXA Developer's Manual:
*
* PixelClock = LCLK
* -------------
* 2 ( PCD + 1 )
*
* PCD = LCLK
* ------------- - 1
* 2(PixelClock)
*
* Where:
* LCLK = LCD/Memory Clock
* PCD = LCCR3[7:0]
*
* PixelClock here is in Hz while the pixclock argument given is the
* period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
*
* The function get_lclk_frequency_10khz returns LCLK in units of
* 10khz. Calling the result of this function lclk gives us the
* following
*
* PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
* -------------------------------------- - 1
* 2
*
* Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
*/
static inline unsigned int get_pcd(unsigned int pixclock)
{
unsigned long long pcd;
/* FIXME: Need to take into account Double Pixel Clock mode
* (DPC) bit? or perhaps set it based on the various clock
* speeds */
pcd = (unsigned long long)get_lclk_frequency_10khz() * (unsigned long long)pixclock;
pcd /= 100000000 * 2;
/* no need for this, since we should subtract 1 anyway. they cancel */
/* pcd += 1; */ /* make up for integer math truncations */
return (unsigned int)pcd;
}
/*
* pxafb_activate_var():
* Configures LCD Controller based on entries in var parameter. Settings are
* only written to the controller if changes were made.
*/
static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
{
struct pxafb_lcd_reg new_regs;
u_long flags;
u_int pcd = get_pcd(var->pixclock);
DPRINTK("Configuring PXA LCD\n");
DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
var->xres, var->hsync_len,
var->left_margin, var->right_margin);
DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
var->yres, var->vsync_len,
var->upper_margin, var->lower_margin);
DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
#if DEBUG_VAR
if (var->xres < 16 || var->xres > 1024)
printk(KERN_ERR "%s: invalid xres %d\n",
fbi->fb.fix.id, var->xres);
switch(var->bits_per_pixel) {
case 1:
case 2:
case 4:
case 8:
case 16:
break;
default:
printk(KERN_ERR "%s: invalid bit depth %d\n",
fbi->fb.fix.id, var->bits_per_pixel);
break;
}
if (var->hsync_len < 1 || var->hsync_len > 64)
printk(KERN_ERR "%s: invalid hsync_len %d\n",
fbi->fb.fix.id, var->hsync_len);
if (var->left_margin < 1 || var->left_margin > 255)
printk(KERN_ERR "%s: invalid left_margin %d\n",
fbi->fb.fix.id, var->left_margin);
if (var->right_margin < 1 || var->right_margin > 255)
printk(KERN_ERR "%s: invalid right_margin %d\n",
fbi->fb.fix.id, var->right_margin);
if (var->yres < 1 || var->yres > 1024)
printk(KERN_ERR "%s: invalid yres %d\n",
fbi->fb.fix.id, var->yres);
if (var->vsync_len < 1 || var->vsync_len > 64)
printk(KERN_ERR "%s: invalid vsync_len %d\n",
fbi->fb.fix.id, var->vsync_len);
if (var->upper_margin < 0 || var->upper_margin > 255)
printk(KERN_ERR "%s: invalid upper_margin %d\n",
fbi->fb.fix.id, var->upper_margin);
if (var->lower_margin < 0 || var->lower_margin > 255)
printk(KERN_ERR "%s: invalid lower_margin %d\n",
fbi->fb.fix.id, var->lower_margin);
#endif
new_regs.lccr0 = fbi->lccr0 |
(LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
new_regs.lccr1 =
LCCR1_DisWdth(var->xres) +
LCCR1_HorSnchWdth(var->hsync_len) +
LCCR1_BegLnDel(var->left_margin) +
LCCR1_EndLnDel(var->right_margin);
new_regs.lccr2 =
LCCR2_DisHght(var->yres) +
LCCR2_VrtSnchWdth(var->vsync_len) +
LCCR2_BegFrmDel(var->upper_margin) +
LCCR2_EndFrmDel(var->lower_margin);
new_regs.lccr3 = fbi->lccr3 |
pxafb_bpp_to_lccr3(var) |
(var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
(var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
if (pcd)
new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
/* Update shadow copy atomically */
local_irq_save(flags);
/* setup dma descriptors */
fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
#define BYTES_PER_PANEL ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual ? \
(var->xres * var->yres * var->bits_per_pixel / 8 / 2) : \
(var->xres * var->yres * var->bits_per_pixel / 8))
/* populate descriptors */
fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
fbi->dmadesc_fblow_cpu->fidr = 0;
fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
fbi->dmadesc_fbhigh_cpu->fidr = 0;
fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
fbi->dmadesc_palette_cpu->fidr = 0;
fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
if( var->bits_per_pixel < 12)
{
/* assume any mode with <12 bpp is palette driven */
fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
}
else
{
/* palette shouldn't be loaded in true-color mode */
fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
/* init it to something, even though we won't be using it */
fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
}
#if 0
DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
#endif
fbi->reg_lccr0 = new_regs.lccr0;
fbi->reg_lccr1 = new_regs.lccr1;
fbi->reg_lccr2 = new_regs.lccr2;
fbi->reg_lccr3 = new_regs.lccr3;
local_irq_restore(flags);
/*
* Only update the registers if the controller is enabled
* and something has changed.
*/
if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
(LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
(FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
pxafb_schedule_work(fbi, C_REENABLE);
return 0;
}
/*
* NOTE! The following functions are purely helpers for set_ctrlr_state.
* Do not call them directly; set_ctrlr_state does the correct serialisation
* to ensure that things happen in the right way 100% of time time.
* -- rmk
*/
static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
{
DPRINTK("backlight o%s\n", on ? "n" : "ff");
if (pxafb_backlight_power)
pxafb_backlight_power(on);
}
static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
{
DPRINTK("LCD power o%s\n", on ? "n" : "ff");
if (pxafb_lcd_power)
pxafb_lcd_power(on);
}
static void pxafb_setup_gpio(struct pxafb_info *fbi)
{
unsigned int lccr0 = fbi->lccr0;
/*
* setup is based on type of panel supported
*/
/* 4 bit interface */
if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
(lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
(lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
{
// bits 58-61
GPDR1 |= (0xf << 26);
GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
// bits 74-77
GPDR2 |= (0xf << 10);
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
}
/* 8 bit interface */
else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
((lccr0 & LCCR0_CMS) == LCCR0_Color &&
(lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
{
// bits 58-65
GPDR1 |= (0x3f << 26);
GPDR2 |= (0x3);
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
// bits 74-77
GPDR2 |= (0xf << 10);
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
}
/* 16 bit interface */
else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
{
// bits 58-77
GPDR1 |= (0x3f << 26);
GPDR2 |= 0x00003fff;
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
}
else {
printk( KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
}
}
static void pxafb_enable_controller(struct pxafb_info *fbi)
{
DPRINTK("Enabling LCD controller\n");
DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
/* Sequence from 11.7.10 */
LCCR3 = fbi->reg_lccr3;
LCCR2 = fbi->reg_lccr2;
LCCR1 = fbi->reg_lccr1;
LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
FDADR0 = fbi->fdadr0;
FDADR1 = fbi->fdadr1;
LCCR0 |= LCCR0_ENB;
DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0);
DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1);
DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0);
DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1);
DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2);
DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3);
}
static void pxafb_disable_controller(struct pxafb_info *fbi)
{
DECLARE_WAITQUEUE(wait, current);
DPRINTK("Disabling LCD controller\n");
add_wait_queue(&fbi->ctrlr_wait, &wait);
set_current_state(TASK_UNINTERRUPTIBLE);
LCSR = 0xffffffff; /* Clear LCD Status Register */
LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
//TODO?enable_irq(IRQ_LCD); /* Enable LCD IRQ */
LCCR0 &= ~LCCR0_ENB; /* Disable LCD Controller */
schedule_timeout(20 * HZ / 1000);
remove_wait_queue(&fbi->ctrlr_wait, &wait);
}
/*
* pxafb_handle_irq: Handle 'LCD DONE' interrupts.
*/
static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
{
struct pxafb_info *fbi = dev_id;
unsigned int lcsr = LCSR;
if (lcsr & LCSR_LDD) {
LCCR0 |= LCCR0_LDM;
wake_up(&fbi->ctrlr_wait);
}
LCSR = lcsr;
return IRQ_HANDLED;
}
/*
* This function must be called from task context only, since it will
* sleep when disabling the LCD controller, or if we get two contending
* processes trying to alter state.
*/
static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
{
u_int old_state;
down(&fbi->ctrlr_sem);
old_state = fbi->state;
/*
* Hack around fbcon initialisation.
*/
if (old_state == C_STARTUP && state == C_REENABLE)
state = C_ENABLE;
switch (state) {
case C_DISABLE_CLKCHANGE:
/*
* Disable controller for clock change. If the
* controller is already disabled, then do nothing.
*/
if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
fbi->state = state;
//TODO __pxafb_lcd_power(fbi, 0);
pxafb_disable_controller(fbi);
}
break;
case C_DISABLE_PM:
case C_DISABLE:
/*
* Disable controller
*/
if (old_state != C_DISABLE) {
fbi->state = state;
__pxafb_backlight_power(fbi, 0);
__pxafb_lcd_power(fbi, 0);
if (old_state != C_DISABLE_CLKCHANGE)
pxafb_disable_controller(fbi);
}
break;
case C_ENABLE_CLKCHANGE:
/*
* Enable the controller after clock change. Only
* do this if we were disabled for the clock change.
*/
if (old_state == C_DISABLE_CLKCHANGE) {
fbi->state = C_ENABLE;
pxafb_enable_controller(fbi);
//TODO __pxafb_lcd_power(fbi, 1);
}
break;
case C_REENABLE:
/*
* Re-enable the controller only if it was already
* enabled. This is so we reprogram the control
* registers.
*/
if (old_state == C_ENABLE) {
pxafb_disable_controller(fbi);
pxafb_setup_gpio(fbi);
pxafb_enable_controller(fbi);
}
break;
case C_ENABLE_PM:
/*
* Re-enable the controller after PM. This is not
* perfect - think about the case where we were doing
* a clock change, and we suspended half-way through.
*/
if (old_state != C_DISABLE_PM)
break;
/* fall through */
case C_ENABLE:
/*
* Power up the LCD screen, enable controller, and
* turn on the backlight.
*/
if (old_state != C_ENABLE) {
fbi->state = C_ENABLE;
pxafb_setup_gpio(fbi);
pxafb_enable_controller(fbi);
__pxafb_lcd_power(fbi, 1);
__pxafb_backlight_power(fbi, 1);
}
break;
}
up(&fbi->ctrlr_sem);
}
/*
* Our LCD controller task (which is called when we blank or unblank)
* via keventd.
*/
static void pxafb_task(void *dummy)
{
struct pxafb_info *fbi = dummy;
u_int state = xchg(&fbi->task_state, -1);
set_ctrlr_state(fbi, state);
}
#ifdef CONFIG_CPU_FREQ
/*
* CPU clock speed change handler. We need to adjust the LCD timing
* parameters when the CPU clock is adjusted by the power management
* subsystem.
*
* TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
*/
static int
pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
{
struct pxafb_info *fbi = TO_INF(nb, freq_transition);
//TODO struct cpufreq_freqs *f = data;
u_int pcd;
switch (val) {
case CPUFREQ_PRECHANGE:
set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
break;
case CPUFREQ_POSTCHANGE:
pcd = get_pcd(fbi->fb.var.pixclock);
fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
break;
}
return 0;
}
static int
pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
{
struct pxafb_info *fbi = TO_INF(nb, freq_policy);
struct fb_var_screeninfo *var = &fbi->fb.var;
struct cpufreq_policy *policy = data;
switch (val) {
case CPUFREQ_ADJUST:
case CPUFREQ_INCOMPATIBLE:
printk(KERN_DEBUG "min dma period: %d ps, "
"new clock %d kHz\n", pxafb_display_dma_period(var),
policy->max);
// TODO: fill in min/max values
break;
#if 0
case CPUFREQ_NOTIFY:
printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
do {} while(0);
/* todo: panic if min/max values aren't fulfilled
* [can't really happen unless there's a bug in the
* CPU policy verification process *
*/
break;
#endif
}
return 0;
}
#endif
#ifdef CONFIG_PM
/*
* Power management hooks. Note that we won't be called from IRQ context,
* unlike the blank functions above, so we may sleep.
*/
static int pxafb_suspend(struct device *dev, u32 state, u32 level)
{
struct pxafb_info *fbi = dev_get_drvdata(dev);
if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
set_ctrlr_state(fbi, C_DISABLE_PM);
return 0;
}
static int pxafb_resume(struct device *dev, u32 level)
{
struct pxafb_info *fbi = dev_get_drvdata(dev);
if (level == RESUME_ENABLE)
set_ctrlr_state(fbi, C_ENABLE_PM);
return 0;
}
#else
#define pxafb_suspend NULL
#define pxafb_resume NULL
#endif
/*
* pxafb_map_video_memory():
* Allocates the DRAM memory for the frame buffer. This buffer is
* remapped into a non-cached, non-buffered, memory region to
* allow palette and pixel writes to occur without flushing the
* cache. Once this area is remapped, all virtual memory
* access to the video memory should occur at the new region.
*/
static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
{
u_long palette_mem_size;
/*
* We reserve one page for the palette, plus the size
* of the framebuffer.
*/
fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
&fbi->map_dma, GFP_KERNEL);
if (fbi->map_cpu) {
/* prevent initial garbage on screen */
memset(fbi->map_cpu, 0, fbi->map_size);
fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
/*
* FIXME: this is actually the wrong thing to place in
* smem_start. But fbdev suffers from the problem that
* it needs an API which doesn't exist (in this case,
* dma_writecombine_mmap)
*/
fbi->fb.fix.smem_start = fbi->screen_dma;
fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
palette_mem_size = fbi->palette_size * sizeof(u16);
DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
}
return fbi->map_cpu ? 0 : -ENOMEM;
}
static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
{
struct pxafb_info *fbi;
void *addr;
struct pxafb_mach_info *inf = dev->platform_data;
/* Alloc the pxafb_info and pseudo_palette in one step */
fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 17, GFP_KERNEL);
if (!fbi)
return NULL;
memset(fbi, 0, sizeof(struct pxafb_info));
fbi->dev = dev;
strcpy(fbi->fb.fix.id, PXA_NAME);
fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fb.fix.type_aux = 0;
fbi->fb.fix.xpanstep = 0;
fbi->fb.fix.ypanstep = 0;
fbi->fb.fix.ywrapstep = 0;
fbi->fb.fix.accel = FB_ACCEL_NONE;
fbi->fb.var.nonstd = 0;
fbi->fb.var.activate = FB_ACTIVATE_NOW;
fbi->fb.var.height = -1;
fbi->fb.var.width = -1;
fbi->fb.var.accel_flags = 0;
fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
fbi->fb.fbops = &pxafb_ops;
fbi->fb.flags = FBINFO_FLAG_DEFAULT;
fbi->fb.node = -1;
fbi->fb.currcon = -1;
addr = fbi;
addr = addr + sizeof(struct pxafb_info);
fbi->fb.pseudo_palette = addr;
fbi->max_xres = inf->xres;
fbi->fb.var.xres = inf->xres;
fbi->fb.var.xres_virtual = inf->xres;
fbi->max_yres = inf->yres;
fbi->fb.var.yres = inf->yres;
fbi->fb.var.yres_virtual = inf->yres;
fbi->max_bpp = inf->bpp;
fbi->fb.var.bits_per_pixel = inf->bpp;
fbi->fb.var.pixclock = inf->pixclock;
fbi->fb.var.hsync_len = inf->hsync_len;
fbi->fb.var.left_margin = inf->left_margin;
fbi->fb.var.right_margin = inf->right_margin;
fbi->fb.var.vsync_len = inf->vsync_len;
fbi->fb.var.upper_margin = inf->upper_margin;
fbi->fb.var.lower_margin = inf->lower_margin;
fbi->fb.var.sync = inf->sync;
fbi->fb.var.grayscale = inf->cmap_greyscale;
fbi->cmap_inverse = inf->cmap_inverse;
fbi->cmap_static = inf->cmap_static;
fbi->lccr0 = inf->lccr0;
fbi->lccr3 = inf->lccr3;
fbi->state = C_STARTUP;
fbi->task_state = (u_char)-1;
fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
fbi->max_bpp / 8;
init_waitqueue_head(&fbi->ctrlr_wait);
INIT_WORK(&fbi->task, pxafb_task, fbi);
init_MUTEX(&fbi->ctrlr_sem);
return fbi;
}
#ifdef CONFIG_FB_PXA_PARAMETERS
static int __init pxafb_parse_options(struct device *dev, char *options)
{
struct pxafb_mach_info *inf = dev->platform_data;
char *this_opt;
if (!options || !*options)
return 0;
dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
/* could be made table driven or similar?... */
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "mode:", 5)) {
const char *name = this_opt+5;
unsigned int namelen = strlen(name);
int res_specified = 0, bpp_specified = 0;
unsigned int xres = 0, yres = 0, bpp = 0;
int yres_specified = 0;
int i;
for (i = namelen-1; i >= 0; i--) {
switch (name[i]) {
case '-':
namelen = i;
if (!bpp_specified && !yres_specified) {
bpp = simple_strtoul(&name[i+1], NULL, 0);
bpp_specified = 1;
} else
goto done;
break;
case 'x':
if (!yres_specified) {
yres = simple_strtoul(&name[i+1], NULL, 0);
yres_specified = 1;
} else
goto done;
break;
case '0'...'9':
break;
default:
goto done;
}
}
if (i < 0 && yres_specified) {
xres = simple_strtoul(name, NULL, 0);
res_specified = 1;
}
done:
if ( res_specified ) {
dev_info(dev, "overriding resolution: %dx%x\n", xres, yres);
inf->xres = xres; inf->yres = yres;
}
if ( bpp_specified )
switch (bpp) {
case 1:
case 2:
case 4:
case 8:
case 16:
inf->bpp = bpp;
dev_info(dev, "overriding bit depth: %d\n", bpp);
break;
default:
dev_err(dev, "Depth %d is not valid\n", bpp);
}
} else if (!strncmp(this_opt, "pixclock:", 9)) {
inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
dev_info(dev, "override pixclock: %uld\n", inf->pixclock);
} else if (!strncmp(this_opt, "left:", 5)) {
inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
dev_info(dev, "override left: %d\n", inf->left_margin);
} else if (!strncmp(this_opt, "right:", 6)) {
inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
dev_info(dev, "override right: %d\n", inf->right_margin);
} else if (!strncmp(this_opt, "upper:", 6)) {
inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
dev_info(dev, "override upper: %d\n", inf->upper_margin);
} else if (!strncmp(this_opt, "lower:", 6)) {
inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
dev_info(dev, "override lower: %d\n", inf->lower_margin);
} else if (!strncmp(this_opt, "hsynclen:", 9)) {
inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
dev_info(dev, "override hsynclen: %d\n", inf->hsync_len);
} else if (!strncmp(this_opt, "vsynclen:", 9)) {
inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
dev_info(dev, "override vsynclen: %d\n", inf->vsync_len);
} else if (!strncmp(this_opt, "hsync:", 6)) {
if ( simple_strtoul(this_opt+6, NULL, 0) == 0 ) {
dev_info(dev, "override hsync: Active Low\n");
inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
} else {
dev_info(dev, "override hsync: Active High\n");
inf->sync |= FB_SYNC_HOR_HIGH_ACT;
}
} else if (!strncmp(this_opt, "vsync:", 6)) {
if ( simple_strtoul(this_opt+6, NULL, 0) == 0 ) {
dev_info(dev, "override vsync: Active Low\n");
inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
} else {
dev_info(dev, "override vsync: Active High\n");
inf->sync |= FB_SYNC_VERT_HIGH_ACT;
}
} else if (!strncmp(this_opt, "dpc:", 4)) {
if ( simple_strtoul(this_opt+4, NULL, 0) == 0 ) {
dev_info(dev, "override double pixel clock: false\n");
inf->lccr3 &= ~LCCR3_DPC;
} else {
dev_info(dev, "override double pixel clock: true\n");
inf->lccr3 |= LCCR3_DPC;
}
} else if (!strncmp(this_opt, "outputen:", 9)) {
if ( simple_strtoul(this_opt+9, NULL, 0) == 0 ) {
dev_info(dev, "override output enable: active low\n");
inf->lccr3 = ( inf->lccr3 & ~LCCR3_OEP ) | LCCR3_OutEnL;
} else {
dev_info(dev, "override output enable: active high\n");
inf->lccr3 = ( inf->lccr3 & ~LCCR3_OEP ) | LCCR3_OutEnH;
}
} else if (!strncmp(this_opt, "pixclockpol:", 12)) {
if ( simple_strtoul(this_opt+12, NULL, 0) == 0 ) {
dev_info(dev, "override pixel clock polarity: falling edge\n");
inf->lccr3 = ( inf->lccr3 & ~LCCR3_PCP ) | LCCR3_PixFlEdg;
} else {
dev_info(dev, "override pixel clock polarity: rising edge\n");
inf->lccr3 = ( inf->lccr3 & ~LCCR3_PCP ) | LCCR3_PixRsEdg;
}
} else if (!strncmp(this_opt, "color", 5)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
} else if (!strncmp(this_opt, "mono", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
} else if (!strncmp(this_opt, "active", 6)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
} else if (!strncmp(this_opt, "passive", 7)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
} else if (!strncmp(this_opt, "single", 6)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
} else if (!strncmp(this_opt, "dual", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
} else if (!strncmp(this_opt, "4pix", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
} else if (!strncmp(this_opt, "8pix", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
} else {
dev_err(dev, "unknown option: %s\n", this_opt);
return -EINVAL;
}
}
return 0;
}
#endif
int __init pxafb_probe(struct device *dev)
{
struct pxafb_info *fbi;
struct pxafb_mach_info *inf;
unsigned long flags;
int ret;
dev_dbg(dev, "pxafb_probe\n");
inf = dev->platform_data;
ret = -ENOMEM;
fbi = NULL;
if (!inf)
goto failed;
#ifdef CONFIG_FB_PXA_PARAMETERS
ret = pxafb_parse_options(dev, g_options);
if ( ret < 0 )
goto failed;
#endif
#ifdef DEBUG_VAR
/* Check for various illegal bit-combinations. Currently only
* a warning is given. */
if ( inf->lccr0 & LCCR0_INVALID_CONFIG_MASK )
dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
if ( inf->lccr3 & LCCR3_INVALID_CONFIG_MASK )
dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
if ( inf->lccr0 & LCCR0_DPD &&
( ( inf->lccr0 & LCCR0_PAS ) != LCCR0_Pas ||
( inf->lccr0 & LCCR0_SDS ) != LCCR0_Sngl ||
( inf->lccr0 & LCCR0_CMS ) != LCCR0_Mono ) )
dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
" single panel mode\n");
if ( (inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
( inf->lccr0 & LCCR0_SDS ) == LCCR0_Dual )
dev_warn(dev, "Dual panel only valid in passive mode\n");
if ( (inf->lccr0 & LCCR0_PAS ) == LCCR0_Pas &&
(inf->upper_margin || inf->lower_margin) )
dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
#endif
dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
dev_err(dev, "Invalid resolution or bit depth\n");
ret = -EINVAL;
goto failed;
}
pxafb_backlight_power = inf->pxafb_backlight_power;
pxafb_lcd_power = inf->pxafb_lcd_power;
fbi = pxafb_init_fbinfo(dev);
if (!fbi) {
dev_err(dev, "Failed to initialize framebuffer device\n");
ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
goto failed;
}
/* Initialize video memory */
ret = pxafb_map_video_memory(fbi);
if (ret) {
dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
ret = -ENOMEM;
goto failed;
}
/* enable LCD controller clock */
local_irq_save(flags);
CKEN |= CKEN16_LCD;
local_irq_restore(flags);
ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
if (ret) {
dev_err(dev, "request_irq failed: %d\n", ret);
ret = -EBUSY;
goto failed;
}
/*
* This makes sure that our colour bitfield
* descriptors are correctly initialised.
*/
pxafb_check_var(&fbi->fb.var, &fbi->fb);
pxafb_set_par(&fbi->fb);
dev_set_drvdata(dev, fbi);
ret = register_framebuffer(&fbi->fb);
if (ret < 0) {
dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
goto failed;
}
#ifdef CONFIG_PM
// TODO
#endif
#ifdef CONFIG_CPU_FREQ
fbi->freq_transition.notifier_call = pxafb_freq_transition;
fbi->freq_policy.notifier_call = pxafb_freq_policy;
cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
#endif
/*
* Ok, now enable the LCD controller
*/
set_ctrlr_state(fbi, C_ENABLE);
return 0;
failed:
dev_set_drvdata(dev, NULL);
if (fbi)
kfree(fbi);
return ret;
}
static struct device_driver pxafb_driver = {
.name = "pxafb",
.bus = &platform_bus_type,
.probe = pxafb_probe,
#ifdef CONFIG_PM
.suspend = pxafb_suspend,
.resume = pxafb_resume,
#endif
};
int __devinit pxafb_init(void)
{
return driver_register(&pxafb_driver);
}
#ifndef MODULE
int __devinit pxafb_setup(char *options)
{
# ifdef CONFIG_FB_PXA_PARAMETERS
strlcpy(g_options, options, sizeof(g_options));
# endif
return 0;
}
#else
module_init(pxafb_init);
# ifdef CONFIG_FB_PXA_PARAMETERS
module_param_string(options, g_options, sizeof(g_options), 0);
MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
# endif
#endif
MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
MODULE_LICENSE("GPL");
drivers/video/pxafb.h 0 → 100644
View file @ 18857d8e
#ifndef __PXAFB_H__
#define __PXAFB_H__
/*
* linux/drivers/video/pxafb.h
* -- Intel PXA250/210 LCD Controller Frame Buffer Device
*
* Copyright (C) 1999 Eric A. Thomas.
* Copyright (C) 2004 Jean-Frederic Clere.
* Copyright (C) 2004 Ian Campbell.
* Copyright (C) 2004 Jeff Lackey.
* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
* which in turn is
* Based on acornfb.c Copyright (C) Russell King.
*
* 2001-08-03: Cliff Brake <cbrake@acclent.com>
* - ported SA1100 code to PXA
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/* Shadows for LCD controller registers */
struct pxafb_lcd_reg {
unsigned int lccr0;
unsigned int lccr1;
unsigned int lccr2;
unsigned int lccr3;
};
/* PXA LCD DMA descriptor */
struct pxafb_dma_descriptor {
unsigned int fdadr;
unsigned int fsadr;
unsigned int fidr;
unsigned int ldcmd;
};
struct pxafb_info {
struct fb_info fb;
struct device *dev;
u_int max_bpp;
u_int max_xres;
u_int max_yres;
/*
* These are the addresses we mapped
* the framebuffer memory region to.
*/
/* raw memory addresses */
dma_addr_t map_dma; /* physical */
u_char * map_cpu; /* virtual */
u_int map_size;
/* addresses of pieces placed in raw buffer */
u_char * screen_cpu; /* virtual address of frame buffer */
dma_addr_t screen_dma; /* physical address of frame buffer */
u16 * palette_cpu; /* virtual address of palette memory */
dma_addr_t palette_dma; /* physical address of palette memory */
u_int palette_size;
/* DMA descriptors */
struct pxafb_dma_descriptor * dmadesc_fblow_cpu;
dma_addr_t dmadesc_fblow_dma;
struct pxafb_dma_descriptor * dmadesc_fbhigh_cpu;
dma_addr_t dmadesc_fbhigh_dma;
struct pxafb_dma_descriptor * dmadesc_palette_cpu;
dma_addr_t dmadesc_palette_dma;
dma_addr_t fdadr0;
dma_addr_t fdadr1;
u_int lccr0;
u_int lccr3;
u_int cmap_inverse:1,
cmap_static:1,
unused:30;
u_int reg_lccr0;
u_int reg_lccr1;
u_int reg_lccr2;
u_int reg_lccr3;
volatile u_char state;
volatile u_char task_state;
struct semaphore ctrlr_sem;
wait_queue_head_t ctrlr_wait;
struct work_struct task;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
struct notifier_block freq_policy;
#endif
};
#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
/*
* These are the actions for set_ctrlr_state
*/
#define C_DISABLE (0)
#define C_ENABLE (1)
#define C_DISABLE_CLKCHANGE (2)
#define C_ENABLE_CLKCHANGE (3)
#define C_REENABLE (4)
#define C_DISABLE_PM (5)
#define C_ENABLE_PM (6)
#define C_STARTUP (7)
#define PXA_NAME "PXA"
/*
* Debug macros
*/
#if DEBUG
# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
#else
# define DPRINTK(fmt, args...)
#endif
/*
* Minimum X and Y resolutions
*/
#define MIN_XRES 64
#define MIN_YRES 64
#endif /* __PXAFB_H__ */
drivers/video/sa1100fb.c
View file @ 18857d8e
......@@ -326,6 +326,22 @@ static struct sa1100fb_mach_info brutus_info __initdata = {
};
#endif
#ifdef CONFIG_SA1100_COLLIE
static struct sa1100fb_mach_info collie_info __initdata = {
pixclock: 171521, bpp: 16,
xres: 320, yres: 240,
hsync_len: 5, vsync_len: 1,
left_margin: 11, upper_margin: 2,
right_margin: 30, lower_margin: 0,
sync: FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
};
#endif
#ifdef CONFIG_SA1100_FREEBIRD
#warning Please check this carefully
static struct sa1100fb_mach_info freebird_info __initdata = {
......@@ -635,6 +651,11 @@ sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
inf = &brutus_info;
}
#endif
#ifdef CONFIG_SA1100_COLLIE
if (machine_is_collie()) {
inf = &collie_info;
}
#endif
#ifdef CONFIG_SA1100_FREEBIRD
if (machine_is_freebird()) {
inf = &freebird_info;
......
include/asm-arm/arch-ixp4xx/coyote.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/coyote.h
*
* ADI Engineering platform specific definitions
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define COYOTE_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define COYOTE_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE * 2
/* PCI controller GPIO to IRQ pin mappings */
#define COYOTE_PCI_SLOT0_PIN 6
#define COYOTE_PCI_SLOT1_PIN 11
#define COYOTE_PCI_SLOT0_DEVID 14
#define COYOTE_PCI_SLOT1_DEVID 15
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_CS3_BASE_PHYS
#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
#define COYOTE_IDE_REGION_SIZE 0x1000
#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
include/asm-arm/arch-ixp4xx/dma.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/dma.h
*
* Copyright (C) 2001-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include <linux/config.h>
#include <linux/device.h>
#include <linux/pci.h>
#include <asm/page.h>
#include <asm/sizes.h>
#include <asm/hardware.h>
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
/* No DMA */
#define MAX_DMA_CHANNELS 0
/*
* Only first 64MB of memory can be accessed via PCI.
* We use GFP_DMA to allocate safe buffers to do map/unmap.
* This is really ugly and we need a better way of specifying
* DMA-capable regions of memory.
*/
static inline void __arch_adjust_zones(int node, unsigned long *zone_size,
unsigned long *zhole_size)
{
unsigned int sz = SZ_64M >> PAGE_SHIFT;
/*
* Only adjust if > 64M on current system
*/
if (node || (zone_size[0] <= sz))
return;
zone_size[1] = zone_size[0] - sz;
zone_size[0] = sz;
zhole_size[1] = zhole_size[0];
zhole_size[0] = 0;
}
#define arch_adjust_zones(node, size, holes) \
__arch_adjust_zones(node, size, holes)
#endif /* _ASM_ARCH_DMA_H */
include/asm-arm/arch-ixp4xx/hardware.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/hardware.h
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* Hardware definitions for IXP4xx based systems
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x48000000
/*
* We override the standard dma-mask routines for bouncing.
*/
#define HAVE_ARCH_PCI_SET_DMA_MASK
#define pcibios_assign_all_busses() 1
/* Register locations and bits */
#include "ixp4xx-regs.h"
/* Platform helper functions and definitions */
#include "platform.h"
/* Platform specific details */
#include "ixdp425.h"
#include "coyote.h"
#include "prpmc1100.h"
#endif /* _ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-ixp4xx/ide.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-ixp4xx/ide.h
*
* Copyright (C) 2003-2004 MontaVista Software, Inc.
* Based on original code Copyright (c) 1998 Russell King
*/
/*
* Set up a hw structure for a specified data port, control port and IRQ.
* This should follow whatever the default interface uses.
*/
static __inline__ void
ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
{
unsigned long reg = (unsigned long) data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
hw->io_ports[IDE_CONTROL_OFFSET] = (unsigned long) ctrl_port;
if (irq)
*irq = 0;
}
/*
* This registers the standard ports for this architecture with the IDE
* driver.
*/
static __inline__ void ide_init_default_hwifs(void)
{
/* There are no standard ports */
}
include/asm-arm/arch-ixp4xx/io.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-ixp4xx/io.h
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffff0000
#define BIT(x) ((1)<<(x))
extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
/*
* IXP4xx provides two methods of accessing PCI memory space:
*
* 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
* To access PCI via this space, we simply ioremap() the BAR
* into the kernel and we can use the standard read[bwl]/write[bwl]
* macros. This is the preffered method due to speed but it
* limits the system to just 64MB of PCI memory. This can be
* problamatic if using video cards and other memory-heavy
* targets.
*
* 2) If > 64MB of memory space is required, the IXP4xx can be configured
* to use indirect registers to access PCI (as we do below for I/O
* transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
* of memory on the bus. The disadvantadge of this is that every
* PCI access requires three local register accesses plus a spinlock,
* but in some cases the performance hit is acceptable. In addition,
* you cannot mmap() PCI devices in this case.
*
*/
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
#define __mem_pci(a) ((unsigned long)(a))
#else
#include <linux/mm.h>
/*
* In the case of using indirect PCI, we simply return the actual PCI
* address and our read/write implementation use that to drive the
* access registers. If something outside of PCI is ioremap'd, we
* fallback to the default.
*/
static inline void *
__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
{
extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
if((addr < 0x48000000) || (addr > 0x4fffffff))
return __ioremap(addr, size, flags, align);
return (void *)addr;
}
static inline void
__ixp4xx_iounmap(void *addr)
{
extern void __iounmap(void *addr);
if ((u32)addr > VMALLOC_START)
__iounmap(addr);
}
#define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x)
#define __arch_iounmap(a) __ixp4xx_iounmap(a)
#define writeb(p, v) __ixp4xx_writeb(p, v)
#define writew(p, v) __ixp4xx_writew(p, v)
#define writel(p, v) __ixp4xx_writel(p, v)
#define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
#define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
#define writesl(p, v, l) __ixp4xx_writesl(p, v, l)
#define readb(p) __ixp4xx_readb(p)
#define readw(p) __ixp4xx_readw(p)
#define readl(p) __ixp4xx_readl(p)
#define readsb(p, v, l) __ixp4xx_readsb(p, v, l)
#define readsw(p, v, l) __ixp4xx_readsw(p, v, l)
#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
static inline void
__ixp4xx_writeb(u8 value, u32 addr)
{
u32 n, byte_enables, data;
if (addr > VMALLOC_START) {
__raw_writeb(value, addr);
return;
}
n = addr % 4;
byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
data = value << (8*n);
ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
}
static inline void
__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
{
while (count--)
writeb(*vaddr++, bus_addr);
}
static inline void
__ixp4xx_writew(u16 value, u32 addr)
{
u32 n, byte_enables, data;
if (addr > VMALLOC_START) {
__raw_writew(value, addr);
return;
}
n = addr % 4;
byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
data = value << (8*n);
ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
}
static inline void
__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
{
while (count--)
writew(*vaddr++, bus_addr);
}
static inline void
__ixp4xx_writel(u32 value, u32 addr)
{
if (addr > VMALLOC_START) {
__raw_writel(value, addr);
return;
}
ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
}
static inline void
__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
{
while (count--)
writel(*vaddr++, bus_addr);
}
static inline unsigned char
__ixp4xx_readb(u32 addr)
{
u32 n, byte_enables, data;
if (addr > VMALLOC_START)
return __raw_readb(addr);
n = addr % 4;
byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
return 0xff;
return data >> (8*n);
}
static inline void
__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readb(bus_addr);
}
static inline unsigned short
__ixp4xx_readw(u32 addr)
{
u32 n, byte_enables, data;
if (addr > VMALLOC_START)
return __raw_readw(addr);
n = addr % 4;
byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
return 0xffff;
return data>>(8*n);
}
static inline void
__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readw(bus_addr);
}
static inline unsigned long
__ixp4xx_readl(u32 addr)
{
u32 data;
if (addr > VMALLOC_START)
return __raw_readl(addr);
if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
return 0xffffffff;
return data;
}
static inline void
__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readl(bus_addr);
}
/*
* We can use the built-in functions b/c they end up calling writeb/readb
*/
#define memset_io(c,v,l) _memset_io((c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
#define eth_io_copy_and_sum(s,c,l,b) \
eth_copy_and_sum((s),__mem_pci(c),(l),(b))
static inline int
check_signature(unsigned long bus_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (readb(bus_addr) != *signature)
goto out;
bus_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#endif
/*
* IXP4xx does not have a transparent cpu -> PCI I/O translation
* window. Instead, it has a set of registers that must be tweaked
* with the proper byte lanes, command types, and address for the
* transaction. This means that we need to override the default
* I/O functions.
*/
#define outb(p, v) __ixp4xx_outb(p, v)
#define outw(p, v) __ixp4xx_outw(p, v)
#define outl(p, v) __ixp4xx_outl(p, v)
#define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
#define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
#define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
#define inb(p) __ixp4xx_inb(p)
#define inw(p) __ixp4xx_inw(p)
#define inl(p) __ixp4xx_inl(p)
#define insb(p, v, l) __ixp4xx_insb(p, v, l)
#define insw(p, v, l) __ixp4xx_insw(p, v, l)
#define insl(p, v, l) __ixp4xx_insl(p, v, l)
static inline void
__ixp4xx_outb(u8 value, u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
data = value << (8*n);
ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
}
static inline void
__ixp4xx_outsb(u32 io_addr, u8 *vaddr, u32 count)
{
while (count--)
outb(*vaddr++, io_addr);
}
static inline void
__ixp4xx_outw(u16 value, u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
data = value << (8*n);
ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
}
static inline void
__ixp4xx_outsw(u32 io_addr, u16 *vaddr, u32 count)
{
while (count--)
outw(cpu_to_le16(*vaddr++), io_addr);
}
static inline void
__ixp4xx_outl(u32 value, u32 addr)
{
ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
}
static inline void
__ixp4xx_outsl(u32 io_addr, u32 *vaddr, u32 count)
{
while (count--)
outl(*vaddr++, io_addr);
}
static inline u8
__ixp4xx_inb(u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
return 0xff;
return data >> (8*n);
}
static inline void
__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
{
while (count--)
*vaddr++ = inb(io_addr);
}
static inline u16
__ixp4xx_inw(u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
return 0xffff;
return data>>(8*n);
}
static inline void
__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
{
while (count--)
*vaddr++ = le16_to_cpu(inw(io_addr));
}
static inline u32
__ixp4xx_inl(u32 addr)
{
u32 data;
if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
return 0xffffffff;
return data;
}
static inline void
__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
{
while (count--)
*vaddr++ = inl(io_addr);
}
#endif // __ASM_ARM_ARCH_IO_H
include/asm-arm/arch-ixp4xx/irq.h 0 → 100644
View file @ 18857d8e
/*
* irq.h
*
* Copyright (C) 2002 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#define fixup_irq(irq) (irq)
include/asm-arm/arch-ixp4xx/irqs.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/irqs.h
*
* IRQ definitions for IXP4XX based systems
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _ARCH_IXP4XX_IRQS_H_
#define _ARCH_IXP4XX_IRQS_H_
#define NR_IRQS 32
#define IRQ_IXP4XX_NPEA 0
#define IRQ_IXP4XX_NPEB 1
#define IRQ_IXP4XX_NPEC 2
#define IRQ_IXP4XX_QM1 3
#define IRQ_IXP4XX_QM2 4
#define IRQ_IXP4XX_TIMER1 5
#define IRQ_IXP4XX_GPIO0 6
#define IRQ_IXP4XX_GPIO1 7
#define IRQ_IXP4XX_PCI_INT 8
#define IRQ_IXP4XX_PCI_DMA1 9
#define IRQ_IXP4XX_PCI_DMA2 10
#define IRQ_IXP4XX_TIMER2 11
#define IRQ_IXP4XX_USB 12
#define IRQ_IXP4XX_UART2 13
#define IRQ_IXP4XX_TIMESTAMP 14
#define IRQ_IXP4XX_UART1 15
#define IRQ_IXP4XX_WDOG 16
#define IRQ_IXP4XX_AHB_PMU 17
#define IRQ_IXP4XX_XSCALE_PMU 18
#define IRQ_IXP4XX_GPIO2 19
#define IRQ_IXP4XX_GPIO3 20
#define IRQ_IXP4XX_GPIO4 21
#define IRQ_IXP4XX_GPIO5 22
#define IRQ_IXP4XX_GPIO6 23
#define IRQ_IXP4XX_GPIO7 24
#define IRQ_IXP4XX_GPIO8 25
#define IRQ_IXP4XX_GPIO9 26
#define IRQ_IXP4XX_GPIO10 27
#define IRQ_IXP4XX_GPIO11 28
#define IRQ_IXP4XX_GPIO12 29
#define IRQ_IXP4XX_SW_INT1 30
#define IRQ_IXP4XX_SW_INT2 31
#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
/*
* IXDP425 board IRQs
*/
#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8
/*
* PrPMC1100 Board IRQs
*/
#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
/*
* ADI Coyote Board IRQs
*/
#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
#endif
include/asm-arm/arch-ixp4xx/ixdp425.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/ixdp425.h
*
* IXDP425 platform specific definitions
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define IXDP425_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define IXDP425_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
#define IXDP425_SDA_PIN 7
#define IXDP425_SCL_PIN 6
/*
* IXDP425 PCI IRQs
*/
#define IXDP425_PCI_MAX_DEV 4
#define IXDP425_PCI_IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define IXDP425_PCI_INTA_PIN 11
#define IXDP425_PCI_INTB_PIN 10
#define IXDP425_PCI_INTC_PIN 9
#define IXDP425_PCI_INTD_PIN 8
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
*
* Register definitions for IXP4xx chipset. This file contains
* register location and bit definitions only. Platform specific
* definitions and helper function declarations are in platform.h
* and machine-name.h.
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#ifndef _ASM_ARM_IXP4XX_H_
#define _ASM_ARM_IXP4XX_H_
/*
* IXP4xx Linux Memory Map:
*
* Phy Size Virt Description
* =========================================================================
*
* 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
*
* 0x48000000 0x04000000 ioremap'd PCI Memory Space
*
* 0x50000000 0x10000000 ioremap'd EXP BUS
*
* 0x6000000 0x00004000 ioremap'd QMgr
*
* 0xC0000000 0x00001000 0xffbfe000 PCI CFG
*
* 0xC4000000 0x00001000 0xffbfd000 EXP CFG
*
* 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals
*/
/*
* Expansion BUS Configuration registers
*/
#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFD000)
#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
/*
* PCI Config registers
*/
#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFD000)
#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
/*
* Peripheral space
*/
#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000)
#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000)
#define IXP4XX_EXP_CS0_OFFSET 0x00
#define IXP4XX_EXP_CS1_OFFSET 0x04
#define IXP4XX_EXP_CS2_OFFSET 0x08
#define IXP4XX_EXP_CS3_OFFSET 0x0C
#define IXP4XX_EXP_CS4_OFFSET 0x10
#define IXP4XX_EXP_CS5_OFFSET 0x14
#define IXP4XX_EXP_CS6_OFFSET 0x18
#define IXP4XX_EXP_CS7_OFFSET 0x1C
#define IXP4XX_EXP_CFG0_OFFSET 0x20
#define IXP4XX_EXP_CFG1_OFFSET 0x24
#define IXP4XX_EXP_CFG2_OFFSET 0x28
#define IXP4XX_EXP_CFG3_OFFSET 0x2C
/*
* Expansion Bus Controller registers.
*/
#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
/*
* Peripheral Space Register Region Base Addresses
*/
#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
/*
* Constants to make it easy to access Interrupt Controller registers
*/
#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
/*
* Interrupt Controller Register Definitions.
*/
#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
/*
* Constants to make it easy to access GPIO registers
*/
#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
#define IXP4XX_GPIO_GPOER_OFFSET 0x04
#define IXP4XX_GPIO_GPINR_OFFSET 0x08
#define IXP4XX_GPIO_GPISR_OFFSET 0x0C
#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
/*
* GPIO Register Definitions.
* [Only perform 32bit reads/writes]
*/
#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
/*
* GPIO register bit definitions
*/
/* Interrupt styles
*/
#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
/*
* Mask used to clear interrupt styles
*/
#define IXP4XX_GPIO_STYLE_CLEAR 0x7
#define IXP4XX_GPIO_STYLE_SIZE 3
/*
* Constants to make it easy to access Timer Control/Status registers
*/
#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
/*
* Operating System Timer Register Definitions.
*/
#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
/*
* Timer register values and bit definitions
*/
#define IXP4XX_OST_ENABLE 0x00000001
#define IXP4XX_OST_ONE_SHOT 0x00000002
/* Low order bits of reload value ignored */
#define IXP4XX_OST_RELOAD_MASK 0x00000004
#define IXP4XX_OST_DISABLED 0x00000000
#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
#define IXP4XX_WDT_KEY 0x0000482E
#define IXP4XX_WDT_RESET_ENABLE 0x00000001
#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
/*
* Constants to make it easy to access PCI Control/Status registers
*/
#define PCI_NP_AD_OFFSET 0x00
#define PCI_NP_CBE_OFFSET 0x04
#define PCI_NP_WDATA_OFFSET 0x08
#define PCI_NP_RDATA_OFFSET 0x0c
#define PCI_CRP_AD_CBE_OFFSET 0x10
#define PCI_CRP_WDATA_OFFSET 0x14
#define PCI_CRP_RDATA_OFFSET 0x18
#define PCI_CSR_OFFSET 0x1c
#define PCI_ISR_OFFSET 0x20
#define PCI_INTEN_OFFSET 0x24
#define PCI_DMACTRL_OFFSET 0x28
#define PCI_AHBMEMBASE_OFFSET 0x2c
#define PCI_AHBIOBASE_OFFSET 0x30
#define PCI_PCIMEMBASE_OFFSET 0x34
#define PCI_AHBDOORBELL_OFFSET 0x38
#define PCI_PCIDOORBELL_OFFSET 0x3C
#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
/*
* PCI Control/Status Registers
*/
#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
/*
* PCI register values and bit definitions
*/
/* CSR bit definitions */
#define PCI_CSR_HOST 0x00000001
#define PCI_CSR_ARBEN 0x00000002
#define PCI_CSR_ADS 0x00000004
#define PCI_CSR_PDS 0x00000008
#define PCI_CSR_ABE 0x00000010
#define PCI_CSR_DBT 0x00000020
#define PCI_CSR_ASE 0x00000100
#define PCI_CSR_IC 0x00008000
/* ISR (Interrupt status) Register bit definitions */
#define PCI_ISR_PSE 0x00000001
#define PCI_ISR_PFE 0x00000002
#define PCI_ISR_PPE 0x00000004
#define PCI_ISR_AHBE 0x00000008
#define PCI_ISR_APDC 0x00000010
#define PCI_ISR_PADC 0x00000020
#define PCI_ISR_ADB 0x00000040
#define PCI_ISR_PDB 0x00000080
/* INTEN (Interrupt Enable) Register bit definitions */
#define PCI_INTEN_PSE 0x00000001
#define PCI_INTEN_PFE 0x00000002
#define PCI_INTEN_PPE 0x00000004
#define PCI_INTEN_AHBE 0x00000008
#define PCI_INTEN_APDC 0x00000010
#define PCI_INTEN_PADC 0x00000020
#define PCI_INTEN_ADB 0x00000040
#define PCI_INTEN_PDB 0x00000080
/*
* Shift value for byte enable on NP cmd/byte enable register
*/
#define IXP4XX_PCI_NP_CBE_BESL 4
/*
* PCI commands supported by NP access unit
*/
#define NP_CMD_IOREAD 0x2
#define NP_CMD_IOWRITE 0x3
#define NP_CMD_CONFIGREAD 0xa
#define NP_CMD_CONFIGWRITE 0xb
#define NP_CMD_MEMREAD 0x6
#define NP_CMD_MEMWRITE 0x7
/*
* Constants for CRP access into local config space
*/
#define CRP_AD_CBE_BESL 20
#define CRP_AD_CBE_WRITE 0x00010000
/*
* USB Device Controller
*
* These are used by the USB gadget driver, so they don't follow the
* IXP4XX_ naming convetions.
*
*/
# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
/* UDC Undocumented - Reserved1 */
#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
/* UDC Undocumented - Reserved2 */
#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
/* UDC Undocumented - Reserved3 */
#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
/* UDC Control Register */
#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
/* UDC Endpoint 0 Control/Status Register */
#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
/* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
/* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
/* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
/* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
/* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
/* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
/* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
/* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
/* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
/* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
/* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
/* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
/* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
/* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
/* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
/* UDC Frame Number Register High */
#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
/* UDC Frame Number Register Low */
#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
/* UDC Byte Count Reg 2 */
#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
/* UDC Byte Count Reg 4 */
#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
/* UDC Byte Count Reg 7 */
#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
/* UDC Byte Count Reg 9 */
#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
/* UDC Byte Count Reg 12 */
#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
/* UDC Byte Count Reg 14 */
#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
/* UDC Endpoint 0 Data Register */
#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
/* UDC Endpoint 1 Data Register */
#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
/* UDC Endpoint 2 Data Register */
#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
/* UDC Endpoint 3 Data Register */
#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
/* UDC Endpoint 4 Data Register */
#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
/* UDC Endpoint 5 Data Register */
#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
/* UDC Endpoint 6 Data Register */
#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
/* UDC Endpoint 7 Data Register */
#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
/* UDC Endpoint 8 Data Register */
#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
/* UDC Endpoint 9 Data Register */
#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
/* UDC Endpoint 10 Data Register */
#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
/* UDC Endpoint 11 Data Register */
#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
/* UDC Endpoint 12 Data Register */
#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
/* UDC Endpoint 13 Data Register */
#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
/* UDC Endpoint 14 Data Register */
#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
/* UDC Endpoint 15 Data Register */
#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
/* UDC Interrupt Control Register 0 */
#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
/* UDC Interrupt Control Register 1 */
#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
/* UDC Status Interrupt Register 0 */
#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
/* UDC Status Interrupt Register 1 */
#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
#endif
include/asm-arm/arch-ixp4xx/memory.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-ixp4xx/memory.h
*
* Copyright (c) 2001-2004 MontaVista Software, Inc.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define TASK_SIZE (0xbf000000UL)
#define TASK_SIZE_26 (0x04000000UL)
/*
* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
#define TASK_UNMAPPED_BASE (0x40000000)
#define PAGE_OFFSET (0xc0000000UL)
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x00000000UL)
/*
* physical vs virtual ram conversion
*/
#define __virt_to_phys__is_a_macro
#define __phys_to_virt__is_a_macro
#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*
* These are dummies for now.
*/
#define __virt_to_bus__is_a_macro
#define __bus_to_virt__is_a_macro
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif
include/asm-arm/arch-ixp4xx/param.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-ixp4xx/param.h
*/
include/asm-arm/arch-ixp4xx/platform.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/platform.h
*
* Constants and functions that are useful to IXP4xx platform-specific code
* and device drivers.
*
* Copyright (C) 2004 MontaVista Software, Inc.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#ifndef __ASSEMBLY__
#include <asm/types.h>
/*
* Expansion bus memory regions
*/
#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000)
#define IXP4XX_EXP_BUS_CSX_REGION_SIZE (0x01000000)
#define IXP4XX_EXP_BUS_CS0_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x00000000)
#define IXP4XX_EXP_BUS_CS1_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x01000000)
#define IXP4XX_EXP_BUS_CS2_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x02000000)
#define IXP4XX_EXP_BUS_CS3_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x03000000)
#define IXP4XX_EXP_BUS_CS4_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x04000000)
#define IXP4XX_EXP_BUS_CS5_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x05000000)
#define IXP4XX_EXP_BUS_CS6_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x06000000)
#define IXP4XX_EXP_BUS_CS7_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x07000000)
#define IXP4XX_FLASH_WRITABLE (0x2)
#define IXP4XX_FLASH_DEFAULT (0xbcd23c40)
#define IXP4XX_FLASH_WRITE (0xbcd23c42)
/*
* Clock Speed Definitions.
*/
#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
#define IXP4XX_UART_XTAL 14745600
/*
* The IXP4xx chips do not have an I2C unit, so GPIO lines are just
* used to
* Used as platform_data to provide GPIO pin information to the ixp42x
* I2C driver.
*/
struct ixp4xx_i2c_pins {
unsigned long sda_pin;
unsigned long scl_pin;
};
/*
* Functions used by platform-level setup code
*/
extern void ixp4xx_map_io(void);
extern void ixp4xx_init_irq(void);
extern void ixp4xx_pci_preinit(void);
struct pci_sys_data;
extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
/*
* GPIO-functions
*/
/*
* The following converted to the real HW bits the gpio_line_config
*/
/* GPIO pin types */
#define IXP4XX_GPIO_OUT 0x1
#define IXP4XX_GPIO_IN 0x2
#define IXP4XX_GPIO_INTSTYLE_MASK 0x7C /* Bits [6:2] define interrupt style */
/*
* GPIO interrupt types.
*/
#define IXP4XX_GPIO_ACTIVE_HIGH 0x4 /* Default */
#define IXP4XX_GPIO_ACTIVE_LOW 0x8
#define IXP4XX_GPIO_RISING_EDGE 0x10
#define IXP4XX_GPIO_FALLING_EDGE 0x20
#define IXP4XX_GPIO_TRANSITIONAL 0x40
/* GPIO signal types */
#define IXP4XX_GPIO_LOW 0
#define IXP4XX_GPIO_HIGH 1
/* GPIO Clocks */
#define IXP4XX_GPIO_CLK_0 14
#define IXP4XX_GPIO_CLK_1 15
extern void gpio_line_config(u8 line, u32 style);
static inline void gpio_line_get(u8 line, int *value)
{
*value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
}
static inline void gpio_line_set(u8 line, int value)
{
if (value == IXP4XX_GPIO_HIGH)
*IXP4XX_GPIO_GPOUTR |= (1 << line);
else if (value == IXP4XX_GPIO_LOW)
*IXP4XX_GPIO_GPOUTR &= ~(1 << line);
}
static inline void gpio_line_isr_clear(u8 line)
{
*IXP4XX_GPIO_GPISR = (1 << line);
}
#endif // __ASSEMBLY__
include/asm-arm/arch-ixp4xx/prpmc1100.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/prpmc1100.h
*
* Motorolla PrPMC1100 platform specific definitions
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
#define PRPMC1100_PCI_MIN_DEVID 10
#define PRPMC1100_PCI_MAX_DEVID 16
#define PRPMC1100_PCI_IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define PRPMC1100_PCI_INTA_PIN 11
#define PRPMC1100_PCI_INTB_PIN 10
#define PRPMC1100_PCI_INTC_PIN 9
#define PRPMC1100_PCI_INTD_PIN 8
include/asm-arm/arch-ixp4xx/serial.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/serial.h
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002-2004 MontaVista Software, Inc.
*
*/
#ifndef _ARCH_SERIAL_H_
#define _ARCH_SERIAL_H_
/*
* We don't hardcode our serial port information but instead
* fill it in dynamically based on our platform in arch->map_io.
* This allows for per-board serial ports w/o a bunch of
* #ifdefs in this file.
*/
#define STD_SERIAL_PORT_DEFNS
#define EXTRA_SERIAL_PORT_DEFNS
/*
* IXP4XX uses 15.6MHz clock for uart
*/
#define BASE_BAUD ( IXP4XX_UART_XTAL / 16 )
#endif // _ARCH_SERIAL_H_
include/asm-arm/arch-ixp4xx/system.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4x//system.h
*
* Copyright (C) 2002 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/hardware.h>
static inline void arch_idle(void)
{
#if 0
if (!hlt_counter)
cpu_do_idle(0);
#endif
}
static inline void arch_reset(char mode)
{
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */
cpu_reset(0);
} else {
/* Use on-chip reset capability */
/* set the "key" register to enable access to
* "timer" and "enable" registers
*/
*IXP4XX_OSWK = 0x482e;
/* write 0 to the timer register for an immidiate reset */
*IXP4XX_OSWT = 0;
/* disable watchdog interrupt, enable reset, enable count */
*IXP4XX_OSWE = 0x3;
}
}
include/asm-arm/arch-ixp4xx/time.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-ixp4xx/time.h
*
* We implement timer code in arch/arm/mach-ixp4xx/time.c
*
*/
include/asm-arm/arch-ixp4xx/timex.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-ixp4xx/timex.h
*
*/
#include <asm/hardware.h>
/*
* We use IXP425 General purpose timer for our timer needs, it runs at 66 MHz
*/
#define CLOCK_TICK_RATE (IXP4XX_PERIPHERAL_BUS_CLOCK * 1000000)
include/asm-arm/arch-ixp4xx/uncompress.h 0 → 100644
View file @ 18857d8e
/*
* include/asm-arm/arch-ixp4xx/uncompress.h
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _ARCH_UNCOMPRESS_H_
#define _ARCH_UNCOMPRESS_H_
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
static volatile u32* uart_base;
static __inline__ void putc(char c)
{
/* Check THRE and TEMT bits before we transmit the character.
*/
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE);
*uart_base = c;
}
/*
* This does not append a newline
*/
static void puts(const char *s)
{
while (*s)
{
putc(*s);
if (*s == '\n')
putc('\r');
s++;
}
}
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
/*
* Coyote only has UART2 connected
*/
if (__machine_arch_type == MACH_TYPE_ADI_COYOTE)
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
}
/*
* arch_id is a variable in decompress_kernel()
*/
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
#define arch_decomp_wdog()
#endif
include/asm-arm/arch-ixp4xx/vmalloc.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-ixp4xx/vmalloc.h
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (0xFF000000)
include/asm-arm/arch-pxa/dma.h
View file @ 18857d8e
......@@ -29,9 +29,21 @@ typedef struct {
volatile u32 dcmd; /* DCMD value for the current transfer */
} pxa_dma_desc;
/*
* DMA registration
*/
#if defined(CONFIG_PXA27x)
#define PXA_DMA_CHANNELS 32
#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 16 : 8)
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 8,
DMA_PRIO_LOW = 16
} pxa_dma_prio;
#elif defined(CONFIG_PXA25x)
#define PXA_DMA_CHANNELS 16
#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 8 : 4)
typedef enum {
DMA_PRIO_HIGH = 0,
......@@ -39,6 +51,12 @@ typedef enum {
DMA_PRIO_LOW = 8
} pxa_dma_prio;
#endif
/*
* DMA registration
*/
int pxa_request_dma (char *name,
pxa_dma_prio prio,
void (*irq_handler)(int, void *, struct pt_regs *),
......
include/asm-arm/arch-pxa/hardware.h
View file @ 18857d8e
......@@ -16,15 +16,6 @@
#include <asm/mach-types.h>
/*
* These are statically mapped PCMCIA IO space for designs using it as a
* generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
* The actual PCMCIA code is mapping required IO region at run time.
*/
#define PCMCIA_IO_0_BASE 0xf6000000
#define PCMCIA_IO_1_BASE 0xf7000000
/*
* We requires absolute addresses.
*/
......@@ -38,15 +29,21 @@
#define UNCACHED_ADDR UNCACHED_PHYS_0
/*
* Intel PXA internal I/O mappings:
* Intel PXA2xx internal register mapping:
*
* 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
* 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
* 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
* 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
* 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
* 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
* 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
*
* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
* Note that not all PXA2xx chips implement all those addresses, and the
* kernel only maps the minimum needed range of this mapping.
*/
#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
#define io_v2p(x) (0x40000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
#ifndef __ASSEMBLY__
......
include/asm-arm/arch-pxa/pxa-regs.h
View file @ 18857d8e
......@@ -10,6 +10,9 @@
* published by the Free Software Foundation.
*/
#ifndef __PXA_REGS_H
#define __PXA_REGS_H
#include <linux/config.h>
// FIXME hack so that SA-1111.h will work [cb]
......@@ -101,6 +104,15 @@ typedef void (*ExcpHndlr) (void) ;
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
#ifdef CONFIG_PXA27x
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_ENRINTR (1 << 9) /* The end of Receive */
#endif
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
......@@ -109,6 +121,7 @@ typedef void (*ExcpHndlr) (void) ;
#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
#define DRCMR(n) __REG2(0x40000100, (n)<<2)
#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
......@@ -150,6 +163,10 @@ typedef void (*ExcpHndlr) (void) ;
#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
#define DRCMR39 __REG(0x4000019C) /* Reserved */
#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
#define DRCMRRXSADR DRCMR2
#define DRCMRTXSADR DRCMR3
#define DRCMRRXBTRBR DRCMR4
......@@ -169,9 +186,10 @@ typedef void (*ExcpHndlr) (void) ;
#define DRCMRTXSTTHR DRCMR20
#define DRCMRRXMMC DRCMR21
#define DRCMRTXMMC DRCMR22
#define DRCMRUDC(x) DRCMR((x) + 24)
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
......@@ -398,6 +416,12 @@ typedef void (*ExcpHndlr) (void) ;
#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
#define ICR_START (1 << 0) /* start bit */
#define ICR_STOP (1 << 1) /* stop bit */
#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
......@@ -523,7 +547,10 @@ typedef void (*ExcpHndlr) (void) ;
/*
* USB Device Controller
* PXA25x and PXA27x USB device controller registers are different.
*/
#if defined(CONFIG_PXA25x)
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
......@@ -679,11 +706,246 @@ typedef void (*ExcpHndlr) (void) ;
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
#elif defined(CONFIG_PXA27x)
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
Protocol Port Support */
#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
Support */
#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
Enable */
#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
#define UDCCR_ACN_S 11
#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
#define UDCCR_AIN_S 8
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
Setting Number */
#define UDCCR_AAISN_S 5
#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
Configuration */
#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
Error */
#define UDCCR_UDR (1 << 2) /* UDC Resume */
#define UDCCR_UDA (1 << 1) /* UDC Active */
#define UDCCR_UDE (1 << 0) /* UDC Enable */
#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
Interrupt Enable */
#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
Edge Interrupt Enable */
#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
Edge Interrupt Enable */
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
Interrupt Enable */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_FST (1 << 5) /* Force Stall */
#define UDCCSR0_SST (1 << 4) /* Sent Stall */
#define UDCCSR0_DME (1 << 3) /* DMA Enable */
#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
#define UDCCSR_FST (1 << 5) /* Force STALL */
#define UDCCSR_SST (1 << 4) /* Sent STALL */
#define UDCCSR_DME (1 << 3) /* DMA Enable */
#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
#define UDCDN(x) __REG2(0x40600300, (x)<<2)
#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
#define UDCCN(x) __REG2(0x40600400, (x)<<2)
#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
#define UDCCONR_CN_S (25)
#define UDCCONR_IN (0x07 << 22) /* Interface Number */
#define UDCCONR_IN_S (22)
#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
#define UDCCONR_AISN_S (19)
#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
#define UDCCONR_EN_S (15)
#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
#define UDCCONR_ET_S (13)
#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
#define UDCCONR_MPS_S (2)
#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDC_FNR_MASK (0x7ff)
#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK (0x3ff)
#endif
/*
* Fast Infrared Communication Port
*/
#define FICP __REG(0x40800000) /* Start of FICP area */
#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
......@@ -691,15 +953,27 @@ typedef void (*ExcpHndlr) (void) ;
#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
#define ICCR0_AME (1 << 7) /* Address match enable */
#define ICCR0_AME (1 << 7) /* Adress match enable */
#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
#define ICCR0_RIE (1 << 5) /* Receive FIFO interrupt enable */
#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
#define ICCR0_RXE (1 << 4) /* Receive enable */
#define ICCR0_TXE (1 << 3) /* Transmit enable */
#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
#define ICCR0_LBM (1 << 1) /* Loopback mode */
#define ICCR0_ITR (1 << 0) /* IrDA transmission */
#ifdef CONFIG_CPU_BULVERDE
#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
#endif
#ifdef CONFIG_CPU_BULVERDE
#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
#endif
#define ICSR0_FRE (1 << 5) /* Framing error */
#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
......@@ -724,7 +998,10 @@ typedef void (*ExcpHndlr) (void) ;
#define RTAR __REG(0x40900004) /* RTC Alarm Register */
#define RTSR __REG(0x40900008) /* RTC Status Register */
#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
......@@ -739,7 +1016,10 @@ typedef void (*ExcpHndlr) (void) ;
#define OSMR1 __REG(0x40A00004) /* */
#define OSMR2 __REG(0x40A00008) /* */
#define OSMR3 __REG(0x40A0000C) /* */
#define OSMR4 __REG(0x40A00080) /* */
#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
#define OMCR4 __REG(0x40A000C0) /* */
#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
......@@ -819,11 +1099,52 @@ typedef void (*ExcpHndlr) (void) ;
#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
/* More handy macros. The argument is a literal GPIO number. */
#define GPIO_bit(x) (1 << ((x) & 0x1f))
#ifdef CONFIG_PXA27x
/* Interrupt Controller */
#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
#else
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
......@@ -833,6 +1154,9 @@ typedef void (*ExcpHndlr) (void) ;
#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
#endif
/* GPIO alternate function assignments */
#define GPIO1_RST 1 /* reset */
......@@ -1047,14 +1371,73 @@ typedef void (*ExcpHndlr) (void) ;
#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
#define PCMD(x) __REG2(0x40F00080, (x)<<2)
#define PCMD0 __REG(0x40F00080 + 0 * 4)
#define PCMD1 __REG(0x40F00080 + 1 * 4)
#define PCMD2 __REG(0x40F00080 + 2 * 4)
#define PCMD3 __REG(0x40F00080 + 3 * 4)
#define PCMD4 __REG(0x40F00080 + 4 * 4)
#define PCMD5 __REG(0x40F00080 + 5 * 4)
#define PCMD6 __REG(0x40F00080 + 6 * 4)
#define PCMD7 __REG(0x40F00080 + 7 * 4)
#define PCMD8 __REG(0x40F00080 + 8 * 4)
#define PCMD9 __REG(0x40F00080 + 9 * 4)
#define PCMD10 __REG(0x40F00080 + 10 * 4)
#define PCMD11 __REG(0x40F00080 + 11 * 4)
#define PCMD12 __REG(0x40F00080 + 12 * 4)
#define PCMD13 __REG(0x40F00080 + 13 * 4)
#define PCMD14 __REG(0x40F00080 + 14 * 4)
#define PCMD15 __REG(0x40F00080 + 15 * 4)
#define PCMD16 __REG(0x40F00080 + 16 * 4)
#define PCMD17 __REG(0x40F00080 + 17 * 4)
#define PCMD18 __REG(0x40F00080 + 18 * 4)
#define PCMD19 __REG(0x40F00080 + 19 * 4)
#define PCMD20 __REG(0x40F00080 + 20 * 4)
#define PCMD21 __REG(0x40F00080 + 21 * 4)
#define PCMD22 __REG(0x40F00080 + 22 * 4)
#define PCMD23 __REG(0x40F00080 + 23 * 4)
#define PCMD24 __REG(0x40F00080 + 24 * 4)
#define PCMD25 __REG(0x40F00080 + 25 * 4)
#define PCMD26 __REG(0x40F00080 + 26 * 4)
#define PCMD27 __REG(0x40F00080 + 27 * 4)
#define PCMD28 __REG(0x40F00080 + 28 * 4)
#define PCMD29 __REG(0x40F00080 + 29 * 4)
#define PCMD30 __REG(0x40F00080 + 30 * 4)
#define PCMD31 __REG(0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
#define PCMD_LC (1<<10)
/* FIXME: PCMD_SQC need be checked. */
#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
bit 9 should be 0 all day. */
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
#define PCFR_PI2C_EN (0x1 << 6)
#define PSSR_OTGPH (1 << 7) /* OTG Peripheral control Hold */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PCFR_RO (1 << 15) /* RDH Override */
#define PCFR_PO (1 << 14) /* PH Override */
#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
......@@ -1137,21 +1520,35 @@ typedef void (*ExcpHndlr) (void) ;
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
#define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */
#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
......@@ -1175,6 +1572,12 @@ typedef void (*ExcpHndlr) (void) ;
#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
#define TMEDCR __REG(0x44000044) /* TMED Control Register */
#define LCCR3_1BPP (0 << 24)
#define LCCR3_2BPP (1 << 24)
#define LCCR3_4BPP (2 << 24)
#define LCCR3_8BPP (3 << 24)
#define LCCR3_16BPP (4 << 24)
#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
......@@ -1185,15 +1588,27 @@ typedef void (*ExcpHndlr) (void) ;
#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */
#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */
/* Select */
#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
#define LCCR0_SFM (1 << 4) /* Start of frame mask */
#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
#define LCCR0_EFM (1 << 6) /* End of Frame mask */
#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */
#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */
#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */
/* display mode) */
#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
/* display */
#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
/* display */
#define LCCR0_DIS (1 << 10) /* LCD Disable */
#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
......@@ -1255,8 +1670,15 @@ typedef void (*ExcpHndlr) (void) ;
#define LCCR3_API_S 16
#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
#define LCCR3_PCP (1 << 22) /* pixel clock polarity */
#define LCCR3_OEP (1 << 23) /* output enable polarity */
#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
#define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */
/* active display mode) */
#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
#if 0
#define LCCR3_BPP (7 << 24) /* bits per pixel */
#define LCCR3_BPP_S 24
......@@ -1364,4 +1786,274 @@ typedef void (*ExcpHndlr) (void) ;
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
#ifdef CONFIG_PXA27x
/*
* Keypad
*/
#define KPC __REG(0x41500000) /* Keypad Interface Control register */
#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
#define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
#define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */
#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
#define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
#define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
#define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */
#define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */
#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
#define KPDK_DKP (0x1 << 31)
#define KPDK_DK7 (0x1 << 7)
#define KPDK_DK6 (0x1 << 6)
#define KPDK_DK5 (0x1 << 5)
#define KPDK_DK4 (0x1 << 4)
#define KPDK_DK3 (0x1 << 3)
#define KPDK_DK2 (0x1 << 2)
#define KPDK_DK1 (0x1 << 1)
#define KPDK_DK0 (0x1 << 0)
#define KPREC_OF1 (0x1 << 31)
#define kPREC_UF1 (0x1 << 30)
#define KPREC_OF0 (0x1 << 15)
#define KPREC_UF0 (0x1 << 14)
#define KPMK_MKP (0x1 << 31)
#define KPAS_SO (0x1 << 31)
#define KPASMKPx_SO (0x1 << 31)
/*
* UHC: USB Host Controller (OHCI-like) register definitions
*/
#define UHC_BASE_PHYS (0x4C000000)
#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
Interrupt Enable*/
#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
/* Camera Interface */
#define CICR0 __REG(0x50000000)
#define CICR1 __REG(0x50000004)
#define CICR2 __REG(0x50000008)
#define CICR3 __REG(0x5000000C)
#define CICR4 __REG(0x50000010)
#define CISR __REG(0x50000014)
#define CIFR __REG(0x50000018)
#define CITOR __REG(0x5000001C)
#define CIBR0 __REG(0x50000028)
#define CIBR1 __REG(0x50000030)
#define CIBR2 __REG(0x50000038)
#define CICR0_DMAEN (1 << 31) /* DMA request enable */
#define CICR0_PAR_EN (1 << 30) /* Parity enable */
#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
#define CICR0_ENB (1 << 28) /* Camera interface enable */
#define CICR0_DIS (1 << 27) /* Camera interface disable */
#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
#define CICR0_TOM (1 << 9) /* Time-out mask */
#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
#define CICR0_EOLM (1 << 6) /* End-of-line mask */
#define CICR0_PERRM (1 << 5) /* Parity-error mask */
#define CICR0_QDM (1 << 4) /* Quick-disable mask */
#define CICR0_CDM (1 << 3) /* Disable-done mask */
#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
#define CICR1_TBIT (1 << 31) /* Transparency bit */
#define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */
#define CICR1_PPL (0x3f << 15) /* Pixels per line mask */
#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
#define CICR1_RGB_F (1 << 11) /* RGB format */
#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
#define CICR1_DW (0x7 << 0) /* Data width mask */
#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
wait count mask */
#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
wait count mask */
#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
wait count mask */
#define CICR2_FSW (0x7 << 0) /* Frame stabilization
wait count mask */
#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
wait count mask */
#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
wait count mask */
#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
wait count mask */
#define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */
#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
#define CISR_FTO (1 << 15) /* FIFO time-out */
#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
#define CISR_EOL (1 << 8) /* End of line */
#define CISR_PAR_ERR (1 << 7) /* Parity error */
#define CISR_CQD (1 << 6) /* Camera interface quick disable */
#define CISR_SOF (1 << 5) /* Start of frame */
#define CISR_CDD (1 << 4) /* Camera interface disable done */
#define CISR_EOF (1 << 3) /* End of frame */
#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
#define SRAM_SIZE 0x40000 /* 4x64K */
#define SRAM_MEM_PHYS 0x5C000000
#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
#endif
#endif
include/asm-arm/arch-pxa/pxafb.h 0 → 100644
View file @ 18857d8e
/*
* linux/include/asm-arm/arch-pxa/pxafb.h
*
* Support for the xscale frame buffer.
*
* Author: Jean-Frederic Clere
* Created: Sep 22, 2003
* Copyright: jfclere@sinix.net
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* This structure describes the machine which we are running on.
* It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
* of linux/drivers/video/pxafb.c
*/
struct pxafb_mach_info {
u_long pixclock;
u_short xres;
u_short yres;
u_char bpp;
u_char hsync_len;
u_char left_margin;
u_char right_margin;
u_char vsync_len;
u_char upper_margin;
u_char lower_margin;
u_char sync;
u_int cmap_greyscale:1,
cmap_inverse:1,
cmap_static:1,
unused:29;
/* The following should be defined in LCCR0
* LCCR0_Act or LCCR0_Pas Active or Passive
* LCCR0_Sngl or LCCR0_Dual Single/Dual panel
* LCCR0_Mono or LCCR0_Color Mono/Color
* LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
* LCCR0_DMADel(Tcpu) (optional) DMA request delay
*
* The following should not be defined in LCCR0:
* LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
* LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
*/
u_int lccr0;
/* The following should be defined in LCCR3
* LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
* LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
* LCCR3_Acb(X) AB Bias pin frequency
* LCCR3_DPC (optional) Double Pixel Clock mode (untested)
*
* The following should not be defined in LCCR3
* LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
*/
u_int lccr3;
void (*pxafb_backlight_power)(int);
void (*pxafb_lcd_power)(int);
};
void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
include/asm-arm/arch-s3c2410/time.h
View file @ 18857d8e
......@@ -122,7 +122,7 @@ void __init time_init (void)
* of 11.25MHz, and a tcnt of 56250.
*/
if (machine_is_h1940()) {
if (machine_is_h1940() || machine_is_smdk2410() ) {
timer_ticks_usec = s3c2410_pclk / (1000*1000);
timer_ticks_usec /= 6;
......
include/asm-arm/spinlock.h
View file @ 18857d8e
......@@ -89,7 +89,7 @@ static inline void _raw_write_lock(rwlock_t *rw)
" strexeq %0, %2, [%1]\n"
" teq %0, #0\n"
" bne 1b"
: "=r" (tmp)
: "=&r" (tmp)
: "r" (&rw->lock), "r" (0x80000000)
: "cc", "memory");
}
......@@ -151,7 +151,7 @@ static inline int _raw_write_trylock(rwlock_t *rw)
"1: ldrex %0, [%1]\n"
" teq %0, #0\n"
" strexeq %0, %2, [%1]"
: "=r" (tmp)
: "=&r" (tmp)
: "r" (&rw->lock), "r" (0x80000000)
: "cc", "memory");
......
include/asm-arm/thread_info.h
View file @ 18857d8e
......@@ -40,7 +40,7 @@ struct cpu_context_save {
/*
* low level task data that entry.S needs immediate access to.
* We assume cpu_context follows immedately after cpu_domain.
* __switch_to() assumes cpu_context follows immediately after cpu_domain.
*/
struct thread_info {
unsigned long flags; /* low level flags */
......
include/linux/pci_ids.h
View file @ 18857d8e
......@@ -2145,6 +2145,7 @@
#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca
#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb
#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea
#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500
#define PCI_VENDOR_ID_COMPUTONE 0x8e0e
#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291
......
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