Skip to content

L
linux
Commit 18aa0dc2 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files
Options

clk: qcom: gcc-sm8550: switch to parent_hws 

Change several entries of parent_data to use parent_hws instead, which
results in slightly more ovbious code.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103145515.1164020-15-dmitry.baryshkov@linaro.org
parent 1b299e87
Hide whitespace changes
Inline Side-by-side
Showing with 126 additions and 126 deletions
drivers/clk/qcom/gcc-sm8550.c
View file @ 18aa0dc2
...@@ -82,8 +82,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { ...@@ -82,8 +82,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0_out_even", .name = "gcc_gpll0_out_even",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_gpll0.clkr.hw, &gcc_gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
...@@ -1198,8 +1198,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { ...@@ -1198,8 +1198,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.width = 4, .width = 4,
.clkr.hw.init = &(struct clk_init_data) { .clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1232,8 +1232,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { ...@@ -1232,8 +1232,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk", .name = "gcc_aggre_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1252,8 +1252,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { ...@@ -1252,8 +1252,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1272,8 +1272,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { ...@@ -1272,8 +1272,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk", .name = "gcc_aggre_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1352,8 +1352,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { ...@@ -1352,8 +1352,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk", .name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1430,8 +1430,8 @@ static struct clk_branch gcc_gp1_clk = { ...@@ -1430,8 +1430,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk", .name = "gcc_gp1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_gp1_clk_src.clkr.hw, &gcc_gp1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1448,8 +1448,8 @@ static struct clk_branch gcc_gp2_clk = { ...@@ -1448,8 +1448,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk", .name = "gcc_gp2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_gp2_clk_src.clkr.hw, &gcc_gp2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1466,8 +1466,8 @@ static struct clk_branch gcc_gp3_clk = { ...@@ -1466,8 +1466,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk", .name = "gcc_gp3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_gp3_clk_src.clkr.hw, &gcc_gp3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1483,8 +1483,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { ...@@ -1483,8 +1483,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_gpll0.clkr.hw, &gcc_gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1500,8 +1500,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { ...@@ -1500,8 +1500,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_gpll0_out_even.clkr.hw, &gcc_gpll0_out_even.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1546,8 +1546,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { ...@@ -1546,8 +1546,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
.enable_mask = BIT(3), .enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk", .name = "gcc_pcie_0_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pcie_0_aux_clk_src.clkr.hw, &gcc_pcie_0_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1594,8 +1594,8 @@ static struct clk_branch gcc_pcie_0_phy_rchng_clk = { ...@@ -1594,8 +1594,8 @@ static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
.enable_mask = BIT(22), .enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk", .name = "gcc_pcie_0_phy_rchng_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1612,8 +1612,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { ...@@ -1612,8 +1612,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
.enable_mask = BIT(4), .enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk", .name = "gcc_pcie_0_pipe_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, &gcc_pcie_0_pipe_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1658,8 +1658,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { ...@@ -1658,8 +1658,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
.enable_mask = BIT(29), .enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk", .name = "gcc_pcie_1_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pcie_1_aux_clk_src.clkr.hw, &gcc_pcie_1_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1706,8 +1706,8 @@ static struct clk_branch gcc_pcie_1_phy_aux_clk = { ...@@ -1706,8 +1706,8 @@ static struct clk_branch gcc_pcie_1_phy_aux_clk = {
.enable_mask = BIT(24), .enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_aux_clk", .name = "gcc_pcie_1_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw, &gcc_pcie_1_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1724,8 +1724,8 @@ static struct clk_branch gcc_pcie_1_phy_rchng_clk = { ...@@ -1724,8 +1724,8 @@ static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
.enable_mask = BIT(23), .enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk", .name = "gcc_pcie_1_phy_rchng_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1742,8 +1742,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { ...@@ -1742,8 +1742,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
.enable_mask = BIT(30), .enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk", .name = "gcc_pcie_1_pipe_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, &gcc_pcie_1_pipe_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1788,8 +1788,8 @@ static struct clk_branch gcc_pdm2_clk = { ...@@ -1788,8 +1788,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk", .name = "gcc_pdm2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_pdm2_clk_src.clkr.hw, &gcc_pdm2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1982,8 +1982,8 @@ static struct clk_branch gcc_qupv3_i2c_s0_clk = { ...@@ -1982,8 +1982,8 @@ static struct clk_branch gcc_qupv3_i2c_s0_clk = {
.enable_mask = BIT(10), .enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s0_clk", .name = "gcc_qupv3_i2c_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s0_clk_src.clkr.hw, &gcc_qupv3_i2c_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2000,8 +2000,8 @@ static struct clk_branch gcc_qupv3_i2c_s1_clk = { ...@@ -2000,8 +2000,8 @@ static struct clk_branch gcc_qupv3_i2c_s1_clk = {
.enable_mask = BIT(11), .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s1_clk", .name = "gcc_qupv3_i2c_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s1_clk_src.clkr.hw, &gcc_qupv3_i2c_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2018,8 +2018,8 @@ static struct clk_branch gcc_qupv3_i2c_s2_clk = { ...@@ -2018,8 +2018,8 @@ static struct clk_branch gcc_qupv3_i2c_s2_clk = {
.enable_mask = BIT(12), .enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s2_clk", .name = "gcc_qupv3_i2c_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s2_clk_src.clkr.hw, &gcc_qupv3_i2c_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2036,8 +2036,8 @@ static struct clk_branch gcc_qupv3_i2c_s3_clk = { ...@@ -2036,8 +2036,8 @@ static struct clk_branch gcc_qupv3_i2c_s3_clk = {
.enable_mask = BIT(13), .enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s3_clk", .name = "gcc_qupv3_i2c_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s3_clk_src.clkr.hw, &gcc_qupv3_i2c_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2054,8 +2054,8 @@ static struct clk_branch gcc_qupv3_i2c_s4_clk = { ...@@ -2054,8 +2054,8 @@ static struct clk_branch gcc_qupv3_i2c_s4_clk = {
.enable_mask = BIT(14), .enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s4_clk", .name = "gcc_qupv3_i2c_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s4_clk_src.clkr.hw, &gcc_qupv3_i2c_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2072,8 +2072,8 @@ static struct clk_branch gcc_qupv3_i2c_s5_clk = { ...@@ -2072,8 +2072,8 @@ static struct clk_branch gcc_qupv3_i2c_s5_clk = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s5_clk", .name = "gcc_qupv3_i2c_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s5_clk_src.clkr.hw, &gcc_qupv3_i2c_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2090,8 +2090,8 @@ static struct clk_branch gcc_qupv3_i2c_s6_clk = { ...@@ -2090,8 +2090,8 @@ static struct clk_branch gcc_qupv3_i2c_s6_clk = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s6_clk", .name = "gcc_qupv3_i2c_s6_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s6_clk_src.clkr.hw, &gcc_qupv3_i2c_s6_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2108,8 +2108,8 @@ static struct clk_branch gcc_qupv3_i2c_s7_clk = { ...@@ -2108,8 +2108,8 @@ static struct clk_branch gcc_qupv3_i2c_s7_clk = {
.enable_mask = BIT(17), .enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s7_clk", .name = "gcc_qupv3_i2c_s7_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s7_clk_src.clkr.hw, &gcc_qupv3_i2c_s7_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2126,8 +2126,8 @@ static struct clk_branch gcc_qupv3_i2c_s8_clk = { ...@@ -2126,8 +2126,8 @@ static struct clk_branch gcc_qupv3_i2c_s8_clk = {
.enable_mask = BIT(14), .enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s8_clk", .name = "gcc_qupv3_i2c_s8_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s8_clk_src.clkr.hw, &gcc_qupv3_i2c_s8_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2144,8 +2144,8 @@ static struct clk_branch gcc_qupv3_i2c_s9_clk = { ...@@ -2144,8 +2144,8 @@ static struct clk_branch gcc_qupv3_i2c_s9_clk = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s9_clk", .name = "gcc_qupv3_i2c_s9_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_i2c_s9_clk_src.clkr.hw, &gcc_qupv3_i2c_s9_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2203,8 +2203,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { ...@@ -2203,8 +2203,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.enable_mask = BIT(22), .enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk", .name = "gcc_qupv3_wrap1_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2221,8 +2221,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { ...@@ -2221,8 +2221,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.enable_mask = BIT(23), .enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk", .name = "gcc_qupv3_wrap1_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2239,8 +2239,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { ...@@ -2239,8 +2239,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.enable_mask = BIT(24), .enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk", .name = "gcc_qupv3_wrap1_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2257,8 +2257,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { ...@@ -2257,8 +2257,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.enable_mask = BIT(25), .enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk", .name = "gcc_qupv3_wrap1_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2275,8 +2275,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { ...@@ -2275,8 +2275,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.enable_mask = BIT(26), .enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk", .name = "gcc_qupv3_wrap1_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2293,8 +2293,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { ...@@ -2293,8 +2293,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.enable_mask = BIT(27), .enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk", .name = "gcc_qupv3_wrap1_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2311,8 +2311,8 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk = { ...@@ -2311,8 +2311,8 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.enable_mask = BIT(28), .enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s6_clk", .name = "gcc_qupv3_wrap1_s6_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2329,8 +2329,8 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk = { ...@@ -2329,8 +2329,8 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s7_clk", .name = "gcc_qupv3_wrap1_s7_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2373,8 +2373,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = { ...@@ -2373,8 +2373,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.enable_mask = BIT(4), .enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk", .name = "gcc_qupv3_wrap2_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2391,8 +2391,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = { ...@@ -2391,8 +2391,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.enable_mask = BIT(5), .enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk", .name = "gcc_qupv3_wrap2_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2409,8 +2409,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = { ...@@ -2409,8 +2409,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.enable_mask = BIT(6), .enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk", .name = "gcc_qupv3_wrap2_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2427,8 +2427,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = { ...@@ -2427,8 +2427,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.enable_mask = BIT(7), .enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk", .name = "gcc_qupv3_wrap2_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2445,8 +2445,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = { ...@@ -2445,8 +2445,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.enable_mask = BIT(8), .enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk", .name = "gcc_qupv3_wrap2_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2463,8 +2463,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = { ...@@ -2463,8 +2463,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.enable_mask = BIT(9), .enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk", .name = "gcc_qupv3_wrap2_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2481,8 +2481,8 @@ static struct clk_branch gcc_qupv3_wrap2_s6_clk = { ...@@ -2481,8 +2481,8 @@ static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
.enable_mask = BIT(10), .enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s6_clk", .name = "gcc_qupv3_wrap2_s6_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2499,8 +2499,8 @@ static struct clk_branch gcc_qupv3_wrap2_s7_clk = { ...@@ -2499,8 +2499,8 @@ static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
.enable_mask = BIT(17), .enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s7_clk", .name = "gcc_qupv3_wrap2_s7_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, &gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2590,8 +2590,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { ...@@ -2590,8 +2590,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk", .name = "gcc_sdcc2_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw, &gcc_sdcc2_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2621,8 +2621,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { ...@@ -2621,8 +2621,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk", .name = "gcc_sdcc4_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_sdcc4_apps_clk_src.clkr.hw, &gcc_sdcc4_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2656,8 +2656,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { ...@@ -2656,8 +2656,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk", .name = "gcc_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2676,8 +2676,8 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { ...@@ -2676,8 +2676,8 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk", .name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2696,8 +2696,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { ...@@ -2696,8 +2696,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk", .name = "gcc_ufs_phy_ice_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2716,8 +2716,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { ...@@ -2716,8 +2716,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk", .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2736,8 +2736,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { ...@@ -2736,8 +2736,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk", .name = "gcc_ufs_phy_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2756,8 +2756,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { ...@@ -2756,8 +2756,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2774,8 +2774,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { ...@@ -2774,8 +2774,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk", .name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2792,8 +2792,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { ...@@ -2792,8 +2792,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk", .name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2810,8 +2810,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { ...@@ -2810,8 +2810,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk", .name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2830,8 +2830,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { ...@@ -2830,8 +2830,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk", .name = "gcc_ufs_phy_unipro_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2850,8 +2850,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { ...@@ -2850,8 +2850,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2868,8 +2868,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { ...@@ -2868,8 +2868,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk", .name = "gcc_usb30_prim_master_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2886,8 +2886,8 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { ...@@ -2886,8 +2886,8 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk", .name = "gcc_usb30_prim_mock_utmi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2917,8 +2917,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { ...@@ -2917,8 +2917,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk", .name = "gcc_usb3_prim_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2935,8 +2935,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { ...@@ -2935,8 +2935,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk", .name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2955,8 +2955,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { ...@@ -2955,8 +2955,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk", .name = "gcc_usb3_prim_phy_pipe_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]) {
.hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7