Merge http://lia64.bkbits.net/to-linus-2.5

into ppc970.osdl.org:/home/torvalds/v2.5/linux

arch/ia64/Kconfig

@@ -245,6 +245,12 @@ config IA64_MCA
 	  Say Y here to enable machine check support for IA-64.  If you're
 	  unsure, answer Y.
 
+config IA64_CYCLONE
+	bool "Support Cyclone(EXA) Time Source"
+	help
+		Say Y here to enable support for IBM EXA Cyclone time source.
+		If you're unsure, answer N.
+
 config PM
 	bool "Power Management support"
 	depends on IA64_GENERIC || IA64_DIG || IA64_HP_ZX1

arch/ia64/kernel/Makefile

@@ -18,6 +18,7 @@ obj-$(CONFIG_IOSAPIC)		+= iosapic.o
 obj-$(CONFIG_MODULES)		+= module.o
 obj-$(CONFIG_SMP)		+= smp.o smpboot.o
 obj-$(CONFIG_PERFMON)		+= perfmon_default_smpl.o
+obj-$(CONFIG_IA64_CYCLONE)	+= cyclone.o
 
 # The gate DSO image is built using a special linker script.
 targets += gate.so gate-syms.o

arch/ia64/kernel/acpi.c

@@ -49,6 +49,8 @@
 #include <asm/page.h>
 #include <asm/system.h>
 #include <asm/numa.h>
+#include <asm/sal.h>
+#include <asm/cyclone.h>
 
 
 #define PREFIX			"ACPI: "
@@ -304,6 +306,22 @@ acpi_parse_nmi_src (acpi_table_entry_header *header)
 	return 0;
 }
 
+/* Hook from generic ACPI tables.c */
+void __init acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+	if (!strncmp(oem_id, "IBM", 3) &&
+	    (!strncmp(oem_table_id, "SERMOW", 6))){
+
+		/* Unfortunatly ITC_DRIFT is not yet part of the
+		 * official SAL spec, so the ITC_DRIFT bit is not
+		 * set by the BIOS on this hardware.
+		 */
+		sal_platform_features |= IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT;
+
+		/*Start cyclone clock*/
+		cyclone_setup(0);
+	}
+}
 
 static int __init
 acpi_parse_madt (unsigned long phys_addr, unsigned long size)
@@ -327,6 +345,10 @@ acpi_parse_madt (unsigned long phys_addr, unsigned long size)
 		ipi_base_addr = (unsigned long) ioremap(acpi_madt->lapic_address, 0);
 
 	printk(KERN_INFO PREFIX "Local APIC address 0x%lx\n", ipi_base_addr);
+
+	acpi_madt_oem_check(acpi_madt->header.oem_id,
+		acpi_madt->header.oem_table_id);
+
 	return 0;
 }
 

arch/ia64/kernel/cyclone.c

+#include <linux/smp.h>
+#include <linux/time.h>
+#include <linux/errno.h>
+
+/* IBM Summit (EXA) Cyclone counter code*/
+#define CYCLONE_CBAR_ADDR 0xFEB00CD0
+#define CYCLONE_PMCC_OFFSET 0x51A0
+#define CYCLONE_MPMC_OFFSET 0x51D0
+#define CYCLONE_MPCS_OFFSET 0x51A8
+#define CYCLONE_TIMER_FREQ 100000000
+
+int use_cyclone;
+int __init cyclone_setup(char *str)
+{
+	use_cyclone = 1;
+	return 1;
+}
+
+static u32* volatile cyclone_timer;	/* Cyclone MPMC0 register */
+static u32 last_update_cyclone;
+
+static unsigned long offset_base;
+
+static unsigned long get_offset_cyclone(void)
+{
+	u32 now;
+	unsigned long offset;
+
+	/* Read the cyclone timer */
+	now = readl(cyclone_timer);
+	/* .. relative to previous update*/
+	offset = now - last_update_cyclone;
+
+	/* convert cyclone ticks to nanoseconds */
+	offset = (offset*NSEC_PER_SEC)/CYCLONE_TIMER_FREQ;
+
+	/* our adjusted time in nanoseconds */
+	return offset_base + offset;
+}
+
+static void update_cyclone(long delta_nsec)
+{
+	u32 now;
+	unsigned long offset;
+
+	/* Read the cyclone timer */
+	now = readl(cyclone_timer);
+	/* .. relative to previous update*/
+	offset = now - last_update_cyclone;
+
+	/* convert cyclone ticks to nanoseconds */
+	offset = (offset*NSEC_PER_SEC)/CYCLONE_TIMER_FREQ;
+
+	offset += offset_base;
+
+	/* Be careful about signed/unsigned comparisons here: */
+	if (delta_nsec < 0 || (unsigned long) delta_nsec < offset)
+		offset_base = offset - delta_nsec;
+	else
+		offset_base = 0;
+
+	last_update_cyclone = now;
+}
+
+static void reset_cyclone(void)
+{
+	offset_base = 0;
+	last_update_cyclone = readl(cyclone_timer);
+}
+
+struct time_interpolator cyclone_interpolator = {
+	.get_offset =	get_offset_cyclone,
+	.update =	update_cyclone,
+	.reset =	reset_cyclone,
+	.frequency =	CYCLONE_TIMER_FREQ,
+	.drift =	-100,
+};
+
+int __init init_cyclone_clock(void)
+{
+	u64* reg;
+	u64 base;	/* saved cyclone base address */
+	u64 offset;	/* offset from pageaddr to cyclone_timer register */
+	int i;
+
+	if (!use_cyclone)
+		return -ENODEV;
+
+	printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
+
+	/* find base address */
+	offset = (CYCLONE_CBAR_ADDR);
+	reg = (u64*)ioremap_nocache(offset, sizeof(u64));
+	if(!reg){
+		printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
+		use_cyclone = 0;
+		return -ENODEV;
+	}
+	base = readq(reg);
+	if(!base){
+		printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
+		use_cyclone = 0;
+		return -ENODEV;
+	}
+	iounmap(reg);
+
+	/* setup PMCC */
+	offset = (base + CYCLONE_PMCC_OFFSET);
+	reg = (u64*)ioremap_nocache(offset, sizeof(u64));
+	if(!reg){
+		printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
+		use_cyclone = 0;
+		return -ENODEV;
+	}
+	writel(0x00000001,reg);
+	iounmap(reg);
+
+	/* setup MPCS */
+	offset = (base + CYCLONE_MPCS_OFFSET);
+	reg = (u64*)ioremap_nocache(offset, sizeof(u64));
+	if(!reg){
+		printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
+		use_cyclone = 0;
+		return -ENODEV;
+	}
+	writel(0x00000001,reg);
+	iounmap(reg);
+
+	/* map in cyclone_timer */
+	offset = (base + CYCLONE_MPMC_OFFSET);
+	cyclone_timer = (u32*)ioremap_nocache(offset, sizeof(u32));
+	if(!cyclone_timer){
+		printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
+		use_cyclone = 0;
+		return -ENODEV;
+	}
+
+	/*quick test to make sure its ticking*/
+	for(i=0; i<3; i++){
+		u32 old = readl(cyclone_timer);
+		int stall = 100;
+		while(stall--) barrier();
+		if(readl(cyclone_timer) == old){
+			printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
+			iounmap(cyclone_timer);
+			cyclone_timer = 0;
+			use_cyclone = 0;
+			return -ENODEV;
+		}
+	}
+	/* initialize last tick */
+	last_update_cyclone = readl(cyclone_timer);
+	register_time_interpolator(&cyclone_interpolator);
+
+	return 0;
+}
+
+__initcall(init_cyclone_clock);

arch/ia64/kernel/unwind.c

@@ -1416,7 +1416,7 @@ compile_reg (struct unw_state_record *sr, int i, struct unw_script *script)
 
 	      case UNW_WHERE_FR:
 		if (rval <= 5)
-			val = unw.preg_index[UNW_REG_F2  + (rval -  1)];
+			val = unw.preg_index[UNW_REG_F2  + (rval -  2)];
 		else if (rval >= 16 && rval <= 31)
 			val = unw.preg_index[UNW_REG_F16 + (rval - 16)];
 		else {

arch/ia64/pci/pci.c

@@ -153,8 +153,10 @@ alloc_resource (char *name, struct resource *root, unsigned long start, unsigned
 	res->end = end;
 	res->flags = flags;
 
-	if (insert_resource(root, res))
+	if (insert_resource(root, res))	{
+		kfree(res);
 		return -EBUSY;
+	}
 
 	return 0;
 }

arch/ia64/sn/io/drivers/ioconfig_bus.c

@@ -16,6 +16,7 @@
 
 #include <linux/pci.h>
 
+#include <asm/uaccess.h>
 #include <asm/sn/sgi.h>
 #include <asm/io.h>
 #include <asm/sn/iograph.h>

arch/ia64/sn/io/io.c

@@ -12,7 +12,6 @@
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/driver.h>
-#include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
 #include <asm/sn/xtalk/xwidget.h>

arch/ia64/sn/io/machvec/pci_bus_cvlink.c

@@ -9,7 +9,6 @@
 #include <linux/vmalloc.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/pci/pci_bus_cvlink.h>
 #include <asm/sn/sn_cpuid.h>
 #include <asm/sn/simulator.h>
@@ -28,7 +27,7 @@ vertex_hdl_t devfn_to_vertex(unsigned char busnum, unsigned int devfn);
 
 extern void register_pcibr_intr(int irq, pcibr_intr_t intr);
 
-static void sn_dma_flush_init(unsigned long start,
+static struct sn_flush_device_list *sn_dma_flush_init(unsigned long start,
 				unsigned long end,
 				int idx, int pin, int slot);
 extern int cbrick_type_get_nasid(nasid_t);
@@ -156,6 +155,235 @@ devfn_to_vertex(unsigned char busnum, unsigned int devfn)
 	return(device_vertex);
 }
 
+/*
+ * sn_alloc_pci_sysdata() - This routine allocates a pci controller
+ *	which is expected as the pci_dev and pci_bus sysdata by the Linux
+ *      PCI infrastructure.
+ */
+static struct pci_controller *
+sn_alloc_pci_sysdata(void)
+{
+	struct pci_controller *pci_sysdata;
+
+	pci_sysdata = kmalloc(sizeof(*pci_sysdata), GFP_KERNEL);
+	if (!pci_sysdata)
+		return NULL;
+
+	memset(pci_sysdata, 0, sizeof(*pci_sysdata));
+	return pci_sysdata;
+}
+
+/*
+ * sn_pci_fixup_bus() - This routine sets up a bus's resources
+ * consistent with the Linux PCI abstraction layer.
+ */
+static int __init
+sn_pci_fixup_bus(struct pci_bus *bus)
+{
+	struct pci_controller *pci_sysdata;
+	struct sn_widget_sysdata *widget_sysdata;
+
+	pci_sysdata = sn_alloc_pci_sysdata();
+	if  (!pci_sysdata) {
+		printk(KERN_WARNING "sn_pci_fixup_bus(): Unable to "
+			       "allocate memory for pci_sysdata\n");
+		return -ENOMEM;
+	}
+	widget_sysdata = kmalloc(sizeof(struct sn_widget_sysdata),
+				 GFP_KERNEL);
+	if (!widget_sysdata) {
+		printk(KERN_WARNING "sn_pci_fixup_bus(): Unable to "
+			       "allocate memory for widget_sysdata\n");
+		kfree(pci_sysdata);
+		return -ENOMEM;
+	}
+
+	widget_sysdata->vhdl = pci_bus_to_vertex(bus->number);
+	pci_sysdata->platform_data = (void *)widget_sysdata;
+	bus->sysdata = pci_sysdata;
+	return 0;
+}
+
+
+/*
+ * sn_pci_fixup_slot() - This routine sets up a slot's resources
+ * consistent with the Linux PCI abstraction layer.  Resources acquired
+ * from our PCI provider include PIO maps to BAR space and interrupt
+ * objects.
+ */
+static int
+sn_pci_fixup_slot(struct pci_dev *dev)
+{
+	extern int bit_pos_to_irq(int);
+	unsigned int irq;
+	int idx;
+	u16 cmd;
+	vertex_hdl_t vhdl;
+	unsigned long size;
+	struct pci_controller *pci_sysdata;
+	struct sn_device_sysdata *device_sysdata;
+	pciio_intr_line_t lines = 0;
+	vertex_hdl_t device_vertex;
+	pciio_provider_t *pci_provider;
+	pciio_intr_t intr_handle;
+
+	/* Allocate a controller structure */
+	pci_sysdata = sn_alloc_pci_sysdata();
+	if (!pci_sysdata) {
+		printk(KERN_WARNING "sn_pci_fixup_slot: Unable to "
+			       "allocate memory for pci_sysdata\n");
+		return -ENOMEM;
+	}
+
+	/* Set the device vertex */
+	device_sysdata = kmalloc(sizeof(struct sn_device_sysdata), GFP_KERNEL);
+	if (!device_sysdata) {
+		printk(KERN_WARNING "sn_pci_fixup_slot: Unable to "
+			       "allocate memory for device_sysdata\n");
+		kfree(pci_sysdata);
+		return -ENOMEM;
+	}
+
+	device_sysdata->vhdl = devfn_to_vertex(dev->bus->number, dev->devfn);
+	pci_sysdata->platform_data = (void *) device_sysdata;
+	dev->sysdata = pci_sysdata;
+	set_pci_provider(device_sysdata);
+
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+
+	/*
+	 * Set the resources address correctly.  The assumption here
+	 * is that the addresses in the resource structure has been
+	 * read from the card and it was set in the card by our
+	 * Infrastructure.  NOTE: PIC and TIOCP don't have big-window
+	 * upport for PCI I/O space.  So by mapping the I/O space
+	 * first we will attempt to use Device(x) registers for I/O
+	 * BARs (which can't use big windows like MEM BARs can).
+	 */
+	vhdl = device_sysdata->vhdl;
+
+	/* Allocate the IORESOURCE_IO space first */
+	for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
+		unsigned long start, end, addr;
+
+		device_sysdata->pio_map[idx] = NULL;
+
+		if (!(dev->resource[idx].flags & IORESOURCE_IO))
+			continue;
+
+		start = dev->resource[idx].start;
+		end = dev->resource[idx].end;
+		size = end - start;
+		if (!size)
+			continue;
+
+		addr = (unsigned long)pciio_pio_addr(vhdl, 0,
+		PCIIO_SPACE_WIN(idx), 0, size,
+				&device_sysdata->pio_map[idx], 0);
+
+		if (!addr) {
+			dev->resource[idx].start = 0;
+			dev->resource[idx].end = 0;
+			printk("sn_pci_fixup(): pio map failure for "
+				"%s bar%d\n", dev->slot_name, idx);
+		} else {
+			addr |= __IA64_UNCACHED_OFFSET;
+			dev->resource[idx].start = addr;
+			dev->resource[idx].end = addr + size;
+		}
+
+		if (dev->resource[idx].flags & IORESOURCE_IO)
+			cmd |= PCI_COMMAND_IO;
+	}
+
+	/* Allocate the IORESOURCE_MEM space next */
+	for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
+		unsigned long start, end, addr;
+
+		if ((dev->resource[idx].flags & IORESOURCE_IO))
+			continue;
+
+		start = dev->resource[idx].start;
+		end = dev->resource[idx].end;
+		size = end - start;
+		if (!size)
+			continue;
+
+		addr = (unsigned long)pciio_pio_addr(vhdl, 0,
+		PCIIO_SPACE_WIN(idx), 0, size,
+				&device_sysdata->pio_map[idx], 0);
+
+		if (!addr) {
+			dev->resource[idx].start = 0;
+			dev->resource[idx].end = 0;
+			printk("sn_pci_fixup(): pio map failure for "
+				"%s bar%d\n", dev->slot_name, idx);
+		} else {
+			addr |= __IA64_UNCACHED_OFFSET;
+			dev->resource[idx].start = addr;
+			dev->resource[idx].end = addr + size;
+		}
+
+		if (dev->resource[idx].flags & IORESOURCE_MEM)
+			cmd |= PCI_COMMAND_MEMORY;
+	}
+
+	/*
+	 * Update the Command Word on the Card.
+	 */
+	cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */
+				   /* bit gets dropped .. no harm */
+	pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
+	device_vertex = device_sysdata->vhdl;
+	pci_provider = device_sysdata->pci_provider;
+	device_sysdata->intr_handle = NULL;
+
+	if (!lines)
+		return 0;
+
+	irqpdaindr->curr = dev;
+
+	intr_handle = (pci_provider->intr_alloc)(device_vertex, NULL, lines, device_vertex);
+	if (intr_handle == NULL) {
+		printk(KERN_WARNING "sn_pci_fixup:  pcibr_intr_alloc() failed\n");
+		kfree(pci_sysdata);
+		kfree(device_sysdata);
+		return -ENOMEM;
+	}
+
+	device_sysdata->intr_handle = intr_handle;
+	irq = intr_handle->pi_irq;
+	irqpdaindr->device_dev[irq] = dev;
+	(pci_provider->intr_connect)(intr_handle, (intr_func_t)0, (intr_arg_t)0);
+	dev->irq = irq;
+
+	register_pcibr_intr(irq, (pcibr_intr_t)intr_handle);
+
+	for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
+		int ibits = ((pcibr_intr_t)intr_handle)->bi_ibits;
+		int i;
+
+		size = dev->resource[idx].end -
+			dev->resource[idx].start;
+		if (size == 0) continue;
+
+		for (i=0; i<8; i++) {
+			if (ibits & (1 << i) ) {
+				extern pcibr_info_t pcibr_info_get(vertex_hdl_t);
+				device_sysdata->dma_flush_list =
+				 sn_dma_flush_init(dev->resource[idx].start,
+						   dev->resource[idx].end,
+						   idx,
+						   i,
+						   PCIBR_INFO_SLOT_GET_EXT(pcibr_info_get(device_sysdata->vhdl)));
+			}
+		}
+	}
+	return 0;
+}
+
 struct sn_flush_nasid_entry flush_nasid_list[MAX_NASIDS];
 
 /* Initialize the data structures for flushing write buffers after a PIO read.
@@ -165,7 +393,7 @@ struct sn_flush_nasid_entry flush_nasid_list[MAX_NASIDS];
  * on the in use pin.  This will prevent the race condition between PIO read responses and
  * DMA writes.
  */
-static void
+static struct sn_flush_device_list *
 sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int slot)
 {
 	nasid_t nasid;
@@ -187,7 +415,7 @@ sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int
 			sizeof(struct sn_flush_device_list *), GFP_KERNEL);
 		if (!flush_nasid_list[nasid].widget_p) {
 			printk(KERN_WARNING "sn_dma_flush_init: Cannot allocate memory for nasid list\n");
-			return;
+			return NULL;
 		}
 		memset(flush_nasid_list[nasid].widget_p, 0, (HUB_WIDGET_ID_MAX+1) * sizeof(struct sn_flush_device_list *));
 	}
@@ -197,8 +425,8 @@ sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int
 
 		itte = HUB_L(IIO_ITTE_GET(nasid, itte_index));
 		flush_nasid_list[nasid].iio_itte[bwin] = itte;
-		wid_num = (itte >> IIO_ITTE_WIDGET_SHIFT) & 
-			  IIO_ITTE_WIDGET_MASK;
+		wid_num = (itte >> IIO_ITTE_WIDGET_SHIFT)
+				& IIO_ITTE_WIDGET_MASK;
 		bus = itte & IIO_ITTE_OFFSET_MASK;
 		if (bus == 0x4 || bus == 0x8) {
 			bus = 0;
@@ -211,14 +439,14 @@ sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int
 	 * because these are the IOC4 slots and we don't flush them.
 	 */
 	if (isIO9(nasid) && bus == 0 && (slot == 1 || slot == 4)) {
-		return;
+		return NULL;
 	}
 	if (flush_nasid_list[nasid].widget_p[wid_num] == NULL) {
 		flush_nasid_list[nasid].widget_p[wid_num] = (struct sn_flush_device_list *)kmalloc(
 			DEV_PER_WIDGET * sizeof (struct sn_flush_device_list), GFP_KERNEL);
 		if (!flush_nasid_list[nasid].widget_p[wid_num]) {
 			printk(KERN_WARNING "sn_dma_flush_init: Cannot allocate memory for nasid sub-list\n");
-			return;
+			return NULL;
 		}
 		memset(flush_nasid_list[nasid].widget_p[wid_num], 0,
 			DEV_PER_WIDGET * sizeof (struct sn_flush_device_list));
@@ -303,233 +531,7 @@ sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int
 				((virt_to_phys(&p->flush_addr) & 0xfffffffff) |
 				(dnasid << 36) | (0xfUL << 48)));
 	}
-}
-
-/*
- * sn_pci_fixup() - This routine is called when platform_pci_fixup() is 
- *	invoked at the end of pcibios_init() to link the Linux pci 
- *	infrastructure to SGI IO Infrasturcture - ia64/kernel/pci.c
- *
- *	Other platform specific fixup can also be done here.
- */
-static void __init
-sn_pci_fixup(int arg)
-{
-	struct list_head *ln;
-	struct pci_bus *pci_bus = NULL;
-	struct pci_dev *device_dev = NULL;
-	struct sn_widget_sysdata *widget_sysdata;
-	struct sn_device_sysdata *device_sysdata;
-	pcibr_intr_t intr_handle;
-	pciio_provider_t *pci_provider;
-	vertex_hdl_t device_vertex;
-	pciio_intr_line_t lines = 0;
-	extern int numnodes;
-	int cnode;
-
-	if (arg == 0) {
-#ifdef CONFIG_PROC_FS
-		extern void register_sn_procfs(void);
-#endif
-		extern void sgi_master_io_infr_init(void);
-		extern void sn_init_cpei_timer(void);
-		
-		sgi_master_io_infr_init();
-		
-		for (cnode = 0; cnode < numnodes; cnode++) {
-			extern void intr_init_vecblk(cnodeid_t);
-			intr_init_vecblk(cnode);
-		} 
-
-		sn_init_cpei_timer();
-
-#ifdef CONFIG_PROC_FS
-		register_sn_procfs();
-#endif
-		return;
-	}
-
-
-	done_probing = 1;
-
-	/*
-	 * Initialize the pci bus vertex in the pci_bus struct.
-	 */
-	for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
-		pci_bus = pci_bus_b(ln);
-		widget_sysdata = kmalloc(sizeof(struct sn_widget_sysdata), 
-					GFP_KERNEL);
-		if (!widget_sysdata) {
-			printk(KERN_WARNING "sn_pci_fixup(): Unable to "
-			       "allocate memory for widget_sysdata\n");
-			return;
-		}			
-		widget_sysdata->vhdl = pci_bus_to_vertex(pci_bus->number);
-		pci_bus->sysdata = (void *)widget_sysdata;
-	}
-
-	/*
- 	 * set the root start and end so that drivers calling check_region()
-	 * won't see a conflict
-	 */
-
-#ifdef CONFIG_IA64_SGI_SN_SIM
-	if (! IS_RUNNING_ON_SIMULATOR()) {
-		ioport_resource.start  = 0xc000000000000000;
-		ioport_resource.end =    0xcfffffffffffffff;
-	}
-#endif
-
-	/*
-	 * Set the root start and end for Mem Resource.
-	 */
-	iomem_resource.start = 0;
-	iomem_resource.end = 0xffffffffffffffff;
-
-	/*
-	 * Initialize the device vertex in the pci_dev struct.
-	 */
-	while ((device_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, device_dev)) != NULL) {
-		unsigned int irq;
-		int idx;
-		u16 cmd;
-		vertex_hdl_t vhdl;
-		unsigned long size;
-		extern int bit_pos_to_irq(int);
-
-		/* Set the device vertex */
-
-		device_sysdata = kmalloc(sizeof(struct sn_device_sysdata),
-					 GFP_KERNEL);
-		if (!device_sysdata) {
-			printk(KERN_WARNING "sn_pci_fixup: Cannot allocate memory for device sysdata\n");
-			return;
-		}
-
-		device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn);
-		device_dev->sysdata = (void *) device_sysdata;
-		set_pci_provider(device_sysdata);
-
-		pci_read_config_word(device_dev, PCI_COMMAND, &cmd);
-
-		/*
-		 * Set the resources address correctly.  The assumption here 
-		 * is that the addresses in the resource structure has been
-		 * read from the card and it was set in the card by our
-		 * Infrastructure ..
-		 */
-		vhdl = device_sysdata->vhdl;
-		/* Allocate the IORESOURCE_IO space first */
-		for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
-			unsigned long start, end, addr;
-
-			if (!(device_dev->resource[idx].flags & IORESOURCE_IO))
-				continue; 
-			
-			start = device_dev->resource[idx].start;
-			end = device_dev->resource[idx].end;
-			size = end - start;
-			if (!size)
-				continue; 
-			
-			addr = (unsigned long)pciio_pio_addr(vhdl, 0, 
-					PCIIO_SPACE_WIN(idx), 0, size, 0, 0);
-			if (!addr) {
-				device_dev->resource[idx].start = 0;
-				device_dev->resource[idx].end = 0;
-				printk("sn_pci_fixup(): pio map failure for "
-				    "%s bar%d\n", device_dev->slot_name, idx);
-			} else {
-				addr |= __IA64_UNCACHED_OFFSET;
-				device_dev->resource[idx].start = addr;
-				device_dev->resource[idx].end = addr + size;
-			}	
-
-			if (device_dev->resource[idx].flags & IORESOURCE_IO) 
-				cmd |= PCI_COMMAND_IO; 
-		} 
-
-		/* Allocate the IORESOURCE_MEM space next */
-		for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
-			unsigned long start, end, addr;
-
-			if ((device_dev->resource[idx].flags & IORESOURCE_IO))
-				continue; 
-
-			start = device_dev->resource[idx].start;
-			end = device_dev->resource[idx].end;
-			size = end - start;
-			if (!size)
-				continue; 
-
-			addr = (unsigned long)pciio_pio_addr(vhdl, 0, 
-					PCIIO_SPACE_WIN(idx), 0, size, 0, 0);
-			if (!addr) {
-				device_dev->resource[idx].start = 0;
-				device_dev->resource[idx].end = 0;
-				printk("sn_pci_fixup(): pio map failure for "
-				    "%s bar%d\n", device_dev->slot_name, idx);
-			} else {
-				addr |= __IA64_UNCACHED_OFFSET;
-				device_dev->resource[idx].start = addr;
-				device_dev->resource[idx].end = addr + size;
-			}	
-
-			if (device_dev->resource[idx].flags & IORESOURCE_MEM)
-				cmd |= PCI_COMMAND_MEMORY;
-		}
-
-		/*
-		 * Update the Command Word on the Card.
-		 */
-		cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */
-					   /* bit gets dropped .. no harm */
-		pci_write_config_word(device_dev, PCI_COMMAND, cmd);
-
-		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN,
-				     (unsigned char *)&lines);
-		device_sysdata = (struct sn_device_sysdata *)device_dev->sysdata;
-		device_vertex = device_sysdata->vhdl;
-		pci_provider = device_sysdata->pci_provider;
- 
-		if (!lines) {
-			continue;
-		}
-
-		irqpdaindr->curr = device_dev;
-		intr_handle = (pci_provider->intr_alloc)(device_vertex, NULL, lines, device_vertex);
-
-		if (intr_handle == NULL) {
-			printk("sn_pci_fixup:  pcibr_intr_alloc() failed\n");
-			continue;
-		}
-		irq = intr_handle->bi_irq;
-		irqpdaindr->device_dev[irq] = device_dev;
-		(pci_provider->intr_connect)(intr_handle, (intr_func_t)0, (intr_arg_t)0);
-		device_dev->irq = irq;
-		register_pcibr_intr(irq, (pcibr_intr_t)intr_handle);
-
-		for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
-			int ibits = intr_handle->bi_ibits;
-			int i;
-
-			size = device_dev->resource[idx].end -
-				device_dev->resource[idx].start;
-			if (size == 0)
-				continue;
-
-			for (i=0; i<8; i++) {
-				if (ibits & (1 << i) ) {
-					sn_dma_flush_init(device_dev->resource[idx].start, 
-						device_dev->resource[idx].end,
-						idx,
-						i,
-						PCIBR_INFO_SLOT_GET_EXT(pcibr_info_get(device_sysdata->vhdl)));
-				}
-			}
-		}
-
-	}
+	return p;
 }
 
 /*
@@ -702,13 +704,26 @@ pci_bus_to_hcl_cvlink(void)
 /*
  * Ugly hack to get PCI setup until we have a proper ACPI namespace.
  */
+
+#define PCI_BUSES_TO_SCAN 256
+
 extern struct pci_ops sn_pci_ops;
 int __init
 sn_pci_init (void)
 {
-#	define PCI_BUSES_TO_SCAN 256
 	int i = 0;
 	struct pci_controller *controller;
+	struct list_head *ln;
+	struct pci_bus *pci_bus = NULL;
+	struct pci_dev *pci_dev = NULL;
+	extern int numnodes;
+	int cnode, ret;
+#ifdef CONFIG_PROC_FS
+	extern void register_sn_procfs(void);
+#endif
+	extern void sgi_master_io_infr_init(void);
+	extern void sn_init_cpei_timer(void);
+
 
 	if (!ia64_platform_is("sn2") || IS_RUNNING_ON_SIMULATOR())
 		return 0;
@@ -721,7 +736,19 @@ sn_pci_init (void)
 	/*
 	 * set pci_raw_ops, etc.
 	 */
-	sn_pci_fixup(0);
+
+	sgi_master_io_infr_init();
+
+	for (cnode = 0; cnode < numnodes; cnode++) {
+		extern void intr_init_vecblk(cnodeid_t);
+		intr_init_vecblk(cnode);
+	}
+
+	sn_init_cpei_timer();
+
+#ifdef CONFIG_PROC_FS
+	register_sn_procfs();
+#endif
 
 	controller = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
 	if (controller) {
@@ -734,7 +761,53 @@ sn_pci_init (void)
 	/*
 	 * actually find devices and fill in hwgraph structs
 	 */
-	sn_pci_fixup(1);
+
+	done_probing = 1;
+
+	/*
+	 * Initialize the pci bus vertex in the pci_bus struct.
+	 */
+	for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
+		pci_bus = pci_bus_b(ln);
+		ret = sn_pci_fixup_bus(pci_bus);
+		if ( ret ) {
+			printk(KERN_WARNING
+				"sn_pci_fixup: sn_pci_fixup_bus fails : error %d\n",
+					ret);
+			return;
+		}
+	}
+
+	/*
+	 * set the root start and end so that drivers calling check_region()
+	 * won't see a conflict
+	 */
+
+#ifdef CONFIG_IA64_SGI_SN_SIM
+	if (! IS_RUNNING_ON_SIMULATOR()) {
+		ioport_resource.start  = 0xc000000000000000;
+		ioport_resource.end =    0xcfffffffffffffff;
+	}
+#endif
+
+	/*
+	 * Set the root start and end for Mem Resource.
+	 */
+	iomem_resource.start = 0;
+	iomem_resource.end = 0xffffffffffffffff;
+
+	/*
+	 * Initialize the device vertex in the pci_dev struct.
+	 */
+	while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
+		ret = sn_pci_fixup_slot(pci_dev);
+		if ( ret ) {
+			printk(KERN_WARNING
+				"sn_pci_fixup: sn_pci_fixup_slot fails : error %d\n",
+					ret);
+			return;
+		}
+	}
 
 	return 0;
 }

arch/ia64/sn/io/machvec/pci_dma.c

@@ -127,7 +127,7 @@ sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_hand
 	/*
 	 * Get hwgraph vertex for the device
 	 */
-	device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
+	device_sysdata = SN_DEVICE_SYSDATA(hwdev);
 	vhdl = device_sysdata->vhdl;
 
 	/*
@@ -240,7 +240,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
 	/*
 	 * Get the hwgraph vertex for the device
 	 */
-	device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
+	device_sysdata = SN_DEVICE_SYSDATA(hwdev);
 	vhdl = device_sysdata->vhdl;
 
 	/*
@@ -367,7 +367,7 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 	/*
 	 * find vertex for the device
 	 */
-	device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata;
+	device_sysdata = SN_DEVICE_SYSDATA(hwdev);
 	vhdl = device_sysdata->vhdl;
 
 	/*

arch/ia64/sn/io/sn2/bte_error.c

@@ -12,7 +12,6 @@
 #include <asm/smp.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/io.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/sn_private.h>

arch/ia64/sn/io/sn2/geo_op.c

@@ -27,7 +27,6 @@
 #include <asm/hw_irq.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/io.h>

arch/ia64/sn/io/sn2/klconflib.c

@@ -474,8 +474,6 @@ board_serial_number_get(lboard_t *board,char *serial_number)
 	return(0);
 }
 
-#include "asm/sn/sn_private.h"
-
 /*
  * Format a module id for printing.
  *

arch/ia64/sn/io/sn2/ml_SN_init.c

@@ -11,12 +11,12 @@
 #include <linux/bootmem.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/io.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/sn_private.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/sn_cpuid.h>
+#include <asm/sn/simulator.h>
 
 int		maxcpus;
 
@@ -69,12 +69,15 @@ void init_platform_nodepda(nodepda_t *npda, cnodeid_t node)
 }
 
 void
-init_platform_hubinfo(nodepda_t **nodepdaindr) {
+init_platform_hubinfo(nodepda_t **nodepdaindr)
+{
 	cnodeid_t       cnode;
 	hubinfo_t hubinfo;
 	nodepda_t *npda;
 	extern int numionodes;
 
+	if (IS_RUNNING_ON_SIMULATOR())
+		return;
 	for (cnode = 0; cnode < numionodes; cnode++) {
 		npda = nodepdaindr[cnode];
 		hubinfo = (hubinfo_t)npda->pdinfo;

arch/ia64/sn/io/sn2/ml_SN_intr.c

@@ -30,6 +30,7 @@
 #include <asm/sal.h>
 #include <asm/sn/sn_sal.h>
 #include <asm/sn/sn2/shub_mmr.h>
+#include <asm/sn/pda.h>
 
 extern irqpda_t	*irqpdaindr;
 extern cnodeid_t master_node_get(vertex_hdl_t vhdl);
@@ -216,7 +217,6 @@ static cpuid_t intr_cpu_choose_from_node(cnodeid_t cnode)
 {
 	cpuid_t		cpu, best_cpu = CPU_NONE;
 	int		slice, min_count = 1000;
-	irqpda_t	*irqs;
 
 	for (slice = CPUS_PER_NODE - 1; slice >= 0; slice--) {
 		int intrs;
@@ -227,8 +227,7 @@ static cpuid_t intr_cpu_choose_from_node(cnodeid_t cnode)
 		if (!cpu_online(cpu))
 			continue;
 
-		irqs = irqpdaindr;
-		intrs = irqs->num_irq_used;
+		intrs = pdacpu(cpu)->sn_num_irqs;
 
 		if (min_count > intrs) {
 			min_count = intrs;
@@ -243,6 +242,7 @@ static cpuid_t intr_cpu_choose_from_node(cnodeid_t cnode)
 			}
 		}
 	}
+	pdacpu(best_cpu)->sn_num_irqs++;
 	return best_cpu;
 }
 

arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c

@@ -8,7 +8,6 @@
 
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>

arch/ia64/sn/io/sn2/pcibr/pcibr_config.c

@@ -8,7 +8,6 @@
 
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>

arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c

@@ -10,7 +10,6 @@
 #include <linux/module.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/arch.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>

arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c

@@ -8,7 +8,6 @@
 
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>

arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c

@@ -8,7 +8,6 @@
 
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>

arch/ia64/sn/io/sn2/pic.c

@@ -90,10 +90,15 @@ pic_bus1_widget_info_dup(vertex_hdl_t conn_v, vertex_hdl_t peer_conn_v,
     		peer_widget_info->w_efunc = 0;
     		peer_widget_info->w_einfo = 0;
 		peer_widget_info->w_name = kmalloc(strlen(peer_path) + 1, GFP_KERNEL);
+		if (!peer_widget_info->w_name) {
+			kfree(peer_widget_info);
+			return -ENOMEM;
+		}
 		strcpy(peer_widget_info->w_name, peer_path);
 
 		if (hwgraph_info_add_LBL(peer_conn_v, INFO_LBL_XWIDGET,
 			(arbitrary_info_t)peer_widget_info) != GRAPH_SUCCESS) {
+			kfree(peer_widget_info->w_name);
 				kfree(peer_widget_info);
 				return 0;
 		}
@@ -359,6 +364,9 @@ pic_attach2(vertex_hdl_t xconn_vhdl, void *bridge,
 
     s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
     pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
+    if (!pcibr_soft->bs_name)
+	    return -ENOMEM;
+
     strcpy(pcibr_soft->bs_name, s);
 
     pcibr_soft->bs_conn = xconn_vhdl;

arch/ia64/sn/io/sn2/shub.c

@@ -17,7 +17,6 @@
 #include <asm/system.h>
 #include <asm/sn/sgi.h>
 #include <asm/uaccess.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/io.h>

arch/ia64/sn/io/sn2/shub_intr.c

@@ -11,7 +11,6 @@
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/driver.h>
-#include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
 #include <asm/sn/xtalk/xwidget.h>

arch/ia64/sn/io/sn2/shuberror.c

@@ -16,7 +16,6 @@
 #include <asm/delay.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/io.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/sn_private.h>

arch/ia64/sn/io/xswitch.c

@@ -11,7 +11,6 @@
 #include <asm/errno.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/driver.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/xtalk/xtalk.h>

arch/ia64/sn/kernel/irq.c

@@ -18,7 +18,6 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/types.h>
 #include <asm/sn/pci/pciio.h>

arch/ia64/sn/kernel/setup.c

@@ -85,6 +85,7 @@ int	numionodes;
 u64 master_node_bedrock_address;
 
 static void sn_init_pdas(char **);
+static void scan_for_ionodes(void);
 
 
 static nodepda_t	*nodepdaindr[MAX_COMPACT_NODES];
@@ -131,7 +132,7 @@ char drive_info[4*16];
  * may not be initialized yet.
  */
 
-static int
+static int __init
 pxm_to_nasid(int pxm)
 {
 	int i;
@@ -358,11 +359,10 @@ sn_setup(char **cmdline_p)
  *
  * One time setup for Node Data Area.  Called by sn_setup().
  */
-void
+void __init
 sn_init_pdas(char **cmdline_p)
 {
 	cnodeid_t	cnode;
-	void scan_for_ionodes(void);
 
 	/*
 	 * Make sure that the PDA fits entirely in the same page as the 
@@ -498,7 +498,7 @@ sn_cpu_init(void)
  * physical_node_map and the pda and increment numionodes.
  */
 
-void
+static void __init
 scan_for_ionodes(void)
 {
 	int nasid = 0;

include/asm-ia64/cyclone.h

+#ifndef ASM_IA64_CYCLONE_H
+#define ASM_IA64_CYCLONE_H
+
+#ifdef	CONFIG_IA64_CYCLONE
+extern int use_cyclone;
+extern int __init cyclone_setup(char*);
+#else	/* CONFIG_IA64_CYCLONE */
+#define use_cyclone 0
+static inline void cyclone_setup(char* s)
+{
+	printk(KERN_ERR "Cyclone Counter: System not configured"
+					" w/ CONFIG_IA64_CYCLONE.\n");
+}
+#endif	/* CONFIG_IA64_CYCLONE */
+#endif	/* !ASM_IA64_CYCLONE_H */

include/asm-ia64/pci.h

@@ -97,6 +97,8 @@ struct pci_controller {
 
 	unsigned int windows;
 	struct pci_window *window;
+
+	void *platform_data;
 };
 
 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)

include/asm-ia64/sn/clksupport.h

@@ -24,17 +24,16 @@
 #define _ASM_IA64_SN_CLKSUPPORT_H
 
 #include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn2/addrs.h>
+#include <asm/sn/sn2/shubio.h>
+#include <asm/sn/sn2/shub_mmr.h>
 
 typedef long clkreg_t;
 
 extern unsigned long sn_rtc_cycles_per_second;
 extern unsigned long sn_rtc_per_itc;
 
-
-#include <asm/sn/addrs.h>
-#include <asm/sn/sn2/addrs.h>
-#include <asm/sn/sn2/shubio.h>
-#include <asm/sn/sn2/shub_mmr.h>
 #define RTC_MASK		SH_RTC_MASK
 #define RTC_COUNTER_ADDR	((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
 #define RTC_COMPARE_A_ADDR      ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))

include/asm-ia64/sn/dmamap.h

@@ -8,12 +8,6 @@
 #ifndef _ASM_IA64_SN_DMAMAP_H
 #define _ASM_IA64_SN_DMAMAP_H
 
-#include <asm/sn/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 /*
  * Definitions for allocating, freeing, and using DMA maps
  */
@@ -43,10 +37,6 @@ typedef struct dmamap {
 	unsigned long	dma_virtaddr;	/* Beginning virtual address that is mapped */
 } dmamap_t;
 
-#ifdef __cplusplus
-}
-#endif
-
 /* standard flags values for pio_map routines,
  * including {xtalk,pciio}_dmamap calls.
  * NOTE: try to keep these in step with PIOMAP flags.

include/asm-ia64/sn/driver.h

@@ -23,10 +23,6 @@ typedef struct device_driver_s *device_driver_t;
 /* == Driver thread priority support == */
 typedef int ilvl_t;
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 struct eframe_s;
 struct piomap;
 struct dmamap;

include/asm-ia64/sn/intr.h

@@ -8,7 +8,6 @@
 #ifndef _ASM_IA64_SN_INTR_H
 #define _ASM_IA64_SN_INTR_H
 
-#include <linux/config.h>
 #include <asm/sn/sn2/intr.h>
 
 extern void sn_send_IPI_phys(long, int, int);

include/asm-ia64/sn/io.h

@@ -9,8 +9,6 @@
 #ifndef _ASM_IA64_SN_IO_H
 #define _ASM_IA64_SN_IO_H
 
-#include <linux/config.h>
-
 #include <asm/sn/addrs.h>
 
 /* Because we only have PCI I/O ports.  */

include/asm-ia64/sn/ioc4.h

@@ -9,682 +9,6 @@
 #ifndef _ASM_IA64_SN_IOC4_H
 #define _ASM_IA64_SN_IOC4_H
 
-#if 0
-
-/*
- * ioc4.h - IOC4 chip header file
- */
-
-/* Notes:
- * The IOC4 chip is a 32-bit PCI device that provides 4 serial ports,
- * an IDE bus interface, a PC keyboard/mouse interface, and a real-time
- * external interrupt interface.
- *
- * It includes an optimized DMA buffer management, and a store-and-forward
- * buffer RAM.
- *
- * All IOC4 registers are 32 bits wide.
- */
-typedef __uint32_t ioc4reg_t;
-
-/*
- * PCI Configuration Space Register Address Map, use offset from IOC4 PCI
- * configuration base such that this can be used for multiple IOC4s
- */
-#define IOC4_PCI_ID		0x0	/* ID */
-
-#define IOC4_VENDOR_ID_NUM	0x10A9
-#define IOC4_DEVICE_ID_NUM	0x100A 
-#define IOC4_ADDRSPACE_MASK	0xfff00000ULL
-
-#define IOC4_PCI_SCR		0x4 /* Status/Command */
-#define IOC4_PCI_REV		0x8 /* Revision */
-#define IOC4_PCI_LAT		0xC /* Latency Timer */
-#define IOC4_PCI_BAR0		0x10 /* IOC4 base address 0 */
-#define IOC4_PCI_SIDV		0x2c /* Subsys ID and vendor */
-#define IOC4_PCI_CAP 		0x34 /* Capability pointer */
-#define IOC4_PCI_LATGNTINT      0x3c /* Max_lat, min_gnt, int_pin, int_line */
-
-/*
- * PCI Memory Space Map 
- */
-#define IOC4_PCI_ERR_ADDR_L     0x000	/* Low Error Address */
-#define IOC4_PCI_ERR_ADDR_VLD	     (0x1 << 0)
-#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
-#define IOC4_PCI_ERR_ADDR_MUL_ERR    (0x1 << 5)
-#define IOC4_PCI_ERR_ADDR_ADDR_MSK   (0x3ffffff << 6)
-
-/* Master IDs contained in PCI_ERR_ADDR_MST_ID_MSK */
-#define IOC4_MST_ID_S0_TX		0
-#define IOC4_MST_ID_S0_RX		1
-#define IOC4_MST_ID_S1_TX		2
-#define IOC4_MST_ID_S1_RX		3
-#define IOC4_MST_ID_S2_TX		4
-#define IOC4_MST_ID_S2_RX		5
-#define IOC4_MST_ID_S3_TX		6
-#define IOC4_MST_ID_S3_RX		7
-#define IOC4_MST_ID_ATA 		8
-
-#define IOC4_PCI_ERR_ADDR_H	0x004	/* High Error Address */
-
-#define IOC4_SIO_IR	        0x008	/* SIO Interrupt Register */
-#define IOC4_OTHER_IR	        0x00C	/* Other Interrupt Register */
-
-/* These registers are read-only for general kernel code. To modify
- * them use the functions in ioc4.c
- */
-#define IOC4_SIO_IES_RO         0x010	/* SIO Interrupt Enable Set Reg */
-#define IOC4_OTHER_IES_RO       0x014	/* Other Interrupt Enable Set Reg */
-#define IOC4_SIO_IEC_RO         0x018	/* SIO Interrupt Enable Clear Reg */
-#define IOC4_OTHER_IEC_RO       0x01C	/* Other Interrupt Enable Clear Reg */
-
-#define IOC4_SIO_CR	        0x020	/* SIO Control Reg */
-#define IOC4_INT_OUT	        0x028	/* INT_OUT Reg (realtime interrupt) */
-#define IOC4_GPCR_S	        0x030	/* GenericPIO Cntrl Set Register */
-#define IOC4_GPCR_C	        0x034	/* GenericPIO Cntrl Clear Register */
-#define IOC4_GPDR	        0x038	/* GenericPIO Data Register */
-#define IOC4_GPPR_0	        0x040	/* GenericPIO Pin Registers */
-#define IOC4_GPPR_OFF	        0x4
-#define IOC4_GPPR(x)	        (IOC4_GPPR_0+(x)*IOC4_GPPR_OFF)
-
-/* ATAPI Registers */
-#define IOC4_ATA_0              0x100	/* Data w/timing */
-#define IOC4_ATA_1              0x104	/* Error/Features w/timing */
-#define IOC4_ATA_2              0x108	/* Sector Count w/timing */
-#define IOC4_ATA_3              0x10C	/* Sector Number w/timing */
-#define IOC4_ATA_4              0x110   /* Cyliner Low w/timing */
-#define IOC4_ATA_5              0x114	/* Cylinder High w/timing */
-#define IOC4_ATA_6              0x118	/* Device/Head w/timing */
-#define IOC4_ATA_7              0x11C	/* Status/Command w/timing */
-#define IOC4_ATA_0_AUX          0x120	/* Aux Status/Device Cntrl w/timing */
-#define IOC4_ATA_TIMING       	0x140	/* Timing value register 0 */
-#define IOC4_ATA_DMA_PTR_L      0x144   /* Low Memory Pointer to DMA List */
-#define IOC4_ATA_DMA_PTR_H      0x148   /* High Memory Pointer to DMA List */
-#define IOC4_ATA_DMA_ADDR_L     0x14C   /* Low Memory DMA Address */
-#define IOC4_ATA_DMA_ADDR_H     0x150   /* High Memory DMA Addresss */
-#define IOC4_ATA_BC_DEV         0x154	/* DMA Byte Count at Device */
-#define IOC4_ATA_BC_MEM         0x158	/* DMA Byte Count at Memory */
-#define IOC4_ATA_DMA_CTRL       0x15C	/* DMA Control/Status */
-
-/* Keyboard and Mouse Registers */
-#define IOC4_KM_CSR	        0x200	/* Kbd and Mouse Cntrl/Status Reg */
-#define IOC4_K_RD	        0x204	/* Kbd Read Data Register */
-#define IOC4_M_RD	        0x208	/* Mouse Read Data Register */
-#define IOC4_K_WD	        0x20C	/* Kbd Write Data Register */
-#define IOC4_M_WD	        0x210	/* Mouse Write Data Register */
-
-/* Serial Port Registers used for DMA mode serial I/O */
-#define IOC4_SBBR01_H	        0x300	/* Serial Port Ring Buffers 
-                                           Base Reg High for Channels 0 1*/
-#define IOC4_SBBR01_L	        0x304	/* Serial Port Ring Buffers 
-                                           Base Reg Low for Channels 0 1 */
-#define IOC4_SBBR23_H	        0x308	/* Serial Port Ring Buffers 
-                                           Base Reg High for Channels 2 3*/
-#define IOC4_SBBR23_L	        0x30C	/* Serial Port Ring Buffers 
-                                           Base Reg Low for Channels 2 3 */
-
-#define IOC4_SSCR_0	        0x310	/* Serial Port 0 Control */
-#define IOC4_STPIR_0	        0x314	/* Serial Port 0 TX Produce */
-#define IOC4_STCIR_0	        0x318	/* Serial Port 0 TX Consume */
-#define IOC4_SRPIR_0	        0x31C	/* Serial Port 0 RX Produce */
-#define IOC4_SRCIR_0	        0x320	/* Serial Port 0 RX Consume */
-#define IOC4_SRTR_0	        0x324	/* Serial Port 0 Receive Timer Reg */
-#define IOC4_SHADOW_0		0x328	/* Serial Port 0 16550 Shadow Reg */
-
-#define IOC4_SSCR_1	        0x32C	/* Serial Port 1 Control */
-#define IOC4_STPIR_1	        0x330	/* Serial Port 1 TX Produce */
-#define IOC4_STCIR_1	        0x334	/* Serial Port 1 TX Consume */
-#define IOC4_SRPIR_1	        0x338   /* Serial Port 1 RX Produce */
-#define IOC4_SRCIR_1	        0x33C	/* Serial Port 1 RX Consume */
-#define IOC4_SRTR_1	        0x340	/* Serial Port 1 Receive Timer Reg */
-#define IOC4_SHADOW_1		0x344	/* Serial Port 1 16550 Shadow Reg */
-
-#define IOC4_SSCR_2	        0x348	/* Serial Port 2 Control */
-#define IOC4_STPIR_2	        0x34C	/* Serial Port 2 TX Produce */
-#define IOC4_STCIR_2	        0x350	/* Serial Port 2 TX Consume */
-#define IOC4_SRPIR_2	        0x354	/* Serial Port 2 RX Produce */
-#define IOC4_SRCIR_2	        0x358	/* Serial Port 2 RX Consume */
-#define IOC4_SRTR_2	        0x35C	/* Serial Port 2 Receive Timer Reg */
-#define IOC4_SHADOW_2		0x360	/* Serial Port 2 16550 Shadow Reg */
-
-#define IOC4_SSCR_3	        0x364	/* Serial Port 3 Control */
-#define IOC4_STPIR_3	        0x368	/* Serial Port 3 TX Produce */
-#define IOC4_STCIR_3	        0x36C	/* Serial Port 3 TX Consume */
-#define IOC4_SRPIR_3	        0x370	/* Serial Port 3 RX Produce */
-#define IOC4_SRCIR_3	        0x374	/* Serial Port 3 RX Consume */
-#define IOC4_SRTR_3	        0x378	/* Serial Port 3 Receive Timer Reg */
-#define IOC4_SHADOW_3		0x37C	/* Serial Port 3 16550 Shadow Reg */
-
-#define IOC4_UART0_BASE         0x380   /* UART 0 */
-#define IOC4_UART1_BASE         0x388   /* UART 1 */
-#define IOC4_UART2_BASE         0x390   /* UART 2 */
-#define IOC4_UART3_BASE         0x398   /* UART 3 */
-
-/* Private page address aliases for usermode mapping */
-#define IOC4_INT_OUT_P	        0x04000	/* INT_OUT Reg */
-
-#define IOC4_SSCR_0_P	        0x08000 /* Serial Port 0 */
-#define IOC4_STPIR_0_P	        0x08004
-#define IOC4_STCIR_0_P	        0x08008	/* (read-only) */
-#define IOC4_SRPIR_0_P	        0x0800C	/* (read-only) */
-#define IOC4_SRCIR_0_P	        0x08010
-#define IOC4_SRTR_0_P	        0x08014
-#define IOC4_UART_LSMSMCR_0_P   0x08018	/* (read-only) */
-
-#define IOC4_SSCR_1_P	        0x0C000	/* Serial Port 1 */
-#define IOC4_STPIR_1_P	        0x0C004
-#define IOC4_STCIR_1_P	        0x0C008	/* (read-only) */
-#define IOC4_SRPIR_1_P	        0x0C00C	/* (read-only) */
-#define IOC4_SRCIR_1_P	        0x0C010
-#define IOC4_SRTR_1_P	        0x0C014
-#define IOC4_UART_LSMSMCR_1_P   0x0C018	/* (read-only) */
-
-#define IOC4_SSCR_2_P	        0x10000	/* Serial Port 2 */
-#define IOC4_STPIR_2_P	        0x10004
-#define IOC4_STCIR_2_P	        0x10008	/* (read-only) */
-#define IOC4_SRPIR_2_P	        0x1000C	/* (read-only) */
-#define IOC4_SRCIR_2_P	        0x10010
-#define IOC4_SRTR_2_P	        0x10014
-#define IOC4_UART_LSMSMCR_2_P   0x10018	/* (read-only) */
-
-#define IOC4_SSCR_3_P	        0x14000	/* Serial Port 3 */
-#define IOC4_STPIR_3_P	        0x14004
-#define IOC4_STCIR_3_P	        0x14008	/* (read-only) */
-#define IOC4_SRPIR_3_P	        0x1400C	/* (read-only) */
-#define IOC4_SRCIR_3_P	        0x14010
-#define IOC4_SRTR_3_P	        0x14014
-#define IOC4_UART_LSMSMCR_3_P   0x14018	/* (read-only) */
-
-#define IOC4_ALIAS_PAGE_SIZE	0x4000
-
-/* Interrupt types */
-typedef enum ioc4_intr_type_e {
-    ioc4_sio_intr_type,
-    ioc4_other_intr_type,
-    ioc4_num_intr_types
-} ioc4_intr_type_t;
-#define ioc4_first_intr_type    ioc4_sio_intr_type
-
-/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES  */
-#define IOC4_SIO_IR_S0_TX_MT		0x00000001 /* Serial port 0 TX empty */
-#define IOC4_SIO_IR_S0_RX_FULL		0x00000002 /* Port 0 RX buf full */
-#define IOC4_SIO_IR_S0_RX_HIGH		0x00000004 /* Port 0 RX hiwat */
-#define IOC4_SIO_IR_S0_RX_TIMER		0x00000008 /* Port 0 RX timeout */
-#define IOC4_SIO_IR_S0_DELTA_DCD	0x00000010 /* Port 0 delta DCD */
-#define IOC4_SIO_IR_S0_DELTA_CTS	0x00000020 /* Port 0 delta CTS */
-#define IOC4_SIO_IR_S0_INT	        0x00000040 /* Port 0 pass-thru intr */
-#define IOC4_SIO_IR_S0_TX_EXPLICIT	0x00000080 /* Port 0 explicit TX thru */
-#define IOC4_SIO_IR_S1_TX_MT		0x00000100 /* Serial port 1 */
-#define IOC4_SIO_IR_S1_RX_FULL		0x00000200 /* */
-#define IOC4_SIO_IR_S1_RX_HIGH		0x00000400 /* */
-#define IOC4_SIO_IR_S1_RX_TIMER		0x00000800 /* */
-#define IOC4_SIO_IR_S1_DELTA_DCD	0x00001000 /* */
-#define IOC4_SIO_IR_S1_DELTA_CTS	0x00002000 /* */
-#define IOC4_SIO_IR_S1_INT		0x00004000 /* */
-#define IOC4_SIO_IR_S1_TX_EXPLICIT	0x00008000 /* */
-#define IOC4_SIO_IR_S2_TX_MT		0x00010000 /* Serial port 2 */
-#define IOC4_SIO_IR_S2_RX_FULL		0x00020000 /* */
-#define IOC4_SIO_IR_S2_RX_HIGH		0x00040000 /* */
-#define IOC4_SIO_IR_S2_RX_TIMER		0x00080000 /* */
-#define IOC4_SIO_IR_S2_DELTA_DCD	0x00100000 /* */
-#define IOC4_SIO_IR_S2_DELTA_CTS	0x00200000 /* */
-#define IOC4_SIO_IR_S2_INT		0x00400000 /* */
-#define IOC4_SIO_IR_S2_TX_EXPLICIT	0x00800000 /* */
-#define IOC4_SIO_IR_S3_TX_MT		0x01000000 /* Serial port 3 */
-#define IOC4_SIO_IR_S3_RX_FULL		0x02000000 /* */
-#define IOC4_SIO_IR_S3_RX_HIGH		0x04000000 /* */
-#define IOC4_SIO_IR_S3_RX_TIMER		0x08000000 /* */
-#define IOC4_SIO_IR_S3_DELTA_DCD	0x10000000 /* */
-#define IOC4_SIO_IR_S3_DELTA_CTS	0x20000000 /* */
-#define IOC4_SIO_IR_S3_INT		0x40000000 /* */
-#define IOC4_SIO_IR_S3_TX_EXPLICIT	0x80000000 /* */
-
-/* Per device interrupt masks */
-#define IOC4_SIO_IR_S0		(IOC4_SIO_IR_S0_TX_MT | \
-				 IOC4_SIO_IR_S0_RX_FULL | \
-				 IOC4_SIO_IR_S0_RX_HIGH | \
-				 IOC4_SIO_IR_S0_RX_TIMER | \
-				 IOC4_SIO_IR_S0_DELTA_DCD | \
-				 IOC4_SIO_IR_S0_DELTA_CTS | \
-				 IOC4_SIO_IR_S0_INT | \
-				 IOC4_SIO_IR_S0_TX_EXPLICIT)
-#define IOC4_SIO_IR_S1		(IOC4_SIO_IR_S1_TX_MT | \
-				 IOC4_SIO_IR_S1_RX_FULL | \
-				 IOC4_SIO_IR_S1_RX_HIGH | \
-				 IOC4_SIO_IR_S1_RX_TIMER | \
-				 IOC4_SIO_IR_S1_DELTA_DCD | \
-				 IOC4_SIO_IR_S1_DELTA_CTS | \
-				 IOC4_SIO_IR_S1_INT | \
-				 IOC4_SIO_IR_S1_TX_EXPLICIT)
-#define IOC4_SIO_IR_S2		(IOC4_SIO_IR_S2_TX_MT | \
-				 IOC4_SIO_IR_S2_RX_FULL | \
-				 IOC4_SIO_IR_S2_RX_HIGH | \
-				 IOC4_SIO_IR_S2_RX_TIMER | \
-				 IOC4_SIO_IR_S2_DELTA_DCD | \
-				 IOC4_SIO_IR_S2_DELTA_CTS | \
-				 IOC4_SIO_IR_S2_INT | \
-				 IOC4_SIO_IR_S2_TX_EXPLICIT)
-#define IOC4_SIO_IR_S3		(IOC4_SIO_IR_S3_TX_MT | \
-				 IOC4_SIO_IR_S3_RX_FULL | \
-				 IOC4_SIO_IR_S3_RX_HIGH | \
-				 IOC4_SIO_IR_S3_RX_TIMER | \
-				 IOC4_SIO_IR_S3_DELTA_DCD | \
-				 IOC4_SIO_IR_S3_DELTA_CTS | \
-				 IOC4_SIO_IR_S3_INT | \
-				 IOC4_SIO_IR_S3_TX_EXPLICIT)
-
-/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES  */
-#define IOC4_OTHER_IR_ATA_INT           0x00000001 /* ATAPI intr pass-thru */
-#define IOC4_OTHER_IR_ATA_MEMERR        0x00000002 /* ATAPI DMA PCI error */
-#define IOC4_OTHER_IR_S0_MEMERR         0x00000004 /* Port 0 PCI error */
-#define IOC4_OTHER_IR_S1_MEMERR         0x00000008 /* Port 1 PCI error */
-#define IOC4_OTHER_IR_S2_MEMERR         0x00000010 /* Port 2 PCI error */
-#define IOC4_OTHER_IR_S3_MEMERR         0x00000020 /* Port 3 PCI error */
-#define IOC4_OTHER_IR_KBD_INT		0x00000040 /* Kbd/mouse intr */
-#define IOC4_OTHER_IR_ATA_DMAINT        0x00000089 /* ATAPI DMA intr */
-#define IOC4_OTHER_IR_RT_INT		0x00800000 /* RT output pulse */
-#define IOC4_OTHER_IR_GEN_INT1		0x02000000 /* RT input pulse */
-#define IOC4_OTHER_IR_GEN_INT_SHIFT	        25
-
-/* Per device interrupt masks */
-#define IOC4_OTHER_IR_ATA       (IOC4_OTHER_IR_ATA_INT | \
-				 IOC4_OTHER_IR_ATA_MEMERR | \
-				 IOC4_OTHER_IR_ATA_DMAINT)
-#define IOC4_OTHER_IR_RT	(IOC4_OTHER_IR_RT_INT | IOC4_OTHER_IR_GEN_INT1)
-
-/* Macro to load pending interrupts */
-#define IOC4_PENDING_SIO_INTRS(mem)     (PCI_INW(&((mem)->sio_ir)) & \
-				         PCI_INW(&((mem)->sio_ies_ro)))
-#define IOC4_PENDING_OTHER_INTRS(mem)   (PCI_INW(&((mem)->other_ir)) & \
-				         PCI_INW(&((mem)->other_ies_ro)))
-
-/* Bitmasks for IOC4_SIO_CR */
-#define IOC4_SIO_SR_CMD_PULSE		0x00000004 /* Byte bus strobe length */
-#define IOC4_SIO_CR_CMD_PULSE_SHIFT              0
-#define IOC4_SIO_CR_ARB_DIAG		0x00000070 /* Current non-ATA PCI bus
-                                                      requester (ro) */
-#define IOC4_SIO_CR_ARB_DIAG_TX0	0x00000000
-#define IOC4_SIO_CR_ARB_DIAG_RX0	0x00000010
-#define IOC4_SIO_CR_ARB_DIAG_TX1	0x00000020
-#define IOC4_SIO_CR_ARB_DIAG_RX1	0x00000030
-#define IOC4_SIO_CR_ARB_DIAG_TX2	0x00000040
-#define IOC4_SIO_CR_ARB_DIAG_RX2	0x00000050
-#define IOC4_SIO_CR_ARB_DIAG_TX3	0x00000060
-#define IOC4_SIO_CR_ARB_DIAG_RX3	0x00000070
-#define IOC4_SIO_CR_SIO_DIAG_IDLE	0x00000080 /* 0 -> active request among
-                                                      serial ports (ro) */
-#define IOC4_SIO_CR_ATA_DIAG_IDLE	0x00000100 /* 0 -> active request from
-                                                      ATA port */
-#define IOC4_SIO_CR_ATA_DIAG_ACTIVE     0x00000200 /* 1 -> ATA request is winner */ 
-
-/* Bitmasks for IOC4_INT_OUT */
-#define IOC4_INT_OUT_COUNT	        0x0000ffff /* Pulse interval timer */
-#define IOC4_INT_OUT_MODE	        0x00070000 /* Mode mask */
-#define IOC4_INT_OUT_MODE_0             0x00000000 /* Set output to 0 */
-#define IOC4_INT_OUT_MODE_1             0x00040000 /* Set output to 1 */
-#define IOC4_INT_OUT_MODE_1PULSE        0x00050000 /* Send 1 pulse */
-#define IOC4_INT_OUT_MODE_PULSES        0x00060000 /* Send 1 pulse every interval */
-#define IOC4_INT_OUT_MODE_SQW           0x00070000 /* Toggle output every interval */
-#define IOC4_INT_OUT_DIAG	        0x40000000 /* Diag mode */
-#define IOC4_INT_OUT_INT_OUT            0x80000000 /* Current state of INT_OUT */
-
-/* Time constants for IOC4_INT_OUT */
-#define IOC4_INT_OUT_NS_PER_TICK        (15 * 520) /* 15 ns PCI clock, multi=520 */
-#define IOC4_INT_OUT_TICKS_PER_PULSE             3 /* Outgoing pulse lasts 3
-                                                      ticks */
-#define IOC4_INT_OUT_US_TO_COUNT(x)	           /* Convert uS to a count value */ \
-	(((x) * 10 + IOC4_INT_OUT_NS_PER_TICK / 200) *	\
-	 100 / IOC4_INT_OUT_NS_PER_TICK - 1)
-#define IOC4_INT_OUT_COUNT_TO_US(x)	           /* Convert count value to uS */ \
-	(((x) + 1) * IOC4_INT_OUT_NS_PER_TICK / 1000)
-#define IOC4_INT_OUT_MIN_TICKS                   3 /* Min period is width of
-                                                      pulse in "ticks" */
-#define IOC4_INT_OUT_MAX_TICKS  IOC4_INT_OUT_COUNT /* Largest possible count */
-
-/* Bitmasks for IOC4_GPCR */
-#define IOC4_GPCR_DIR	                0x000000ff /* Tristate pin in or out */
-#define IOC4_GPCR_DIR_PIN(x)              (1<<(x)) /* Access one of the DIR bits */
-#define IOC4_GPCR_EDGE	                0x0000ff00 /* Extint edge or level
-                                                      sensitive */
-#define IOC4_GPCR_EDGE_PIN(x)        (1<<((x)+7 )) /* Access one of the EDGE bits */
-
-/* Values for IOC4_GPCR */
-#define IOC4_GPCR_INT_OUT_EN            0x00100000 /* Enable INT_OUT to pin 0 */
-#define IOC4_GPCR_DIR_SER0_XCVR         0x00000010 /* Port 0 Transceiver select
-                                                      enable */
-#define IOC4_GPCR_DIR_SER1_XCVR         0x00000020 /* Port 1 Transceiver select
-                                                      enable */
-#define IOC4_GPCR_DIR_SER2_XCVR         0x00000040 /* Port 2 Transceiver select
-                                                      enable */
-#define IOC4_GPCR_DIR_SER3_XCVR         0x00000080 /* Port 3 Transceiver select
-                                                      enable */
-
-/* Defs for some of the generic I/O pins */
-#define IOC4_GPCR_UART0_MODESEL	              0x10 /* Pin is output to port 0
-                                                      mode sel */
-#define IOC4_GPCR_UART1_MODESEL	              0x20 /* Pin is output to port 1
-                                                      mode sel */
-#define IOC4_GPCR_UART2_MODESEL	              0x40 /* Pin is output to port 2
-                                                      mode sel */
-#define IOC4_GPCR_UART3_MODESEL	              0x80 /* Pin is output to port 3
-                                                      mode sel */
-
-#define IOC4_GPPR_UART0_MODESEL_PIN	         4 /* GIO pin controlling
-                                                      uart 0 mode select */
-#define IOC4_GPPR_UART1_MODESEL_PIN	         5 /* GIO pin controlling
-                                                      uart 1 mode select */
-#define IOC4_GPPR_UART2_MODESEL_PIN	         6 /* GIO pin controlling
-                                                      uart 2 mode select */
-#define IOC4_GPPR_UART3_MODESEL_PIN	         7 /* GIO pin controlling
-                                                      uart 3 mode select */
-
-/* Bitmasks for IOC4_ATA_TIMING */
-#define IOC4_ATA_TIMING_ADR_SETUP	0x00000003 /* Clocks of addr set-up */
-#define IOC4_ATA_TIMING_PULSE_WIDTH	0x000001f8 /* Clocks of read or write
-                                                      pulse width */
-#define IOC4_ATA_TIMING_RECOVERY	0x0000fe00 /* Clocks before next read
-                                                      or write */
-#define IOC4_ATA_TIMING_USE_IORDY	0x00010000 /* PIO uses IORDY */
-
-/* Bitmasks for address list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */
-#define IOC4_ATA_ALE_DMA_ADDRESS        0xfffffffffffffffe
-
-/* Bitmasks for byte count list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */
-#define IOC4_ATA_BCLE_BYTE_COUNT        0x000000000000fffe
-#define IOC4_ATA_BCLE_LIST_END          0x0000000080000000
-
-/* Bitmasks for IOC4_ATA_BC_<DEV|MEM> */
-#define IOC4_ATA_BC_BYTE_CNT            0x0001fffe /* Byte count */
-
-/* Bitmasks for IOC4_ATA_DMA_CTRL */
-#define IOC4_ATA_DMA_CTRL_STRAT		0x00000001 /* 1 -> start DMA engine */
-#define IOC4_ATA_DMA_CTRL_STOP		0x00000002 /* 1 -> stop DMA engine */
-#define IOC4_ATA_DMA_CTRL_DIR		0x00000004 /* 1 -> ATA bus data copied
-                                                      to memory */
-#define IOC4_ATA_DMA_CTRL_ACTIVE	0x00000008 /* DMA channel is active */
-#define IOC4_ATA_DMA_CTRL_MEM_ERROR	0x00000010 /* DMA engine encountered 
-						      a PCI error */
-/* Bitmasks for IOC4_KM_CSR */
-#define IOC4_KM_CSR_K_WRT_PEND  0x00000001 /* Kbd port xmitting or resetting */
-#define IOC4_KM_CSR_M_WRT_PEND  0x00000002 /* Mouse port xmitting or resetting */
-#define IOC4_KM_CSR_K_LCB       0x00000004 /* Line Cntrl Bit for last KBD write */
-#define IOC4_KM_CSR_M_LCB       0x00000008 /* Same for mouse */
-#define IOC4_KM_CSR_K_DATA      0x00000010 /* State of kbd data line */
-#define IOC4_KM_CSR_K_CLK       0x00000020 /* State of kbd clock line */
-#define IOC4_KM_CSR_K_PULL_DATA 0x00000040 /* Pull kbd data line low */
-#define IOC4_KM_CSR_K_PULL_CLK  0x00000080 /* Pull kbd clock line low */
-#define IOC4_KM_CSR_M_DATA      0x00000100 /* State of mouse data line */
-#define IOC4_KM_CSR_M_CLK       0x00000200 /* State of mouse clock line */
-#define IOC4_KM_CSR_M_PULL_DATA 0x00000400 /* Pull mouse data line low */
-#define IOC4_KM_CSR_M_PULL_CLK  0x00000800 /* Pull mouse clock line low */
-#define IOC4_KM_CSR_EMM_MODE	0x00001000 /* Emulation mode */
-#define IOC4_KM_CSR_SIM_MODE	0x00002000 /* Clock X8 */
-#define IOC4_KM_CSR_K_SM_IDLE   0x00004000 /* Keyboard is idle */
-#define IOC4_KM_CSR_M_SM_IDLE   0x00008000 /* Mouse is idle */
-#define IOC4_KM_CSR_K_TO	0x00010000 /* Keyboard trying to send/receive */
-#define IOC4_KM_CSR_M_TO        0x00020000 /* Mouse trying to send/receive */
-#define IOC4_KM_CSR_K_TO_EN     0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN =
-                                              cause SIO_IR to assert */
-#define IOC4_KM_CSR_M_TO_EN	0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN =
-                                              cause SIO_IR to assert */
-#define IOC4_KM_CSR_K_CLAMP_ONE	0x00100000 /* Pull K_CLK low after rec. one char */
-#define IOC4_KM_CSR_M_CLAMP_ONE	0x00200000 /* Pull M_CLK low after rec. one char */
-#define IOC4_KM_CSR_K_CLAMP_THREE \
-                           	0x00400000 /* Pull K_CLK low after rec. three chars */
-#define IOC4_KM_CSR_M_CLAMP_THREE \
-                            	0x00800000 /* Pull M_CLK low after rec. three char */
-
-/* Bitmasks for IOC4_K_RD and IOC4_M_RD */
-#define IOC4_KM_RD_DATA_2       0x000000ff /* 3rd char recvd since last read */
-#define IOC4_KM_RD_DATA_2_SHIFT          0
-#define IOC4_KM_RD_DATA_1       0x0000ff00 /* 2nd char recvd since last read */
-#define IOC4_KM_RD_DATA_1_SHIFT          8
-#define IOC4_KM_RD_DATA_0	0x00ff0000 /* 1st char recvd since last read */
-#define IOC4_KM_RD_DATA_0_SHIFT         16
-#define IOC4_KM_RD_FRAME_ERR_2  0x01000000 /* Framing or parity error in byte 2 */
-#define IOC4_KM_RD_FRAME_ERR_1  0x02000000 /* Same for byte 1 */
-#define IOC4_KM_RD_FRAME_ERR_0  0x04000000 /* Same for byte 0 */
-
-#define IOC4_KM_RD_KBD_MSE      0x08000000 /* 0 if from kbd, 1 if from mouse */
-#define IOC4_KM_RD_OFLO	        0x10000000 /* 4th char recvd before this read */
-#define IOC4_KM_RD_VALID_2      0x20000000 /* DATA_2 valid */
-#define IOC4_KM_RD_VALID_1      0x40000000 /* DATA_1 valid */
-#define IOC4_KM_RD_VALID_0      0x80000000 /* DATA_0 valid */
-#define IOC4_KM_RD_VALID_ALL    (IOC4_KM_RD_VALID_0 | IOC4_KM_RD_VALID_1 | \
-                                 IOC4_KM_RD_VALID_2)
-
-/* Bitmasks for IOC4_K_WD & IOC4_M_WD */
-#define IOC4_KM_WD_WRT_DATA     0x000000ff /* Write to keyboard/mouse port */
-#define IOC4_KM_WD_WRT_DATA_SHIFT        0
-
-/* Bitmasks for serial RX status byte */
-#define IOC4_RXSB_OVERRUN       0x01       /* Char(s) lost */
-#define IOC4_RXSB_PAR_ERR	0x02	   /* Parity error */
-#define IOC4_RXSB_FRAME_ERR	0x04	   /* Framing error */
-#define IOC4_RXSB_BREAK	        0x08	   /* Break character */
-#define IOC4_RXSB_CTS	        0x10	   /* State of CTS */
-#define IOC4_RXSB_DCD	        0x20	   /* State of DCD */
-#define IOC4_RXSB_MODEM_VALID   0x40	   /* DCD, CTS, and OVERRUN are valid */
-#define IOC4_RXSB_DATA_VALID    0x80	   /* Data byte, FRAME_ERR PAR_ERR & BREAK valid */
-
-/* Bitmasks for serial TX control byte */
-#define IOC4_TXCB_INT_WHEN_DONE 0x20       /* Interrupt after this byte is sent */
-#define IOC4_TXCB_INVALID	0x00	   /* Byte is invalid */
-#define IOC4_TXCB_VALID	        0x40	   /* Byte is valid */
-#define IOC4_TXCB_MCR	        0x80	   /* Data<7:0> to modem control register */
-#define IOC4_TXCB_DELAY	        0xc0	   /* Delay data<7:0> mSec */
-
-/* Bitmasks for IOC4_SBBR_L */
-#define IOC4_SBBR_L_SIZE	0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
-#define IOC4_SBBR_L_BASE	0xfffff000 /* Lower serial ring base addr */
-
-/* Bitmasks for IOC4_SSCR_<3:0> */
-#define IOC4_SSCR_RX_THRESHOLD  0x000001ff /* Hiwater mark */
-#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
-#define IOC4_SSCR_HFC_EN	0x00020000 /* Hardware flow control enabled */
-#define IOC4_SSCR_RX_RING_DCD   0x00040000 /* Post RX record on delta-DCD */
-#define IOC4_SSCR_RX_RING_CTS   0x00080000 /* Post RX record on delta-CTS */
-#define IOC4_SSCR_DIAG	        0x00200000 /* Bypass clock divider for sim */
-#define IOC4_SSCR_RX_DRAIN	0x08000000 /* Drain RX buffer to memory */
-#define IOC4_SSCR_DMA_EN	0x10000000 /* Enable ring buffer DMA */
-#define IOC4_SSCR_DMA_PAUSE	0x20000000 /* Pause DMA */
-#define IOC4_SSCR_PAUSE_STATE   0x40000000 /* Sets when PAUSE takes effect */
-#define IOC4_SSCR_RESET	        0x80000000 /* Reset DMA channels */
-
-/* All producer/comsumer pointers are the same bitfield */
-#define IOC4_PROD_CONS_PTR_4K   0x00000ff8 /* For 4K buffers */
-#define IOC4_PROD_CONS_PTR_1K   0x000003f8 /* For 1K buffers */
-#define IOC4_PROD_CONS_PTR_OFF           3
-
-/* Bitmasks for IOC4_STPIR_<3:0> */
-/* Reserved for future register definitions */
-
-/* Bitmasks for IOC4_STCIR_<3:0> */
-#define IOC4_STCIR_BYTE_CNT     0x0f000000 /* Bytes in unpacker */
-#define IOC4_STCIR_BYTE_CNT_SHIFT       24
-
-/* Bitmasks for IOC4_SRPIR_<3:0> */
-#define IOC4_SRPIR_BYTE_CNT	0x0f000000 /* Bytes in packer */
-#define IOC4_SRPIR_BYTE_CNT_SHIFT       24
-
-/* Bitmasks for IOC4_SRCIR_<3:0> */
-#define IOC4_SRCIR_ARM	        0x80000000 /* Arm RX timer */
-
-/* Bitmasks for IOC4_SHADOW_<3:0> */
-#define IOC4_SHADOW_DR          0x00000001  /* Data ready */
-#define IOC4_SHADOW_OE          0x00000002  /* Overrun error */
-#define IOC4_SHADOW_PE          0x00000004  /* Parity error */
-#define IOC4_SHADOW_FE          0x00000008  /* Framing error */
-#define IOC4_SHADOW_BI          0x00000010  /* Break interrupt */
-#define IOC4_SHADOW_THRE        0x00000020  /* Xmit holding register empty */
-#define IOC4_SHADOW_TEMT        0x00000040  /* Xmit shift register empty */
-#define IOC4_SHADOW_RFCE        0x00000080  /* Char in RX fifo has an error */
-#define IOC4_SHADOW_DCTS        0x00010000  /* Delta clear to send */
-#define IOC4_SHADOW_DDCD        0x00080000  /* Delta data carrier detect */
-#define IOC4_SHADOW_CTS         0x00100000  /* Clear to send */
-#define IOC4_SHADOW_DCD         0x00800000  /* Data carrier detect */
-#define IOC4_SHADOW_DTR         0x01000000  /* Data terminal ready */
-#define IOC4_SHADOW_RTS         0x02000000  /* Request to send */
-#define IOC4_SHADOW_OUT1        0x04000000  /* 16550 OUT1 bit */
-#define IOC4_SHADOW_OUT2        0x08000000  /* 16550 OUT2 bit */
-#define IOC4_SHADOW_LOOP        0x10000000  /* Loopback enabled */
-
-/* Bitmasks for IOC4_SRTR_<3:0> */
-#define IOC4_SRTR_CNT	        0x00000fff /* Reload value for RX timer */
-#define IOC4_SRTR_CNT_VAL	0x0fff0000 /* Current value of RX timer */
-#define IOC4_SRTR_CNT_VAL_SHIFT         16
-#define IOC4_SRTR_HZ                 16000 /* SRTR clock frequency */
-
-/* Serial port register map used for DMA and PIO serial I/O */
-typedef volatile struct ioc4_serialregs {
-    ioc4reg_t		    sscr;
-    ioc4reg_t		    stpir;
-    ioc4reg_t		    stcir;
-    ioc4reg_t		    srpir;
-    ioc4reg_t		    srcir;
-    ioc4reg_t		    srtr;
-    ioc4reg_t		    shadow;
-} ioc4_sregs_t;
-
-/* IOC4 UART register map */
-typedef volatile struct ioc4_uartregs {
-    union {
-        char                    rbr;    /* read only, DLAB == 0 */
-        char                    thr;    /* write only, DLAB == 0 */
-        char                    dll;    /* DLAB == 1 */
-    } u1;
-    union {
-        char                    ier;    /* DLAB == 0 */
-        char                    dlm;    /* DLAB == 1 */
-    } u2;
-    union {
-        char                    iir;    /* read only */
-        char                    fcr;    /* write only */
-    } u3;
-    char                    i4u_lcr;
-    char                    i4u_mcr;
-    char                    i4u_lsr;
-    char                    i4u_msr;
-    char                    i4u_scr;
-} ioc4_uart_t;
-
-#define i4u_rbr u1.rbr
-#define i4u_thr u1.thr
-#define i4u_dll u1.dll
-#define i4u_ier u2.ier
-#define i4u_dlm u2.dlm
-#define i4u_iir u3.iir
-#define i4u_fcr u3.fcr
-
-/* PCI config space register map */
-typedef volatile struct ioc4_configregs {
-    ioc4reg_t		    pci_id;
-    ioc4reg_t		    pci_scr;
-    ioc4reg_t		    pci_rev;
-    ioc4reg_t		    pci_lat;
-    ioc4reg_t		    pci_bar0;
-    ioc4reg_t		    pci_bar1;
-    ioc4reg_t               pci_bar2_not_implemented;
-    ioc4reg_t               pci_cis_ptr_not_implemented;
-    ioc4reg_t		    pci_sidv;
-    ioc4reg_t		    pci_rom_bar_not_implemented;
-    ioc4reg_t		    pci_cap;
-    ioc4reg_t		    pci_rsv;
-    ioc4reg_t		    pci_latgntint;
-
-    char                    pci_fill1[0x58 - 0x3c - 4];
-
-    ioc4reg_t               pci_pcix;
-    ioc4reg_t               pci_pcixstatus;
-} ioc4_cfg_t;
-
-/* PCI memory space register map addressed using pci_bar0 */
-typedef volatile struct ioc4_memregs {
-
-    /* Miscellaneous IOC4  registers */
-    ioc4reg_t		    pci_err_addr_l;
-    ioc4reg_t		    pci_err_addr_h;
-    ioc4reg_t		    sio_ir;
-    ioc4reg_t		    other_ir;
-
-    /* These registers are read-only for general kernel code.  To
-     * modify them use the functions in ioc4.c.
-     */
-    ioc4reg_t		    sio_ies_ro;
-    ioc4reg_t		    other_ies_ro;
-    ioc4reg_t		    sio_iec_ro;
-    ioc4reg_t		    other_iec_ro;
-    ioc4reg_t		    sio_cr;
-    ioc4reg_t		    misc_fill1;
-    ioc4reg_t		    int_out;
-    ioc4reg_t		    misc_fill2;
-    ioc4reg_t		    gpcr_s;
-    ioc4reg_t		    gpcr_c;
-    ioc4reg_t		    gpdr;
-    ioc4reg_t		    misc_fill3;
-    ioc4reg_t		    gppr_0;
-    ioc4reg_t		    gppr_1;
-    ioc4reg_t		    gppr_2;
-    ioc4reg_t		    gppr_3;
-    ioc4reg_t		    gppr_4;
-    ioc4reg_t		    gppr_5;
-    ioc4reg_t		    gppr_6;
-    ioc4reg_t		    gppr_7;
-
-    char		    misc_fill4[0x100 - 0x5C - 4];
-
-    /* ATA/ATAP registers */
-    ioc4reg_t		    ata_0;
-    ioc4reg_t		    ata_1;
-    ioc4reg_t		    ata_2;
-    ioc4reg_t		    ata_3;
-    ioc4reg_t		    ata_4;
-    ioc4reg_t		    ata_5;
-    ioc4reg_t		    ata_6;
-    ioc4reg_t		    ata_7;
-    ioc4reg_t		    ata_aux;
-
-    char		    ata_fill1[0x140 - 0x120 - 4];
-
-    ioc4reg_t		    ata_timing;
-    ioc4reg_t		    ata_dma_ptr_l;
-    ioc4reg_t		    ata_dma_ptr_h;
-    ioc4reg_t		    ata_dma_addr_l;
-    ioc4reg_t		    ata_dma_addr_h;
-    ioc4reg_t		    ata_bc_dev;
-    ioc4reg_t		    ata_bc_mem;
-    ioc4reg_t		    ata_dma_ctrl;
-
-    char		    ata_fill2[0x200 - 0x15C - 4];
-
-    /* Keyboard and mouse registers */
-    ioc4reg_t		    km_csr;
-    ioc4reg_t		    k_rd;
-    ioc4reg_t		    m_rd;
-    ioc4reg_t		    k_wd;
-    ioc4reg_t		    m_wd;
-
-    char		    km_fill1[0x300 - 0x210 - 4];
-
-    /* Serial port registers used for DMA serial I/O */
-    ioc4reg_t		    sbbr01_l;
-    ioc4reg_t		    sbbr01_h;
-    ioc4reg_t		    sbbr23_l;
-    ioc4reg_t		    sbbr23_h;
-
-    ioc4_sregs_t	    port_0;
-    ioc4_sregs_t	    port_1;
-    ioc4_sregs_t	    port_2;
-    ioc4_sregs_t	    port_3;
-
-    ioc4_uart_t		    uart_0;
-    ioc4_uart_t		    uart_1;
-    ioc4_uart_t		    uart_2;
-    ioc4_uart_t		    uart_3;
-} ioc4_mem_t;
-
-#endif	/* 0 */
-
 /*
  * Bytebus device space
  */
@@ -693,88 +17,4 @@ typedef volatile struct ioc4_memregs {
 #define IOC4_BYTEBUS_DEV2	0xC0000L  /* Addressed using pci_bar0 */
 #define IOC4_BYTEBUS_DEV3	0xE0000L  /* Addressed using pci_bar0 */
 
-#if 0
-/* UART clock speed */
-#define IOC4_SER_XIN_CLK        66000000
-
-typedef enum ioc4_subdevs_e {
-    ioc4_subdev_generic,
-    ioc4_subdev_kbms,
-    ioc4_subdev_tty0,
-    ioc4_subdev_tty1,
-    ioc4_subdev_tty2,
-    ioc4_subdev_tty3,
-    ioc4_subdev_rt,
-    ioc4_nsubdevs
-} ioc4_subdev_t;
-
-/* Subdevice disable bits,
- * from the standard INFO_LBL_SUBDEVS
- */
-#define IOC4_SDB_TTY0		(1 << ioc4_subdev_tty0)
-#define IOC4_SDB_TTY1		(1 << ioc4_subdev_tty1)
-#define IOC4_SDB_TTY2		(1 << ioc4_subdev_tty2)
-#define IOC4_SDB_TTY3		(1 << ioc4_subdev_tty3)
-#define IOC4_SDB_KBMS		(1 << ioc4_subdev_kbms)
-#define IOC4_SDB_RT		(1 << ioc4_subdev_rt)
-#define IOC4_SDB_GENERIC	(1 << ioc4_subdev_generic)
-
-#define IOC4_ALL_SUBDEVS	((1 << ioc4_nsubdevs) - 1)
-
-#define IOC4_SDB_SERIAL		(IOC4_SDB_TTY0 | IOC4_SDB_TTY1 | IOC4_SDB_TTY2 | IOC4_SDB_TTY3)
-
-#define IOC4_STD_SUBDEVS	IOC4_ALL_SUBDEVS
-
-#define IOC4_INTA_SUBDEVS	(IOC4_SDB_SERIAL | IOC4_SDB_KBMS | IOC4_SDB_RT | IOC4_SDB_GENERIC)
-
-extern int		ioc4_subdev_enabled(vertex_hdl_t, ioc4_subdev_t);
-extern void		ioc4_subdev_enables(vertex_hdl_t, ulong_t);
-extern void		ioc4_subdev_enable(vertex_hdl_t, ioc4_subdev_t);
-extern void		ioc4_subdev_disable(vertex_hdl_t, ioc4_subdev_t);
-
-/* Macros to read and write the SIO_IEC and SIO_IES registers (see the
- * comments in ioc4.c for details on why this is necessary
- */
-#define IOC4_W_IES	0
-#define IOC4_W_IEC	1
-extern void		ioc4_write_ireg(void *, ioc4reg_t, int, ioc4_intr_type_t);
-
-#define IOC4_WRITE_IES(ioc4, val, type)	ioc4_write_ireg(ioc4, val, IOC4_W_IES, type)
-#define IOC4_WRITE_IEC(ioc4, val, type)	ioc4_write_ireg(ioc4, val, IOC4_W_IEC, type)
-
-typedef void
-ioc4_intr_func_f	(intr_arg_t, ioc4reg_t);
-
-typedef void
-ioc4_intr_connect_f	(vertex_hdl_t conn_vhdl,
-			 ioc4_intr_type_t,
-			 ioc4reg_t,
-			 ioc4_intr_func_f *,
-			 intr_arg_t info,
-			 vertex_hdl_t owner_vhdl,
-			 vertex_hdl_t intr_dev_vhdl,
-			 int (*)(intr_arg_t));
-
-typedef void
-ioc4_intr_disconnect_f	(vertex_hdl_t conn_vhdl,
-			 ioc4_intr_type_t,
-			 ioc4reg_t,
-			 ioc4_intr_func_f *,
-			 intr_arg_t info,
-			 vertex_hdl_t owner_vhdl);
-
-ioc4_intr_disconnect_f	ioc4_intr_disconnect;
-ioc4_intr_connect_f	ioc4_intr_connect;
-
-extern int		ioc4_is_console(vertex_hdl_t conn_vhdl);
-
-extern void		ioc4_mlreset(ioc4_cfg_t *, ioc4_mem_t *);
-
-extern intr_func_f	ioc4_intr;
-
-extern ioc4_mem_t      *ioc4_mem_ptr(void *ioc4_fastinfo);
-
-typedef ioc4_intr_func_f *ioc4_intr_func_t;
-
-#endif	/* 0 */
 #endif	/* _ASM_IA64_SN_IOC4_H */

include/asm-ia64/sn/ioconfig_bus.h

@@ -20,7 +20,7 @@ struct ioconfig_parm {
 	void *buffer;
 };
 
-struct  ascii_moduleid{
+struct ascii_moduleid {
 	unsigned char   io_moduleid[8]; /* pci path name */
 };
 

include/asm-ia64/sn/ioerror_handling.h

@@ -11,7 +11,7 @@
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
 
-#if __KERNEL__
+#ifdef __KERNEL__
 
 /*
  * Basic types required for io error handling interfaces.
@@ -155,88 +155,5 @@ enum error_class_e {
 	ERROR_CLASS_BAD_RESP_PKT
 };
 
-typedef uint64_t  error_class_t;
-
-
-/* 
- * Error context which the error action can use.
- */
-typedef void			*error_context_t;
-#define ERROR_CONTEXT_IGNORE	((error_context_t)-1ll)
-
-
-/* 
- * Error action type.
- */
-typedef error_return_code_t 	(*error_action_f)( error_context_t);
-#define ERROR_ACTION_IGNORE	((error_action_f)-1ll)
-
-/* Typical set of error actions */
-typedef struct error_action_set_s {
-	error_action_f		eas_panic;
-	error_action_f		eas_shutdown;
-	error_action_f		eas_abort;
-	error_action_f		eas_retry;
-	error_action_f		eas_failover;
-	error_action_f		eas_log_n_ignore;
-	error_action_f		eas_reset;
-} error_action_set_t;
-
-
-/* Set of priorites for in case mutliple error actions/states
- * are trying to be prescribed for a device.
- * NOTE : The ordering below encapsulates the priorities. Highest value
- * corresponds to highest priority.
- */
-enum error_priority_e {
-	ERROR_PRIORITY_IGNORE,
-	ERROR_PRIORITY_NONE,
-	ERROR_PRIORITY_NORMAL,
-	ERROR_PRIORITY_LOG,
-	ERROR_PRIORITY_FAILOVER,
-	ERROR_PRIORITY_RETRY,
-	ERROR_PRIORITY_ABORT,
-	ERROR_PRIORITY_SHUTDOWN,
-	ERROR_PRIORITY_RESTART,
-	ERROR_PRIORITY_PANIC
-};
-
-typedef uint64_t  error_priority_t;
-
-/* Error action interfaces */
-
-extern error_return_code_t	error_action_set(vertex_hdl_t,
-						 error_action_f,
-						 error_context_t,
-						 error_priority_t);
-extern error_return_code_t	error_action_perform(vertex_hdl_t);
-
-
-#define INFO_LBL_ERROR_SKIP_ENV	"error_skip_env"
-
-#define v_error_skip_env_get(v, l)		\
-hwgraph_info_get_LBL(v, INFO_LBL_ERROR_SKIP_ENV, (arbitrary_info_t *)&l)
-
-#define v_error_skip_env_set(v, l, r)		\
-(r ? 						\
- hwgraph_info_replace_LBL(v, INFO_LBL_ERROR_SKIP_ENV, (arbitrary_info_t)l,0) :\
- hwgraph_info_add_LBL(v, INFO_LBL_ERROR_SKIP_ENV, (arbitrary_info_t)l))
-
-#define v_error_skip_env_clear(v)		\
-hwgraph_info_remove_LBL(v, INFO_LBL_ERROR_SKIP_ENV, 0)
-
-typedef uint64_t		counter_t;
-
-extern counter_t		error_retry_count_get(vertex_hdl_t);
-extern error_return_code_t	error_retry_count_set(vertex_hdl_t,counter_t);
-extern counter_t		error_retry_count_increment(vertex_hdl_t);
-extern counter_t		error_retry_count_decrement(vertex_hdl_t);
-
-/* Except for the PIO Read error typically the other errors are handled in
- * the context of an asynchronous error interrupt.
- */
-#define	IS_ERROR_INTR_CONTEXT(_ec)	((_ec & IOECODE_DMA) 		|| \
-					 (_ec == IOECODE_PIO_WRITE))
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_IA64_SN_IOERROR_HANDLING_H */

include/asm-ia64/sn/iograph.h

@@ -8,6 +8,8 @@
 #ifndef _ASM_IA64_SN_IOGRAPH_H
 #define _ASM_IA64_SN_IOGRAPH_H
 
+#include <asm/sn/xtalk/xbow.h>	/* For get MAX_PORT_NUM */
+
 /*
  * During initialization, platform-dependent kernel code establishes some
  * basic elements of the hardware graph.  This file contains edge and
@@ -115,40 +117,13 @@
 #define INFO_LBL_XSWITCH_VOL		"_xswitch_volunteer"
 #define INFO_LBL_XFUNCS			"_xtalk_ops"	/* ops vector for gio providers */
 #define INFO_LBL_XWIDGET		"_xwidget"
-/* Device/Driver  Admin directive labels  */
-#define ADMIN_LBL_INTR_TARGET		"INTR_TARGET"	/* Target cpu for device interrupts*/
-#define ADMIN_LBL_INTR_SWLEVEL		"INTR_SWLEVEL"	/* Priority level of the ithread */
 
-#define	ADMIN_LBL_DMATRANS_NODE		"PCIBUS_DMATRANS_NODE" /* Node used for
-								* 32-bit Direct
-								* Mapping I/O
-								*/
-#define ADMIN_LBL_DISABLED		"DISABLE"	/* Device has been disabled */
-#define ADMIN_LBL_DETACH		"DETACH"	/* Device has been detached */
 
-#define ADMIN_LBL_THREAD_PRI		"thread_priority" 
-							/* Driver adminstrator
-							 * hint parameter for 
-							 * thread priority
-							 */
-#define ADMIN_LBL_THREAD_CLASS		"thread_class" 
-							/* Driver adminstrator
-							 * hint parameter for 
-							 * thread priority
-							 * default class
-							 */
-/* Info labels that begin with '_' cannot be overwritten by an attr_set call */
-#define INFO_LBL_RESERVED(name) ((name)[0] == '_')
-
-#if defined(__KERNEL__)
+#ifdef __KERNEL__
 void init_all_devices(void);
 #endif /* __KERNEL__ */
 
-#include <asm/sn/sgi.h>
-#include <asm/sn/xtalk/xbow.h>	/* For get MAX_PORT_NUM */
-
 int io_brick_map_widget(int, int);
-int io_path_map_widget(vertex_hdl_t);
 
 /*
  * Map a brick's widget number to a meaningful int
@@ -159,5 +134,4 @@ struct io_brick_map_s {
     int                 ibm_map_wid[MAX_PORT_NUM]; /* wid to int map */
 };
 
-
 #endif /* _ASM_IA64_SN_IOGRAPH_H */

include/asm-ia64/sn/leds.h

@@ -8,10 +8,7 @@
  * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved.
  */
 
-#include <linux/config.h>
-#include <asm/smp.h>
 #include <asm/sn/addrs.h>
-#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/pda.h>
 #include <asm/sn/sn2/shub.h>
 
@@ -23,7 +20,7 @@
 #define LED_ALWAYS_SET		0x00
 
 /*
- * Basic macros for flashing the LEDS on an SGI, SN1.
+ * Basic macros for flashing the LEDS on an SGI SN.
  */
 
 static __inline__ void

include/asm-ia64/sn/module.h

@@ -8,12 +8,6 @@
 #ifndef _ASM_IA64_SN_MODULE_H
 #define _ASM_IA64_SN_MODULE_H
 
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-
-#include <asm/semaphore.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/ksys/elsc.h>
 

include/asm-ia64/sn/pci/pci_bus_cvlink.h

@@ -31,14 +31,15 @@
 #define MAX_PCI_XWIDGET 256
 #define MAX_ATE_MAPS 1024
 
+#define SN_DEVICE_SYSDATA(dev) \
+	((struct sn_device_sysdata *) \
+	(((struct pci_controller *) ((dev)->sysdata))->platform_data))
+
 #define IS_PCI32G(dev)	((dev)->dma_mask >= 0xffffffff)
 #define IS_PCI32L(dev)	((dev)->dma_mask < 0xffffffff)
 
 #define PCIDEV_VERTEX(pci_dev) \
-	(((struct sn_device_sysdata *)((pci_dev)->sysdata))->vhdl)
-
-#define PCIBUS_VERTEX(pci_bus) \
-	(((struct sn_widget_sysdata *)((pci_bus)->sysdata))->vhdl)
+	((SN_DEVICE_SYSDATA(pci_dev))->vhdl)
 
 struct sn_widget_sysdata {
         vertex_hdl_t  vhdl;
@@ -47,6 +48,9 @@ struct sn_widget_sysdata {
 struct sn_device_sysdata {
         vertex_hdl_t		vhdl;
 	pciio_provider_t	*pci_provider;
+	pciio_intr_t		intr_handle;
+	struct sn_flush_device_list *dma_flush_list;
+        pciio_piomap_t		pio_map[PCI_ROM_RESOURCE];
 };
 
 struct ioports_to_tlbs_s {

include/asm-ia64/sn/sgi.h

@@ -13,7 +13,6 @@
 #include <linux/config.h>
 
 #include <asm/sn/types.h>
-#include <asm/uaccess.h>		/* for copy_??_user */
 #include <asm/sn/hwgfs.h>
 
 typedef hwgfs_handle_t vertex_hdl_t;

include/asm-ia64/sn/sn2/sn_private.h

@@ -11,6 +11,7 @@
 #include <linux/wait.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
 #include <asm/sn/xtalk/xwidget.h>
 #include <asm/sn/xtalk/xtalk_private.h>