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Commit 192cca6e authored by Franck Bui-Huu's avatar Franck Bui-Huu Committed by Ralf Baechle
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[MIPS] Remove Momenco Ocelot C support 

Signed-off-by: default avatarFranck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>

 delete mode 100644 arch/mips/configs/ocelot_c_defconfig
 delete mode 100644 arch/mips/momentum/ocelot_c/Makefile
 delete mode 100644 arch/mips/momentum/ocelot_c/cpci-irq.c
 delete mode 100644 arch/mips/momentum/ocelot_c/dbg_io.c
 delete mode 100644 arch/mips/momentum/ocelot_c/irq.c
 delete mode 100644 arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
 delete mode 100644 arch/mips/momentum/ocelot_c/platform.c
 delete mode 100644 arch/mips/momentum/ocelot_c/prom.c
 delete mode 100644 arch/mips/momentum/ocelot_c/reset.c
 delete mode 100644 arch/mips/momentum/ocelot_c/setup.c
 delete mode 100644 arch/mips/momentum/ocelot_c/uart-irq.c
 delete mode 100644 arch/mips/pci/fixup-ocelot-c.c
 delete mode 100644 arch/mips/pci/pci-ocelot-c.c
parent cfd2afc0
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Showing with 6 additions and 2543 deletions
arch/mips/Kconfig
View file @ 192cca6e
......@@ -276,24 +276,6 @@ config MOMENCO_OCELOT_3
The Ocelot-3 is based off Discovery III System Controller and
PMC-Sierra Rm79000 core.
config MOMENCO_OCELOT_C
bool "Momentum Ocelot-C board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_MV64340
select PCI_MARVELL
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
help
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
config PNX8550_JBS
bool "Philips PNX8550 based JBS board"
select PNX8550
......
arch/mips/Makefile
View file @ 192cca6e
......@@ -334,14 +334,6 @@ core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \
cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
#
# Momentum Ocelot-C and -CS boards
#
# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the
# mips_io_port_base.
core-$(CONFIG_MOMENCO_OCELOT_C) += arch/mips/momentum/ocelot_c/
load-$(CONFIG_MOMENCO_OCELOT_C) += 0xffffffff80100000
#
# PMC-Sierra Yosemite
#
......
arch/mips/configs/atlas_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_MIPS_ATLAS=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/bigsur_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/capcella_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/cobalt_defconfig
View file @ 192cca6e
......@@ -21,7 +21,6 @@ CONFIG_MIPS_COBALT=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_DDB5477 is not set
......
arch/mips/configs/db1000_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/db1100_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/db1200_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1200=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/db1500_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/db1550_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1550=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/ddb5477_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/decstation_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_MACH_DECSTATION=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/e55_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/emma2rh_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/excite_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_BASLER_EXCITE=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/ip22_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/ip27_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/ip32_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/jazz_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_MACH_JAZZ=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/jmr3927_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/lasat200_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_LASAT=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/malta_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_MIPS_MALTA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/mipssim_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_MIPS_SIM=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/mpc30x_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/ocelot_3_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
CONFIG_MOMENCO_OCELOT_3=y
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/ocelot_c_defconfig deleted 100644 → 0
View file @ cfd2afc0
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.20
# Tue Feb 20 21:47:36 2007
#
CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_ZONE_DMA=y
# CONFIG_MIPS_MTX1 is not set
# CONFIG_MIPS_BOSPORUS is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_MIPS_PB1100 is not set
# CONFIG_MIPS_PB1500 is not set
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_PB1200 is not set
# CONFIG_MIPS_DB1000 is not set
# CONFIG_MIPS_DB1100 is not set
# CONFIG_MIPS_DB1500 is not set
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_LASAT is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
CONFIG_MOMENCO_OCELOT_C=y
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_TOSHIBA_RBTX4938 is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_TIME=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_IRQ_CPU=y
CONFIG_IRQ_MV64340=y
CONFIG_PCI_MARVELL=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
# CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
CONFIG_CPU_RM7000=y
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_SYS_HAS_CPU_RM7000=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
#
# Kernel type
#
# CONFIG_32BIT is not set
CONFIG_64BIT=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_BOARD_SCACHE=y
CONFIG_RM7000_CPU_SCACHE=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_RESOURCES_64BIT=y
CONFIG_ZONE_DMA_FLAG=1
# CONFIG_HZ_48 is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_128 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_256 is not set
CONFIG_HZ_1000=y
# CONFIG_HZ_1024 is not set
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_HZ=1000
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
# CONFIG_KEXEC is not set
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_RELAY=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_BLK_DEV_IO_TRACE is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_HW_HAS_PCI=y
CONFIG_PCI=y
CONFIG_MMU=y
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# PCI Hotplug Support
#
# CONFIG_HOTPLUG_PCI is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_BUILD_ELF64 is not set
CONFIG_MIPS32_COMPAT=y
CONFIG_COMPAT=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_MIPS32_O32=y
CONFIG_MIPS32_N32=y
CONFIG_BINFMT_ELF32=y
#
# Power management options
#
CONFIG_PM=y
# CONFIG_PM_LEGACY is not set
# CONFIG_PM_DEBUG is not set
# CONFIG_PM_SYSFS_DEPRECATED is not set
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_NETDEBUG is not set
# CONFIG_PACKET is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_SUB_POLICY is not set
CONFIG_XFRM_MIGRATE=y
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
CONFIG_NETWORK_SECMARK=y
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
#
# TIPC Configuration (EXPERIMENTAL)
#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_IEEE80211=y
# CONFIG_IEEE80211_DEBUG is not set
CONFIG_IEEE80211_CRYPT_WEP=y
CONFIG_IEEE80211_CRYPT_CCMP=y
CONFIG_IEEE80211_SOFTMAC=y
# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
CONFIG_WIRELESS_EXT=y
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_CDROM_PKTCDVD=y
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
CONFIG_ATA_OVER_ETH=y
#
# Misc devices
#
CONFIG_SGI_IOC4=y
# CONFIG_TIFM_CORE is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_RAID_ATTRS=y
# CONFIG_SCSI is not set
# CONFIG_SCSI_NETLINK is not set
#
# Serial ATA (prod) and Parallel ATA (experimental) drivers
#
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# PHY device support
#
CONFIG_PHYLIB=y
#
# MII PHY device drivers
#
CONFIG_MARVELL_PHY=y
CONFIG_DAVICOM_PHY=y
CONFIG_QSEMI_PHY=y
CONFIG_LXT_PHY=y
CONFIG_CICADA_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_SMSC_PHY=y
# CONFIG_BROADCOM_PHY is not set
# CONFIG_FIXED_PHY is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_DM9000 is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_PCI is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_MV643XX_ETH is not set
CONFIG_QLA3XXX=y
# CONFIG_ATL1 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_CHELSIO_T1 is not set
CONFIG_CHELSIO_T3=y
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
CONFIG_NETXEN_NIC=y
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_PCIPS2 is not set
# CONFIG_SERIO_LIBPS2 is not set
CONFIG_SERIO_RAW=y
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# HID Devices
#
# CONFIG_HID is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
# CONFIG_INFINIBAND is not set
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# Auxiliary Display support
#
#
# Virtualization
#
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=y
CONFIG_GENERIC_ACL=y
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
CONFIG_CONFIGFS_FS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
CONFIG_NFSD=y
# CONFIG_NFSD_V3 is not set
# CONFIG_NFSD_TCP is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_EXPORTFS=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Distributed Lock Manager
#
CONFIG_DLM=y
CONFIG_DLM_TCP=y
# CONFIG_DLM_SCTP is not set
# CONFIG_DLM_DEBUG is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_DEBUG_PROC_KEYS=y
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_WP512=y
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CAMELLIA=y
#
# Hardware crypto devices
#
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=y
CONFIG_CRC32=y
CONFIG_LIBCRC32C=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
arch/mips/configs/ocelot_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
CONFIG_MOMENCO_OCELOT=y
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/pb1100_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/pb1500_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/pb1550_defconfig
View file @ 192cca6e
......@@ -36,7 +36,6 @@ CONFIG_MIPS_PB1550=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/pnx8550-jbs_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_PNX8550_JBS=y
......
arch/mips/configs/pnx8550-stb810_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/qemu_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/rbhma4200_defconfig
View file @ 192cca6e
......@@ -33,7 +33,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
......
arch/mips/configs/rbhma4500_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/rm200_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/sb1250-swarm_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/sead_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_MIPS_SEAD=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/tb0219_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/tb0226_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/tb0287_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/workpad_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/wrppmc_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_WR_PPMC=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/configs/yosemite_defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/defconfig
View file @ 192cca6e
......@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
......
arch/mips/momentum/ocelot_c/Makefile deleted 100644 → 0
View file @ cfd2afc0
#
# Makefile for Momentum Computer's Ocelot-C and -CS boards.
#
obj-y += cpci-irq.o irq.o platform.o prom.o reset.o \
setup.o uart-irq.o
obj-$(CONFIG_KGDB) += dbg_io.o
arch/mips/momentum/ocelot_c/cpci-irq.c deleted 100644 → 0
View file @ cfd2afc0
/*
* Copyright 2002 Momentum Computer
* Author: mdharm@momenco.com
*
* arch/mips/momentum/ocelot_c/cpci-irq.c
* Interrupt routines for cpci. Interrupt numbers are assigned from
* CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
*
* Note that the high-level software will need to be careful about using
* these interrupts. If this board is asserting a cPCI interrupt, it will
* also see the asserted interrupt. Care must be taken to avoid an
* interrupt flood.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include "ocelot_c_fpga.h"
#define CPCI_IRQ_BASE 8
static inline int ls1bit8(unsigned int x)
{
int b = 7, s;
s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
return b;
}
/* mask off an interrupt -- 0 is enable, 1 is disable */
static inline void mask_cpci_irq(unsigned int irq)
{
uint32_t value;
value = OCELOT_FPGA_READ(INTMASK);
value |= 1 << (irq - CPCI_IRQ_BASE);
OCELOT_FPGA_WRITE(value, INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(INTMASK);
}
/* unmask an interrupt -- 0 is enable, 1 is disable */
static inline void unmask_cpci_irq(unsigned int irq)
{
uint32_t value;
value = OCELOT_FPGA_READ(INTMASK);
value &= ~(1 << (irq - CPCI_IRQ_BASE));
OCELOT_FPGA_WRITE(value, INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(INTMASK);
}
/*
* Interrupt handler for interrupts coming from the FPGA chip.
* It could be built in ethernet ports etc...
*/
void ll_cpci_irq(void)
{
unsigned int irq_src, irq_mask;
/* read the interrupt status registers */
irq_src = OCELOT_FPGA_READ(INTSTAT);
irq_mask = OCELOT_FPGA_READ(INTMASK);
/* mask for just the interrupts we want */
irq_src &= ~irq_mask;
do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
}
struct irq_chip cpci_irq_type = {
.name = "CPCI/FPGA",
.ack = mask_cpci_irq,
.mask = mask_cpci_irq,
.mask_ack = mask_cpci_irq,
.unmask = unmask_cpci_irq,
};
void cpci_irq_init(void)
{
int i;
for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
}
arch/mips/momentum/ocelot_c/dbg_io.c deleted 100644 → 0
View file @ cfd2afc0
#include <asm/serial.h> /* For the serial port location and base baud */
/* --- CONFIG --- */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the second serial port for kdb */
#define BASE OCELOT_SERIAL1_BASE
#define MAX_BAUD OCELOT_BASE_BAUD
/* === END OF CONFIG === */
#define REG_OFFSET 4
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up baud rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
arch/mips/momentum/ocelot_c/irq.c deleted 100644 → 0
View file @ cfd2afc0
/*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
* Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/bitops.h>
#include <linux/mv643xx.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
extern void uart_irq_init(void);
extern void cpci_irq_init(void);
static struct irqaction cascade_fpga = {
no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
};
static struct irqaction cascade_mv64340 = {
no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
};
extern void ll_uart_irq(void);
extern void ll_cpci_irq(void);
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & STATUSF_IP0)
do_IRQ(0);
else if (pending & STATUSF_IP1)
do_IRQ(1);
else if (pending & STATUSF_IP2)
do_IRQ(2);
else if (pending & STATUSF_IP3)
ll_uart_irq();
else if (pending & STATUSF_IP4)
do_IRQ(4);
else if (pending & STATUSF_IP5)
ll_cpci_irq();
else if (pending & STATUSF_IP6)
ll_mv64340_irq();
else if (pending & STATUSF_IP7)
do_IRQ(7);
else
spurious_interrupt();
}
void __init arch_init_irq(void)
{
/*
* Clear all of the interrupts while we change the able around a bit.
* int-handler is not on bootstrap
*/
clear_c0_status(ST0_IM);
mips_cpu_irq_init();
/* set up the cascading interrupts */
setup_irq(3, &cascade_fpga);
setup_irq(5, &cascade_fpga);
setup_irq(6, &cascade_mv64340);
mv64340_irq_init(16);
uart_irq_init();
cpci_irq_init();
}
arch/mips/momentum/ocelot_c/ocelot_c_fpga.h deleted 100644 → 0
View file @ cfd2afc0
/*
* Ocelot-C Board Register Definitions
*
* (C) 2002 Momentum Computer Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*/
#ifndef __OCELOT_C_FPGA_H__
#define __OCELOT_C_FPGA_H__
#ifdef CONFIG_64BIT
#define OCELOT_C_CS0_ADDR (0xfffffffffc000000)
#else
#define OCELOT_C_CS0_ADDR (0xfc000000)
#endif
#define OCELOT_C_REG_BOARDREV 0x0
#define OCELOT_C_REG_FPGA_REV 0x1
#define OCELOT_C_REG_FPGA_TYPE 0x2
#define OCELOT_C_REG_RESET_STATUS 0x3
#define OCELOT_C_REG_BOARD_STATUS 0x4
#define OCELOT_C_REG_CPCI_ID 0x5
#define OCELOT_C_REG_SET 0x6
#define OCELOT_C_REG_CLR 0x7
#define OCELOT_C_REG_EEPROM_MODE 0x9
#define OCELOT_C_REG_INTMASK 0xa
#define OCELOT_C_REG_INTSTAT 0xb
#define OCELOT_C_REG_UART_INTMASK 0xc
#define OCELOT_C_REG_UART_INTSTAT 0xd
#define OCELOT_C_REG_INTSET 0xe
#define OCELOT_C_REG_INTCLR 0xf
#define __FPGA_REG_TO_ADDR(reg) \
((void *) OCELOT_C_CS0_ADDR + OCELOT_C_REG_##reg)
#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
#endif
arch/mips/momentum/ocelot_c/platform.c deleted 100644 → 0
View file @ cfd2afc0
#include <linux/delay.h>
#include <linux/if_ether.h>
#include <linux/ioport.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#include "ocelot_c_fpga.h"
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
.name = "ethernet shared base",
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
MV643XX_ETH_SHARED_REGS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv643xx_eth_shared_device = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
.resource = mv643xx_eth_shared_resources,
};
#define MV_SRAM_BASE 0xfe000000UL
#define MV_SRAM_SIZE (256 * 1024)
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
#define MV64x60_IRQ_ETH_0 48
#define MV64x60_IRQ_ETH_1 49
static struct resource mv64x60_eth0_resources[] = {
[0] = {
.name = "eth0 irq",
.start = MV64x60_IRQ_ETH_0,
.end = MV64x60_IRQ_ETH_0,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth0_pd = {
.port_number = 0,
.tx_sram_addr = MV_SRAM_BASE_ETH0,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
.resource = mv64x60_eth0_resources,
.dev = {
.platform_data = &eth0_pd,
},
};
static struct resource mv64x60_eth1_resources[] = {
[0] = {
.name = "eth1 irq",
.start = MV64x60_IRQ_ETH_1,
.end = MV64x60_IRQ_ETH_1,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth1_pd = {
.port_number = 1,
.tx_sram_addr = MV_SRAM_BASE_ETH1,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
.resource = mv64x60_eth1_resources,
.dev = {
.platform_data = &eth1_pd,
},
};
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
&mv643xx_eth_shared_device,
&eth0_device,
&eth1_device,
/* The third port is not wired up on the Ocelot C */
};
static u8 __init exchange_bit(u8 val, u8 cs)
{
/* place the data */
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
udelay(1);
/* turn the clock on */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
udelay(1);
/* turn the clock off and read-strobe */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
}
static void __init get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
/*
* Copy and increment ethernet MAC address by a small value.
*
* This is useful for systems where the only one MAC address is stored in
* non-volatile memory for multiple ports.
*/
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
unsigned int add)
{
int i;
BUG_ON(add >= 256);
for (i = ETH_ALEN; i >= 0; i--) {
dst[i] = src[i] + add;
add = dst[i] < src[i]; /* compute carry */
}
WARN_ON(add);
}
static int __init mv643xx_eth_add_pds(void)
{
unsigned char mac[ETH_ALEN];
int ret;
get_mac(mac);
eth_mac_add(eth0_pd.mac_addr, mac, 0);
eth_mac_add(eth1_pd.mac_addr, mac, 1);
ret = platform_add_devices(mv643xx_eth_pd_devs,
ARRAY_SIZE(mv643xx_eth_pd_devs));
return ret;
}
device_initcall(mv643xx_eth_add_pds);
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
arch/mips/momentum/ocelot_c/prom.c deleted 100644 → 0
View file @ cfd2afc0
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*
* Based on Ocelot Linux port, which is
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/mv643xx.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/pmon.h>
#include "ocelot_c_fpga.h"
struct callvectors* debug_vectors;
extern unsigned long marvell_base;
extern unsigned int cpu_clock;
const char *get_system_type(void)
{
#ifdef CONFIG_CPU_SR71000
return "Momentum Ocelot-CS";
#else
return "Momentum Ocelot-C";
#endif
}
#ifdef CONFIG_64BIT
unsigned long signext(unsigned long addr)
{
addr &= 0xffffffff;
return (unsigned long)((int)addr);
}
void *get_arg(unsigned long args, int arc)
{
unsigned long ul;
unsigned char *puc, uc;
args += (arc * 4);
ul = (unsigned long)signext(args);
puc = (unsigned char *)ul;
if (puc == 0)
return (void *)0;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
uc = *puc++;
ul = (unsigned long)uc;
uc = *puc++;
ul |= (((unsigned long)uc) << 8);
uc = *puc++;
ul |= (((unsigned long)uc) << 16);
uc = *puc++;
ul |= (((unsigned long)uc) << 24);
#else /* CONFIG_CPU_LITTLE_ENDIAN */
uc = *puc++;
ul = ((unsigned long)uc) << 24;
uc = *puc++;
ul |= (((unsigned long)uc) << 16);
uc = *puc++;
ul |= (((unsigned long)uc) << 8);
uc = *puc++;
ul |= ((unsigned long)uc);
#endif /* CONFIG_CPU_LITTLE_ENDIAN */
ul = signext(ul);
return (void *)ul;
}
char *arg64(unsigned long addrin, int arg_index)
{
unsigned long args;
char *p;
args = signext(addrin);
p = (char *)get_arg(args, arg_index);
return p;
}
#endif /* CONFIG_64BIT */
void __init prom_init(void)
{
int argc = fw_arg0;
char **arg = (char **) fw_arg1;
char **env = (char **) fw_arg2;
struct callvectors *cv = (struct callvectors *) fw_arg3;
int i;
#ifdef CONFIG_64BIT
char *ptr;
printk("prom_init - MIPS64\n");
/* save the PROM vectors for debugging use */
debug_vectors = (struct callvectors *)signext((unsigned long)cv);
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
ptr = (char *)arg64((unsigned long)arg, i);
if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, ptr);
strcat(arcs_cmdline, " ");
}
i = 0;
while (1) {
ptr = (char *)arg64((unsigned long)env, i);
if (! ptr)
break;
if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
marvell_base = simple_strtol(ptr + strlen("gtbase="),
NULL, 16);
if ((marvell_base & 0xffffffff00000000) == 0)
marvell_base |= 0xffffffff00000000;
printk("marvell_base set to 0x%016lx\n", marvell_base);
}
if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
NULL, 10);
printk("cpu_clock set to %d\n", cpu_clock);
}
i++;
}
printk("arcs_cmdline: %s\n", arcs_cmdline);
#else /* CONFIG_64BIT */
/* save the PROM vectors for debugging use */
debug_vectors = cv;
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
>= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
while (*env) {
if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
marvell_base = simple_strtol(*env + strlen("gtbase="),
NULL, 16);
}
if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
cpu_clock = simple_strtol(*env + strlen("cpuclock="),
NULL, 10);
}
env++;
}
#endif /* CONFIG_64BIT */
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_OCELOT_C;
#ifndef CONFIG_64BIT
debug_vectors->printf("Booting Linux kernel...\n");
#endif
}
void __init prom_free_prom_memory(void)
{
}
arch/mips/momentum/ocelot_c/reset.c deleted 100644 → 0
View file @ cfd2afc0
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 2001 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* Copyright (C) 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <linux/delay.h>
void momenco_ocelot_restart(char *command)
{
/* base address of timekeeper portion of part */
void *nvram = (void *)
#ifdef CONFIG_64BIT
0xfffffffffc807000;
#else
0xfc807000;
#endif
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
mdelay(100+(1000/16));
/* if the watchdog fails for some reason, let people know */
printk(KERN_NOTICE "Watchdog reset failed\n");
}
void momenco_ocelot_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
}
void momenco_ocelot_power_off(void)
{
momenco_ocelot_halt();
}
arch/mips/momentum/ocelot_c/setup.c deleted 100644 → 0
View file @ cfd2afc0
/*
* BRIEF MODULE DESCRIPTION
* Momentum Computer Ocelot-C and -CS board dependent boot routines
*
* Copyright (C) 1996, 1997, 2001 Ralf Baechle
* Copyright (C) 2000 RidgeRun, Inc.
* Copyright (C) 2001 Red Hat, Inc.
* Copyright (C) 2002 Momentum Computer
*
* Author: Matthew Dharm, Momentum Computer
* mdharm@momenco.com
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
#include <linux/mv643xx.h>
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/marvell.h>
#include <linux/bootmem.h>
#include <linux/blkdev.h>
#include "ocelot_c_fpga.h"
unsigned long marvell_base;
unsigned int cpu_clock;
/* These functions are used for rebooting or halting the machine*/
extern void momenco_ocelot_restart(char *command);
extern void momenco_ocelot_halt(void);
extern void momenco_ocelot_power_off(void);
void momenco_time_init(void);
static char reset_reason;
void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
static unsigned long ENTRYLO(unsigned long paddr)
{
return ((paddr & PAGE_MASK) |
(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
_CACHE_UNCACHED)) >> 6;
}
/* setup code for a handoff from a version 2 PMON 2000 PROM */
void PMON_v2_setup(void)
{
/* Some wired TLB entries for the MV64340 and perhiperals. The
MV64340 is going to be hit on every IRQ anyway - there's
absolutely no point in letting it be a random TLB entry, as
it'll just cause needless churning of the TLB. And we use
the other half for the serial port, which is just a PITA
otherwise :)
Device Physical Virtual
MV64340 Internal Regs 0xf4000000 0xf4000000
Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
NVRAM (CS1) 0xfc800000 0xfc800000
UARTs (CS2) 0xfd000000 0xfd000000
Internal SRAM 0xfe000000 0xfe000000
M-Systems DOC (CS3) 0xff000000 0xff000000
*/
printk("PMON_v2_setup\n");
#ifdef CONFIG_64BIT
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
/* fpga, rtc, and uart */
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
/* m-sys and internal SRAM */
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
marvell_base = 0xfffffffff4000000;
#else
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
/* fpga, rtc, and uart */
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
/* m-sys and internal SRAM */
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
marvell_base = 0xf4000000;
#endif
}
unsigned long m48t37y_get_time(void)
{
#ifdef CONFIG_64BIT
unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
#else
unsigned char* rtc_base = (unsigned char*)0xfc800000;
#endif
unsigned int year, month, day, hour, min, sec;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* stop the update */
rtc_base[0x7ff8] = 0x40;
year = BCD2BIN(rtc_base[0x7fff]);
year += BCD2BIN(rtc_base[0x7ff1]) * 100;
month = BCD2BIN(rtc_base[0x7ffe]);
day = BCD2BIN(rtc_base[0x7ffd]);
hour = BCD2BIN(rtc_base[0x7ffb]);
min = BCD2BIN(rtc_base[0x7ffa]);
sec = BCD2BIN(rtc_base[0x7ff9]);
/* start the update */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
int m48t37y_set_time(unsigned long sec)
{
#ifdef CONFIG_64BIT
unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
#else
unsigned char* rtc_base = (unsigned char*)0xfc800000;
#endif
struct rtc_time tm;
unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
rtc_base[0x7ff8] = 0x80;
/* year */
rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
/* month */
rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
/* day */
rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
/* hour/min/sec */
rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
/* day of week -- not really used, but let's keep it up-to-date */
rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
/* disable writing */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(7, irq);
}
void momenco_time_init(void)
{
#ifdef CONFIG_CPU_SR71000
mips_hpt_frequency = cpu_clock;
#elif defined(CONFIG_CPU_RM7000)
mips_hpt_frequency = cpu_clock / 2;
#else
#error Unknown CPU for this board
#endif
printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
rtc_mips_get_time = m48t37y_get_time;
rtc_mips_set_time = m48t37y_set_time;
}
void __init plat_mem_setup(void)
{
unsigned int tmpword;
board_time_init = momenco_time_init;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
pm_power_off = momenco_ocelot_power_off;
/*
* initrd_start = (unsigned long)ocelot_initrd_start;
* initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
* initrd_below_start_ok = 1;
*/
/* do handoff reconfiguration */
PMON_v2_setup();
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
do {}
while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
do {}
while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE(0x80, CLR);
tmpword = OCELOT_FPGA_READ(BOARDREV);
#ifdef CONFIG_CPU_SR71000
if (tmpword < 26)
printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
tmpword);
#else
if (tmpword < 26)
printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
tmpword);
#endif
tmpword = OCELOT_FPGA_READ(FPGA_REV);
printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = OCELOT_FPGA_READ(RESET_STATUS);
printk("Reset reason: 0x%x\n", tmpword);
switch (tmpword) {
case 0x1:
printk(" - Power-up reset\n");
break;
case 0x2:
printk(" - Push-button reset\n");
break;
case 0x4:
printk(" - cPCI bus reset\n");
break;
case 0x8:
printk(" - Watchdog reset\n");
break;
case 0x10:
printk(" - Software reset\n");
break;
default:
printk(" - Unknown reset cause\n");
}
reset_reason = tmpword;
OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
tmpword = OCELOT_FPGA_READ(CPCI_ID);
printk("cPCI ID register: 0x%02x\n", tmpword);
printk(" - Slot number: %d\n", tmpword & 0x1f);
printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
printk("Board Status register: 0x%02x\n", tmpword);
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
switch(tmpword &3) {
case 3:
/* 512MiB */
add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
break;
case 2:
/* 256MiB */
add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
break;
case 1:
/* 128MiB */
add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
break;
case 0:
/* 1GiB -- needs CONFIG_HIGHMEM */
add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
break;
}
}
/*
* This needs to be one of the first initcalls, because no I/O port access
* can work before this
*/
static int io_base_ioremap(void)
{
void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
if (!io_remap_range)
panic("Could not ioremap I/O port range");
set_io_port_base((unsigned long) io_remap_range);
return 0;
}
module_init(io_base_ioremap);
arch/mips/momentum/ocelot_c/uart-irq.c deleted 100644 → 0
View file @ cfd2afc0
/*
* Copyright 2002 Momentum Computer
* Author: mdharm@momenco.com
*
* arch/mips/momentum/ocelot_c/uart-irq.c
* Interrupt routines for UARTs. Interrupt numbers are assigned from
* 80 to 81 (2 interrupt sources).
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/irq.h>
#include "ocelot_c_fpga.h"
static inline int ls1bit8(unsigned int x)
{
int b = 7, s;
s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
return b;
}
/* mask off an interrupt -- 0 is enable, 1 is disable */
static inline void mask_uart_irq(unsigned int irq)
{
uint8_t value;
value = OCELOT_FPGA_READ(UART_INTMASK);
value |= 1 << (irq - 74);
OCELOT_FPGA_WRITE(value, UART_INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(UART_INTMASK);
}
/* unmask an interrupt -- 0 is enable, 1 is disable */
static inline void unmask_uart_irq(unsigned int irq)
{
uint8_t value;
value = OCELOT_FPGA_READ(UART_INTMASK);
value &= ~(1 << (irq - 74));
OCELOT_FPGA_WRITE(value, UART_INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(UART_INTMASK);
}
/*
* Interrupt handler for interrupts coming from the FPGA chip.
*/
void ll_uart_irq(void)
{
unsigned int irq_src, irq_mask;
/* read the interrupt status registers */
irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
/* mask for just the interrupts we want */
irq_src &= ~irq_mask;
do_IRQ(ls1bit8(irq_src) + 74);
}
struct irq_chip uart_irq_type = {
.name = "UART/FPGA",
.ack = mask_uart_irq,
.mask = mask_uart_irq,
.mask_ack = mask_uart_irq,
.unmask = unmask_uart_irq,
};
void uart_irq_init(void)
{
set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
}
arch/mips/pci/Makefile
View file @ 192cca6e
......@@ -31,7 +31,6 @@ obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o
obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
pci-yosemite.o
obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o
......
arch/mips/pci/fixup-ocelot-c.c deleted 100644 → 0
View file @ cfd2afc0
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Based on work for the Linux port to the Ocelot board, which is
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/momentum/ocelot_g/pci.c
* Board-specific PCI routines for mv64340 controller.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int bus = dev->bus->number;
if (bus == 0 && slot == 1)
return 2; /* PCI-X A */
if (bus == 1 && slot == 1)
return 12; /* PCI-X B */
if (bus == 1 && slot == 2)
return 4; /* PCI B */
return 0;
panic("Whooops in pcibios_map_irq");
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
arch/mips/pci/pci-ocelot-c.c deleted 100644 → 0
View file @ cfd2afc0
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org)
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/mv643xx.h>
#include <linux/init.h>
#include <asm/marvell.h>
/*
* We assume the address ranges have already been setup appropriately by
* the firmware. PMON in case of the Ocelot C does that.
*/
static struct resource mv_pci_io_mem0_resource = {
.name = "MV64340 PCI0 IO MEM",
.flags = IORESOURCE_IO
};
static struct resource mv_pci_mem0_resource = {
.name = "MV64340 PCI0 MEM",
.flags = IORESOURCE_MEM
};
static struct mv_pci_controller mv_bus0_controller = {
.pcic = {
.pci_ops = &mv_pci_ops,
.mem_resource = &mv_pci_mem0_resource,
.io_resource = &mv_pci_io_mem0_resource,
},
.config_addr = MV64340_PCI_0_CONFIG_ADDR,
.config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
};
static uint32_t mv_io_base, mv_io_size;
static void mv64340_pci0_init(void)
{
uint32_t mem0_base, mem0_size;
uint32_t io_base, io_size;
io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
mv_pci_io_mem0_resource.start = 0;
mv_pci_io_mem0_resource.end = io_size - 1;
mv_pci_mem0_resource.start = mem0_base;
mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
mv_bus0_controller.pcic.mem_offset = mem0_base;
mv_bus0_controller.pcic.io_offset = 0;
ioport_resource.end = io_size - 1;
register_pci_controller(&mv_bus0_controller.pcic);
mv_io_base = io_base;
mv_io_size = io_size;
}
static struct resource mv_pci_io_mem1_resource = {
.name = "MV64340 PCI1 IO MEM",
.flags = IORESOURCE_IO
};
static struct resource mv_pci_mem1_resource = {
.name = "MV64340 PCI1 MEM",
.flags = IORESOURCE_MEM
};
static struct mv_pci_controller mv_bus1_controller = {
.pcic = {
.pci_ops = &mv_pci_ops,
.mem_resource = &mv_pci_mem1_resource,
.io_resource = &mv_pci_io_mem1_resource,
},
.config_addr = MV64340_PCI_1_CONFIG_ADDR,
.config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
};
static __init void mv64340_pci1_init(void)
{
uint32_t mem0_base, mem0_size;
uint32_t io_base, io_size;
io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
/*
* Here we assume the I/O window of second bus to be contiguous with
* the first. A gap is no problem but would waste address space for
* remapping the port space.
*/
mv_pci_io_mem1_resource.start = mv_io_size;
mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
mv_pci_mem1_resource.start = mem0_base;
mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
mv_bus1_controller.pcic.mem_offset = mem0_base;
mv_bus1_controller.pcic.io_offset = 0;
ioport_resource.end = io_base + io_size -mv_io_base - 1;
register_pci_controller(&mv_bus1_controller.pcic);
mv_io_size = io_base + io_size - mv_io_base;
}
static __init int __init ocelot_c_pci_init(void)
{
unsigned long io_v_base;
uint32_t enable;
enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
/*
* We require at least one enabled I/O or PCI memory window or we
* will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
*/
if (enable & (0x01 << 9) || enable & (0x01 << 10))
mv64340_pci0_init();
if (enable & (0x01 << 14) || enable & (0x01 << 15))
mv64340_pci1_init();
if (mv_io_size) {
io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
if (!io_v_base)
panic("Could not ioremap I/O port range");
set_io_port_base(io_v_base);
}
return 0;
}
arch_initcall(ocelot_c_pci_init);
drivers/mtd/devices/docprobe.c
View file @ 192cca6e
......@@ -84,7 +84,7 @@ static unsigned long __initdata doc_locations[] = {
#elif defined(CONFIG_MOMENCO_OCELOT)
0x2f000000,
0xff000000,
#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C)
#elif defined(CONFIG_MOMENCO_OCELOT_G)
0xff000000,
##else
#warning Unknown architecture for DiskOnChip. No default probe locations defined
......
drivers/mtd/nand/diskonchip.c
View file @ 192cca6e
......@@ -59,7 +59,7 @@ static unsigned long __initdata doc_locations[] = {
#elif defined(CONFIG_MOMENCO_OCELOT)
0x2f000000,
0xff000000,
#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C)
#elif defined(CONFIG_MOMENCO_OCELOT_G)
0xff000000,
#else
#warning Unknown architecture for DiskOnChip. No default probe locations defined
......
drivers/net/Kconfig
View file @ 192cca6e
......@@ -2307,7 +2307,7 @@ config UGETH_TX_ON_DEMAND
config MV643XX_ETH
tristate "MV-643XX Ethernet support"
depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MV64X60 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
depends on MOMENCO_JAGUAR_ATX || MV64360 || MV64X60 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
select MII
help
This driver supports the gigabit Ethernet on the Marvell MV643XX
......
include/asm-mips/bootinfo.h
View file @ 192cca6e
......@@ -114,7 +114,7 @@
#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */
#define MACH_MOMENCO_OCELOT 0
#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */
#define MACH_MOMENCO_OCELOT_C 2
#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */
#define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */
#define MACH_MOMENCO_OCELOT_3 4
......
include/asm-mips/serial.h
View file @ 192cca6e
......@@ -97,31 +97,6 @@
#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
#endif
#ifdef CONFIG_MOMENCO_OCELOT_C
/* Ordinary NS16552 duart with a 20MHz crystal. */
#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
#define OCELOT_C_SERIAL1_IRQ 80
#define OCELOT_C_SERIAL1_BASE 0xfd000020
#define OCELOT_C_SERIAL2_IRQ 81
#define OCELOT_C_SERIAL2_BASE 0xfd000000
#define _OCELOT_C_SERIAL_INIT(int, base) \
{ .baud_base = OCELOT_C_BASE_BAUD, \
.irq = (int), \
.flags = STD_COM_FLAGS, \
.iomem_base = (u8 *) base, \
.iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM \
}
#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
#else
#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
#endif
#ifdef CONFIG_DDB5477
#include <asm/ddb5xxx/ddb5477.h>
#define DDB5477_SERIAL_PORT_DEFNS \
......@@ -151,7 +126,6 @@
IP32_SERIAL_PORT_DEFNS \
JAZZ_SERIAL_PORT_DEFNS \
STD_SERIAL_PORT_DEFNS \
MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
......
include/asm-mips/war.h
View file @ 192cca6e
......@@ -185,8 +185,8 @@
#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \
defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \
defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \
defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \
defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
defined(CONFIG_WR_PPMC)
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif
......
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