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Commit 19491c22 authored by Arnd Bergmann's avatar Arnd Bergmann
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ARM: omap1: dma: remove omap2 specific bits 

No part of plat-omap/dma.c is called on omap2 any more, so
anything omap2 specific in here can simply be removed.
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 52ef8efc
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Showing with 55 additions and 162 deletions
arch/arm/plat-omap/dma.c
View file @ 19491c22
......@@ -34,11 +34,9 @@
#include <linux/omap-dma.h>
#ifdef CONFIG_ARCH_OMAP1
#include <mach/hardware.h>
#include <linux/soc/ti/omap1-io.h>
#include <linux/soc/ti/omap1-soc.h>
#endif
/*
* MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
......@@ -51,16 +49,7 @@
#undef DEBUG
#ifndef CONFIG_ARCH_OMAP1
enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
};
enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
#endif
#define OMAP_DMA_ACTIVE 0x01
#define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
......@@ -94,13 +83,9 @@ static inline void omap_disable_channel_irq(int lch)
/* disable channel interrupts */
p->dma_write(0, CICR, lch);
/* Clear CSR */
if (dma_omap1())
p->dma_read(CSR, lch);
else
p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
}
#ifdef CONFIG_ARCH_OMAP1
static inline void set_gdma_dev(int req, int dev)
{
u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
......@@ -112,11 +97,6 @@ static inline void set_gdma_dev(int req, int dev)
l |= (dev - 1) << shift;
omap_writel(l, reg);
}
#else
#define set_gdma_dev(req, dev) do {} while (0)
#define omap_readl(reg) 0
#define omap_writel(val, reg) do {} while (0)
#endif
#ifdef CONFIG_ARCH_OMAP1
void omap_set_dma_priority(int lch, int dst_port, int priority)
......@@ -181,15 +161,13 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
int dma_trigger, int src_or_dst_synch)
{
u32 l;
u16 ccr;
l = p->dma_read(CSDP, lch);
l &= ~0x03;
l |= data_type;
p->dma_write(l, CSDP, lch);
if (dma_omap1()) {
u16 ccr;
ccr = p->dma_read(CCR, lch);
ccr &= ~(1 << 5);
if (sync_mode == OMAP_DMA_SYNC_FRAME)
......@@ -201,39 +179,6 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
if (sync_mode == OMAP_DMA_SYNC_BLOCK)
ccr |= 1 << 2;
p->dma_write(ccr, CCR2, lch);
}
if (dma_omap2plus() && dma_trigger) {
u32 val;
val = p->dma_read(CCR, lch);
/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
val &= ~((1 << 23) | (3 << 19) | 0x1f);
val |= (dma_trigger & ~0x1f) << 14;
val |= dma_trigger & 0x1f;
if (sync_mode & OMAP_DMA_SYNC_FRAME)
val |= 1 << 5;
else
val &= ~(1 << 5);
if (sync_mode & OMAP_DMA_SYNC_BLOCK)
val |= 1 << 18;
else
val &= ~(1 << 18);
if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
val &= ~(1 << 24); /* dest synch */
val |= (1 << 23); /* Prefetch */
} else if (src_or_dst_synch) {
val |= 1 << 24; /* source synch */
} else {
val &= ~(1 << 24); /* dest synch */
}
p->dma_write(val, CCR, lch);
}
p->dma_write(elem_count, CEN, lch);
p->dma_write(frame_count, CFN, lch);
}
......@@ -241,7 +186,7 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
{
if (dma_omap1() && !dma_omap15xx()) {
if (!dma_omap15xx()) {
u32 l;
l = p->dma_read(LCH_CTRL, lch);
......@@ -258,15 +203,12 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
int src_ei, int src_fi)
{
u32 l;
if (dma_omap1()) {
u16 w;
w = p->dma_read(CSDP, lch);
w &= ~(0x1f << 2);
w |= src_port << 2;
p->dma_write(w, CSDP, lch);
}
l = p->dma_read(CCR, lch);
l &= ~(0x03 << 12);
......@@ -304,26 +246,15 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
case OMAP_DMA_DATA_BURST_DIS:
break;
case OMAP_DMA_DATA_BURST_4:
if (dma_omap2plus())
burst = 0x1;
else
burst = 0x2;
break;
case OMAP_DMA_DATA_BURST_8:
if (dma_omap2plus()) {
burst = 0x2;
break;
}
/*
* not supported by current hardware on OMAP1
* w |= (0x03 << 7);
*/
fallthrough;
case OMAP_DMA_DATA_BURST_16:
if (dma_omap2plus()) {
burst = 0x3;
break;
}
/* OMAP1 don't support burst 16 */
fallthrough;
default:
......@@ -342,12 +273,10 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
{
u32 l;
if (dma_omap1()) {
l = p->dma_read(CSDP, lch);
l &= ~(0x1f << 9);
l |= dest_port << 9;
p->dma_write(l, CSDP, lch);
}
l = p->dma_read(CCR, lch);
l &= ~(0x03 << 14);
......@@ -385,22 +314,12 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
case OMAP_DMA_DATA_BURST_DIS:
break;
case OMAP_DMA_DATA_BURST_4:
if (dma_omap2plus())
burst = 0x1;
else
burst = 0x2;
break;
case OMAP_DMA_DATA_BURST_8:
if (dma_omap2plus())
burst = 0x2;
else
burst = 0x3;
break;
case OMAP_DMA_DATA_BURST_16:
if (dma_omap2plus()) {
burst = 0x3;
break;
}
/* OMAP1 don't support burst 16 */
fallthrough;
default:
......@@ -416,10 +335,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
static inline void omap_enable_channel_irq(int lch)
{
/* Clear CSR */
if (dma_omap1())
p->dma_read(CSR, lch);
else
p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
/* Enable some nice interrupts. */
p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
......@@ -437,7 +353,6 @@ static inline void enable_lnk(int lch)
l = p->dma_read(CLNK_CTRL, lch);
if (dma_omap1())
l &= ~(1 << 14);
/* Set the ENABLE_LNK bits */
......@@ -456,15 +371,8 @@ static inline void disable_lnk(int lch)
/* Disable interrupts */
omap_disable_channel_irq(lch);
if (dma_omap1()) {
/* Set the STOP_LNK bit */
l |= 1 << 14;
}
if (dma_omap2plus()) {
/* Clear the ENABLE_LNK bit */
l &= ~(1 << 15);
}
p->dma_write(l, CLNK_CTRL, lch);
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
......@@ -508,7 +416,6 @@ int omap_request_dma(int dev_id, const char *dev_name,
chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
if (dma_omap1())
chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
if (dma_omap16xx()) {
......@@ -522,7 +429,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
* id.
*/
p->dma_write(dev_id | (1 << 10), CCR, free_ch);
} else if (dma_omap1()) {
} else {
p->dma_write(dev_id, CCR, free_ch);
}
......@@ -739,7 +646,6 @@ dma_addr_t omap_get_dma_src_pos(int lch)
offset = p->dma_read(CSSA, lch);
}
if (dma_omap1())
offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
return offset;
......@@ -778,7 +684,6 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
offset = p->dma_read(CDSA, lch);
}
if (dma_omap1())
offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
return offset;
......@@ -796,7 +701,6 @@ int omap_dma_running(void)
{
int lch;
if (dma_omap1())
if (omap_lcd_dma_running())
return 1;
......@@ -809,8 +713,6 @@ int omap_dma_running(void)
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_ARCH_OMAP1
static int omap1_dma_handle_ch(int ch)
{
u32 csr;
......@@ -863,10 +765,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
return handled ? IRQ_HANDLED : IRQ_NONE;
}
#else
#define omap1_dma_irq_handler NULL
#endif
struct omap_system_dma_plat_info *omap_get_plat_info(void)
{
return p;
......@@ -912,7 +810,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
if (ch >= 6 && enable_1510_mode)
continue;
if (dma_omap1()) {
/*
* request_irq() doesn't like dev_id (ie. ch) being
* zero, so we have to kludge around this.
......@@ -935,7 +832,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
if (ret != 0)
goto exit_dma_irq_fail;
}
}
/* reserve dma channels 0 and 1 in high security devices on 34xx */
if (d->dev_caps & HS_CHANNELS_RESERVED) {
......@@ -954,9 +850,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
{
int dma_irq, irq_rel = 0;
if (dma_omap2plus())
return 0;
for ( ; irq_rel < dma_chan_count; irq_rel++) {
dma_irq = platform_get_irq(pdev, irq_rel);
free_irq(dma_irq, (void *)(irq_rel + 1));
......
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