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Commit 1a4a561b authored by Leo Chen's avatar Leo Chen Committed by Russell King
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ARM: 5658/1: bcmring: add csp dmac header files 

add csp dmac header files
Signed-off-by: default avatarLeo Chen <leochen@broadcom.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 638ee2db
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arch/arm/mach-bcmring/include/csp/dmacHw.h 0 → 100644
View file @ 1a4a561b
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw.h
*
* @brief API definitions for low level DMA controller driver
*
*/
/****************************************************************************/
#ifndef _DMACHW_H
#define _DMACHW_H
#include <stddef.h>
#include <csp/stdint.h>
#include <mach/csp/dmacHw_reg.h>
/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
System specific channel ID should be defined as follows
For example:
#include <dmacHw.h>
...
#define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5)
#define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0)
#define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1)
#define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3)
#define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4)
...
#define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4)
#define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5)
#define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6)
...
*/
#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c)
typedef enum {
dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */
dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */
dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */
dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */
dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */
dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */
dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */
dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */
} dmacHw_CHANNEL_PRIORITY_e;
/* Source destination master interface */
typedef enum {
dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */
dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */
dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */
dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */
} dmacHw_MASTER_INTERFACE_e;
typedef enum {
dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */
dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */
dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */
dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */
} dmacHw_TRANSACTION_WIDTH_e;
typedef enum {
dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */
dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */
dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
} dmacHw_BURST_WIDTH_e;
typedef enum {
dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */
dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */
} dmacHw_TRANSFER_TYPE_e;
typedef enum {
dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */
dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */
dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */
} dmacHw_TRANSFER_MODE_e;
typedef enum {
dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */
dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */
dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */
dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */
dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */
dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */
} dmacHw_ADDRESS_UPDATE_MODE_e;
typedef enum {
dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */
dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */
} dmacHw_FLOW_CONTROL_e;
typedef enum {
dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */
dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */
dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */
} dmacHw_TRANSFER_STATUS_e;
typedef enum {
dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */
dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
} dmacHw_INTERRUPT_e;
typedef enum {
dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */
dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */
dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */
dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */
} dmacHw_INTERRUPT_STATUS_e;
typedef enum {
dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */
dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */
dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */
dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */
dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */
} dmacHw_CONTROLLER_ATTRIB_e;
typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */
typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using
"dmacHw_MAKE_CHANNEL_ID" macro
*/
/* DMA channel configuration parameters */
typedef struct {
uint32_t srcPeripheralPort; /* Source peripheral port */
uint32_t dstPeripheralPort; /* Destination peripheral port */
uint32_t srcStatusRegisterAddress; /* Source status register address */
uint32_t dstStatusRegisterAddress; /* Destination status register address of type */
uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */
uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */
uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */
uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor.
0 = Maximum possible.
*/
dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */
dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */
dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */
dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */
dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */
dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */
dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */
dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */
dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */
dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */
dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */
dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */
dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */
} dmacHw_CONFIG_t;
/****************************************************************************/
/**
* @brief Initializes DMA
*
* This function initializes DMA CSP driver
*
* @note
* Must be called before using any DMA channel
*/
/****************************************************************************/
void dmacHw_initDma(void);
/****************************************************************************/
/**
* @brief Exit function for DMA
*
* This function isolates DMA from the system
*
*/
/****************************************************************************/
void dmacHw_exitDma(void);
/****************************************************************************/
/**
* @brief Gets a handle to a DMA channel
*
* This function returns a handle, representing a control block of a particular DMA channel
*
* @return -1 - On Failure
* handle - On Success, representing a channel control block
*
* @note
* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
*/
/****************************************************************************/
dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
);
/****************************************************************************/
/**
* @brief Initializes a DMA channel for use
*
* This function initializes and resets a DMA channel for use
*
* @return -1 - On Failure
* 0 - On Success
*
* @note
* None
*/
/****************************************************************************/
int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Estimates number of descriptor needed to perform certain DMA transfer
*
*
* @return On failure : -1
* On success : Number of descriptor count
*
*
*/
/****************************************************************************/
int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
size_t dataLen /* [ IN ] Data length in bytes */
);
/****************************************************************************/
/**
* @brief Initializes descriptor ring
*
* This function will initializes the descriptor ring of a DMA channel
*
*
* @return -1 - On failure
* 0 - On success
* @note
* - "len" parameter should be obtained from "dmacHw_descriptorLen"
* - Descriptor buffer MUST be 32 bit aligned and uncached as it
* is accessed by ARM and DMA
*/
/****************************************************************************/
int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
uint32_t len, /* [ IN ] Size of the pBuf */
uint32_t num /* [ IN ] Number of descriptor in the ring */
);
/****************************************************************************/
/**
* @brief Finds amount of memory required to form a descriptor ring
*
*
* @return Number of bytes required to form a descriptor ring
*
*
* @note
* None
*/
/****************************************************************************/
uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
);
/****************************************************************************/
/**
* @brief Configure DMA channel
*
* @return 0 : On success
* -1 : On failure
*/
/****************************************************************************/
int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
);
/****************************************************************************/
/**
* @brief Set descriptors for known data length
*
* When DMA has to work as a flow controller, this function prepares the
* descriptor chain to transfer data
*
* from:
* - Memory to memory
* - Peripheral to memory
* - Memory to Peripheral
* - Peripheral to Peripheral
*
* @return -1 - On failure
* 0 - On success
*
*/
/****************************************************************************/
int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
size_t dataLen /* [ IN ] Length in bytes */
);
/****************************************************************************/
/**
* @brief Indicates whether DMA transfer is in progress or completed
*
* @return DMA transfer status
* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
*
*/
/****************************************************************************/
dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Set descriptor carrying control information
*
* This function will be used to send specific control information to the device
* using the DMA channel
*
*
* @return -1 - On failure
* 0 - On success
*
* @note
* None
*/
/****************************************************************************/
int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
uint32_t ctlAddress, /* [ IN ] Address of the device control register */
uint32_t control /* [ IN ] Device control information */
);
/****************************************************************************/
/**
* @brief Read data DMA transferred to memory
*
* This function will read data that has been DMAed to memory while transfering from:
* - Memory to memory
* - Peripheral to memory
*
* @return 0 - No more data is available to read
* 1 - More data might be available to read
*
*/
/****************************************************************************/
int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
void **ppBbuf, /* [ OUT ] Data received */
size_t *pLlen /* [ OUT ] Length of the data received */
);
/****************************************************************************/
/**
* @brief Prepares descriptor ring, when source peripheral working as a flow controller
*
* This function will form the descriptor ring by allocating buffers, when source peripheral
* has to work as a flow controller to transfer data from:
* - Peripheral to memory.
*
* @return -1 - On failure
* 0 - On success
*
*
* @note
* None
*/
/****************************************************************************/
int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
uint32_t srcAddr, /* [ IN ] Source peripheral address */
void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
int num /* [ IN ] Number of descriptor to set */
);
/****************************************************************************/
/**
* @brief Program channel register to initiate transfer
*
* @return void
*
*
* @note
* - Descriptor buffer MUST ALWAYS be flushed before calling this function
* - This function should also be called from ISR to program the channel with
* pending descriptors
*/
/****************************************************************************/
void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor /* [ IN ] Descriptor buffer */
);
/****************************************************************************/
/**
* @brief Resets descriptor control information
*
* @return void
*/
/****************************************************************************/
void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
);
/****************************************************************************/
/**
* @brief Program channel register to stop transfer
*
* Ensures the channel is not doing any transfer after calling this function
*
* @return void
*
*/
/****************************************************************************/
void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Check the existance of pending descriptor
*
* This function confirmes if there is any pending descriptor in the chain
* to program the channel
*
* @return 1 : Channel need to be programmed with pending descriptor
* 0 : No more pending descriptor to programe the channel
*
* @note
* - This function should be called from ISR in case there are pending
* descriptor to program the channel.
*
* Example:
*
* dmac_isr ()
* {
* ...
* if (dmacHw_descriptorPending (handle))
* {
* dmacHw_initiateTransfer (handle);
* }
* }
*
*/
/****************************************************************************/
uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
void *pDescriptor /* [ IN ] Descriptor buffer */
);
/****************************************************************************/
/**
* @brief Deallocates source or destination memory, allocated
*
* This function can be called to deallocate data memory that was DMAed successfully
*
* @return -1 - On failure
* 0 - On success
*
* @note
* This function will be called ONLY, when source OR destination address is pointing
* to dynamic memory
*/
/****************************************************************************/
int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
);
/****************************************************************************/
/**
* @brief Clears the interrupt
*
* This function clears the DMA channel specific interrupt
*
* @return N/A
*
* @note
* Must be called under the context of ISR
*/
/****************************************************************************/
void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Returns the cause of channel specific DMA interrupt
*
* This function returns the cause of interrupt
*
* @return Interrupt status, each bit representing a specific type of interrupt
* of type dmacHw_INTERRUPT_STATUS_e
* @note
* This function should be called under the context of ISR
*/
/****************************************************************************/
dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Indentifies a DMA channel causing interrupt
*
* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
*
* @return NULL : No channel causing DMA interrupt
* ! NULL : Handle to a channel causing DMA interrupt
* @note
* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
*/
/****************************************************************************/
dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
/****************************************************************************/
/**
* @brief Sets channel specific user data
*
* This function associates user data to a specif DMA channel
*
*/
/****************************************************************************/
void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
void *userData /* [ IN ] User data */
);
/****************************************************************************/
/**
* @brief Gets channel specific user data
*
* This function returns user data specific to a DMA channel
*
* @return user data
*/
/****************************************************************************/
void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Displays channel specific registers and other control parameters
*
*
* @return void
*
* @note
* None
*/
/****************************************************************************/
void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
void *pDescriptor, /* [ IN ] Descriptor buffer */
int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
);
/****************************************************************************/
/**
* @brief Provides DMA controller attributes
*
*
* @return DMA controller attributes
*
* @note
* None
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
);
#endif /* _DMACHW_H */
arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h 0 → 100644
View file @ 1a4a561b
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw_priv.h
*
* @brief Private Definitions for low level DMA driver
*
*/
/****************************************************************************/
#ifndef _DMACHW_PRIV_H
#define _DMACHW_PRIV_H
#include <csp/stdint.h>
/* Data type for DMA Link List Item */
typedef struct {
uint32_t sar; /* Source Adress Register.
Address must be aligned to CTLx.SRC_TR_WIDTH. */
uint32_t dar; /* Destination Address Register.
Address must be aligned to CTLx.DST_TR_WIDTH. */
uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
Address MUST be aligned to a 32-bit boundary. */
dmacHw_REG64_t ctl; /* Control Register. 64 bits */
uint32_t sstat; /* Source Status Register */
uint32_t dstat; /* Destination Status Register */
uint32_t devCtl; /* Device specific control information */
uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
} dmacHw_DESC_t;
/*
* Descriptor ring pointers
*/
typedef struct {
int num; /* Number of link items */
dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
} dmacHw_DESC_RING_t;
/*
* DMA channel control block
*/
typedef struct {
uint32_t module; /* DMA controller module (0-1) */
uint32_t channel; /* DMA channel (0-7) */
volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
void *userData; /* Channel specifc user data */
} dmacHw_CBLK_t;
#define dmacHw_ASSERT(a) if (!(a)) while (1)
#define dmacHw_MAX_CHANNEL_COUNT 16
#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
#define dmacHw_MAX_BLOCKSIZE 4064
#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
/****************************************************************************/
/**
* @brief Get next available transaction width
*
*
* @return On sucess : Next avail able transaction width
* On failure : dmacHw_TRANSACTION_WIDTH_8
*
* @note
* None
*/
/****************************************************************************/
static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
) {
if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
}
/* Default return */
return dmacHw_SRC_TRANSACTION_WIDTH_8;
}
/****************************************************************************/
/**
* @brief Get number of bytes per transaction
*
* @return Number of bytes per transaction
*
*
* @note
* None
*/
/****************************************************************************/
static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
) {
int width = 1;
switch (tw) {
case dmacHw_SRC_TRANSACTION_WIDTH_8:
width = 1;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_16:
case dmacHw_DST_TRANSACTION_WIDTH_16:
width = 2;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_32:
case dmacHw_DST_TRANSACTION_WIDTH_32:
width = 4;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_64:
case dmacHw_DST_TRANSACTION_WIDTH_64:
width = 8;
break;
default:
dmacHw_ASSERT(0);
}
/* Default transaction width */
return width;
}
#endif /* _DMACHW_PRIV_H */
arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h 0 → 100644
View file @ 1a4a561b
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw_reg.h
*
* @brief Definitions for low level DMA registers
*
*/
/****************************************************************************/
#ifndef _DMACHW_REG_H
#define _DMACHW_REG_H
#include <csp/stdint.h>
#include <mach/csp/mm_io.h>
/* Data type for 64 bit little endian register */
typedef struct {
volatile uint32_t lo; /* Lower 32 bit in little endian mode */
volatile uint32_t hi; /* Upper 32 bit in little endian mode */
} dmacHw_REG64_t;
/* Data type representing DMA channel registers */
typedef struct {
dmacHw_REG64_t ChannelSar; /* Source Adress Register. 64 bits (upper 32 bits are reserved)
Address must be aligned to CTLx.SRC_TR_WIDTH.
*/
dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
Address must be aligned to CTLx.DST_TR_WIDTH.
*/
dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved)
LLP contains the pointer to the next LLI for block chaining using linked lists.
If LLPis set to 0x0, then transfers using linked lists are not enabled.
Address MUST be aligned to a 32-bit boundary.
*/
dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */
dmacHw_REG64_t ChannelSstat; /* Source Status Register */
dmacHw_REG64_t ChannelDstat; /* Destination Status Register */
dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */
dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */
dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */
dmacHw_REG64_t SrcGather; /* Source gather register */
dmacHw_REG64_t DstScatter; /* Destination scatter register */
} dmacHw_CH_REG_t;
/* Data type for RAW interrupt status registers */
typedef struct {
dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */
dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */
dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */
dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */
dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */
} dmacHw_INT_RAW_t;
/* Data type for interrupt status registers */
typedef struct {
dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */
dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */
dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */
dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */
dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */
} dmacHw_INT_STATUS_t;
/* Data type for interrupt mask registers*/
typedef struct {
dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */
dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */
dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */
dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
} dmacHw_INT_MASK_t;
/* Data type for interrupt clear registers */
typedef struct {
dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */
dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */
dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */
dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */
dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */
dmacHw_REG64_t StatusInt; /* Status for each interrupt type */
} dmacHw_INT_CLEAR_t;
/* Data type for software handshaking registers */
typedef struct {
dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */
dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */
dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */
dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */
dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */
dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */
} dmacHw_SW_HANDSHAKE_t;
/* Data type for misc. registers */
typedef struct {
dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */
dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
dmacHw_REG64_t DmaIdReg; /* DMA ID Register */
dmacHw_REG64_t DmaTestReg; /* DMA Test Register */
dmacHw_REG64_t Reserved0; /* Reserved */
dmacHw_REG64_t Reserved1; /* Reserved */
dmacHw_REG64_t CompParm6; /* Component Parameter 6 */
dmacHw_REG64_t CompParm5; /* Component Parameter 5 */
dmacHw_REG64_t CompParm4; /* Component Parameter 4 */
dmacHw_REG64_t CompParm3; /* Component Parameter 3 */
dmacHw_REG64_t CompParm2; /* Component Parameter 2 */
dmacHw_REG64_t CompParm1; /* Component Parameter 1 */
dmacHw_REG64_t CompId; /* Compoent ID */
} dmacHw_MISC_t;
/* Base registers */
#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
extern uint32_t dmaChannelCount_0;
extern uint32_t dmaChannelCount_1;
/* Define channel specific registers */
#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
/* Raw interrupt status registers */
#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
/* Interrupt status registers */
#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
/* Interrupt status registers */
#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
/* Interrupt clear registers */
#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
/* Software handshaking registers */
#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
/* Miscellaneous registers */
#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
/* Channel control registers */
#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
#define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
#define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
#define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
#define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
#define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
#define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
#define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
#define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
#define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
#define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
#define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
#define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
#define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
#define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
#define INT_STATUS_MASK(channel) (0x00000001 << (channel))
#define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
/* Bit mask for REG_DMACx_CTL_LO */
#define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */
#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */
#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1
#define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */
#define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */
#define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */
#define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4
#define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */
#define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */
#define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */
#define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */
#define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */
#define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */
#define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */
#define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */
#define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */
#define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */
#define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */
#define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */
#define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */
#define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */
#define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */
#define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */
#define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */
#define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */
#define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */
#define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */
#define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */
#define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */
#define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */
#define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */
#define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */
#define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */
#define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */
#define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */
#define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */
#define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */
#define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */
#define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */
#define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */
#define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */
/* Bit mask for REG_DMACx_CTL_HI */
#define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */
#define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */
/* Bit mask for REG_DMACx_CFG_LO */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */
#define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */
#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */
#define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */
#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */
#define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */
#define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */
#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */
#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */
#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */
#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */
#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */
#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */
#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */
#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */
#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */
#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */
#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */
#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */
#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */
/* Bit mask for REG_DMACx_CFG_HI */
#define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */
#define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */
#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */
#define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */
#define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */
#define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */
#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */
#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */
#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */
#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */
/* DMA Configuration Parameters */
#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */
#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */
#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */
#define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */
/* Define GET/SET macros to program the registers */
#define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
#define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel)))
#define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel)))
#define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
#define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0)
#define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)))
#define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
#define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0)
#define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)))
#define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
#define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
#define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
#define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0)
#define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)))
#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
#define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
#define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
#define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0)
#define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)))
#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
#define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
#define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
#define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1)
#define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0)
#define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
#define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
#define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
#define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
#define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
#endif /* _DMACHW_REG_H */
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