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Commit 1f02c8ef authored by Linus Walleij's avatar Linus Walleij
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Merge tag 'renesas-pinctrl-for-v5.18-tag2' of... 

Merge tag 'renesas-pinctrl-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.18 (take two)

  - Share more pin group data, to reduce kernel size and ease review,
  - Improve the pin control table validator,
  - Add support for the new R-Car S4-8 SoC,
  - Miscellaneous fixes and improvements.
parents 4649b970 babe298e
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Showing with 3915 additions and 3126 deletions
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
View file @ 1f02c8ef
......@@ -44,6 +44,7 @@ properties:
- renesas,pfc-r8a77990 # R-Car E3
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-r8a779f0 # R-Car S4-8
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
......
drivers/pinctrl/renesas/Kconfig
View file @ 1f02c8ef
......@@ -37,6 +37,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
select PINCTRL_RZG2L if ARCH_R9A07G044
select PINCTRL_RZG2L if ARCH_R9A07G054
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
......@@ -133,6 +134,10 @@ config PINCTRL_PFC_R8A77961
bool "pin control support for R-Car M3-W+" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A779F0
bool "pin control support for R-Car S4-8" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7792
bool "pin control support for R-Car V2H" if COMPILE_TEST
select PINCTRL_SH_PFC
......
drivers/pinctrl/renesas/Makefile
View file @ 1f02c8ef
......@@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
......
drivers/pinctrl/renesas/core.c
View file @ 1f02c8ef
This diff is collapsed.
drivers/pinctrl/renesas/pfc-emev2.c
View file @ 1f02c8ef
......@@ -749,23 +749,14 @@ static const unsigned int cf_ctrl_mux[] = {
CF_CDB2_MARK,
};
static const unsigned int cf_data8_pins[] = {
/* CF_D[0:7] */
77, 78, 79, 80,
81, 82, 83, 84,
};
static const unsigned int cf_data8_mux[] = {
CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
};
static const unsigned int cf_data16_pins[] = {
static const unsigned int cf_data_pins[] = {
/* CF_D[0:15] */
77, 78, 79, 80,
81, 82, 83, 84,
85, 86, 87, 88,
89, 90, 91, 92,
};
static const unsigned int cf_data16_mux[] = {
static const unsigned int cf_data_mux[] = {
CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
......@@ -895,26 +886,12 @@ static const unsigned int sdi0_ctrl_mux[] = {
SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
};
static const unsigned int sdi0_data1_pins[] = {
/* SDI0_DATA[0] */
53,
};
static const unsigned int sdi0_data1_mux[] = {
SDI0_DATA0_MARK,
};
static const unsigned int sdi0_data4_pins[] = {
/* SDI0_DATA[0:3] */
53, 54, 55, 56,
};
static const unsigned int sdi0_data4_mux[] = {
SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
};
static const unsigned int sdi0_data8_pins[] = {
static const unsigned int sdi0_data_pins[] = {
/* SDI0_DATA[0:7] */
53, 54, 55, 56,
57, 58, 59, 60
};
static const unsigned int sdi0_data8_mux[] = {
static const unsigned int sdi0_data_mux[] = {
SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
};
......@@ -928,18 +905,11 @@ static const unsigned int sdi1_ctrl_mux[] = {
SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
};
static const unsigned int sdi1_data1_pins[] = {
/* SDI1_DATA[0] */
64,
};
static const unsigned int sdi1_data1_mux[] = {
SDI1_DATA0_MARK,
};
static const unsigned int sdi1_data4_pins[] = {
static const unsigned int sdi1_data_pins[] = {
/* SDI1_DATA[0:3] */
64, 65, 66, 67,
};
static const unsigned int sdi1_data4_mux[] = {
static const unsigned int sdi1_data_mux[] = {
SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
};
......@@ -952,18 +922,11 @@ static const unsigned int sdi2_ctrl_mux[] = {
SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
};
static const unsigned int sdi2_data1_pins[] = {
/* SDI2_DATA[0] */
89,
};
static const unsigned int sdi2_data1_mux[] = {
SDI2_DATA0_MARK,
};
static const unsigned int sdi2_data4_pins[] = {
static const unsigned int sdi2_data_pins[] = {
/* SDI2_DATA[0:3] */
89, 90, 91, 92,
};
static const unsigned int sdi2_data4_mux[] = {
static const unsigned int sdi2_data_mux[] = {
SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
};
......@@ -1131,8 +1094,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(cam),
SH_PFC_PIN_GROUP(cf_ctrl),
SH_PFC_PIN_GROUP(cf_data8),
SH_PFC_PIN_GROUP(cf_data16),
BUS_DATA_PIN_GROUP(cf_data, 8),
BUS_DATA_PIN_GROUP(cf_data, 16),
SH_PFC_PIN_GROUP(dtv_a),
SH_PFC_PIN_GROUP(dtv_b),
......@@ -1161,17 +1124,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sd_cki),
SH_PFC_PIN_GROUP(sdi0_ctrl),
SH_PFC_PIN_GROUP(sdi0_data1),
SH_PFC_PIN_GROUP(sdi0_data4),
SH_PFC_PIN_GROUP(sdi0_data8),
BUS_DATA_PIN_GROUP(sdi0_data, 1),
BUS_DATA_PIN_GROUP(sdi0_data, 4),
BUS_DATA_PIN_GROUP(sdi0_data, 8),
SH_PFC_PIN_GROUP(sdi1_ctrl),
SH_PFC_PIN_GROUP(sdi1_data1),
SH_PFC_PIN_GROUP(sdi1_data4),
BUS_DATA_PIN_GROUP(sdi1_data, 1),
BUS_DATA_PIN_GROUP(sdi1_data, 4),
SH_PFC_PIN_GROUP(sdi2_ctrl),
SH_PFC_PIN_GROUP(sdi2_data1),
SH_PFC_PIN_GROUP(sdi2_data4),
BUS_DATA_PIN_GROUP(sdi2_data, 1),
BUS_DATA_PIN_GROUP(sdi2_data, 4),
SH_PFC_PIN_GROUP(tp33),
......
drivers/pinctrl/renesas/pfc-r8a73a4.c
View file @ 1f02c8ef
......@@ -1449,25 +1449,11 @@ IRQC_PINS_MUX(327, 55);
IRQC_PINS_MUX(328, 56);
IRQC_PINS_MUX(329, 57);
/* - MMCIF0 ----------------------------------------------------------------- */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
164,
};
static const unsigned int mmc0_data1_mux[] = {
MMCD0_0_MARK,
};
static const unsigned int mmc0_data4_pins[] = {
/* D[0:3] */
164, 165, 166, 167,
};
static const unsigned int mmc0_data4_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
};
static const unsigned int mmc0_data8_pins[] = {
static const unsigned int mmc0_data_pins[] = {
/* D[0:7] */
164, 165, 166, 167, 168, 169, 170, 171,
};
static const unsigned int mmc0_data8_mux[] = {
static const unsigned int mmc0_data_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
};
......@@ -1479,25 +1465,11 @@ static const unsigned int mmc0_ctrl_mux[] = {
MMCCMD0_MARK, MMCCLK0_MARK,
};
/* - MMCIF1 ----------------------------------------------------------------- */
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
199,
};
static const unsigned int mmc1_data1_mux[] = {
MMCD1_0_MARK,
};
static const unsigned int mmc1_data4_pins[] = {
/* D[0:3] */
199, 198, 197, 196,
};
static const unsigned int mmc1_data4_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
};
static const unsigned int mmc1_data8_pins[] = {
static const unsigned int mmc1_data_pins[] = {
/* D[0:7] */
199, 198, 197, 196, 195, 194, 193, 192,
};
static const unsigned int mmc1_data8_mux[] = {
static const unsigned int mmc1_data_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
};
......@@ -1704,18 +1676,11 @@ static const unsigned int scifb3_ctrl_b_mux[] = {
SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
302,
};
static const unsigned int sdhi0_data1_mux[] = {
SDHID0_0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
302, 303, 304, 305,
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
......@@ -1740,18 +1705,11 @@ static const unsigned int sdhi0_wp_mux[] = {
SDHIWP0_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
289,
};
static const unsigned int sdhi1_data1_mux[] = {
SDHID1_0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
289, 290, 291, 292,
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
......@@ -1762,18 +1720,11 @@ static const unsigned int sdhi1_ctrl_mux[] = {
SDHICLK1_MARK, SDHICMD1_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
295,
};
static const unsigned int sdhi2_data1_mux[] = {
SDHID2_0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
295, 296, 297, 298,
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
......@@ -1843,13 +1794,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(irqc_irq55),
SH_PFC_PIN_GROUP(irqc_irq56),
SH_PFC_PIN_GROUP(irqc_irq57),
SH_PFC_PIN_GROUP(mmc0_data1),
SH_PFC_PIN_GROUP(mmc0_data4),
SH_PFC_PIN_GROUP(mmc0_data8),
BUS_DATA_PIN_GROUP(mmc0_data, 1),
BUS_DATA_PIN_GROUP(mmc0_data, 4),
BUS_DATA_PIN_GROUP(mmc0_data, 8),
SH_PFC_PIN_GROUP(mmc0_ctrl),
SH_PFC_PIN_GROUP(mmc1_data1),
SH_PFC_PIN_GROUP(mmc1_data4),
SH_PFC_PIN_GROUP(mmc1_data8),
BUS_DATA_PIN_GROUP(mmc1_data, 1),
BUS_DATA_PIN_GROUP(mmc1_data, 4),
BUS_DATA_PIN_GROUP(mmc1_data, 8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
......@@ -1878,16 +1829,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb3_data_b),
SH_PFC_PIN_GROUP(scifb3_clk_b),
SH_PFC_PIN_GROUP(scifb3_ctrl_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
};
......@@ -2655,9 +2606,9 @@ static const unsigned int r8a73a4_portcr_offsets[] = {
0x00002000, 0x00003000, 0x00003000,
};
static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
static int r8a73a4_pin_to_portcr(unsigned int pin)
{
return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
return r8a73a4_portcr_offsets[pin >> 5] + pin;
}
static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
......
drivers/pinctrl/renesas/pfc-r8a7740.c
View file @ 1f02c8ef
This diff is collapsed.
drivers/pinctrl/renesas/pfc-r8a77470.c
View file @ 1f02c8ef
This diff is collapsed.
drivers/pinctrl/renesas/pfc-r8a7778.c
View file @ 1f02c8ef
......@@ -1427,25 +1427,17 @@ I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
/* - MMC macro -------------------------------------------------------------- */
#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
/* - MMC -------------------------------------------------------------------- */
MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
MMC_PFC_DAT1(mmc_data1, MMC_D0);
MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
MMC_D2, MMC_D3);
MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
MMC_PFC_PINS(mmc_data, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
MMC_PFC_DAT8(mmc_data, MMC_D0, MMC_D1,
MMC_D2, MMC_D3,
MMC_D4, MMC_D5,
MMC_D6, MMC_D7);
......@@ -1530,7 +1522,6 @@ SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
/* - SDHI macro ------------------------------------------------------------- */
#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
......@@ -1541,11 +1532,9 @@ SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17));
SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
SDHI_PFC_PINS(sdhi0_data, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
SDHI_PFC_DAT4(sdhi0_data, SD0_DAT0, SD0_DAT1,
SD0_DAT2, SD0_DAT3);
SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
......@@ -1559,17 +1548,13 @@ SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
SDHI_PFC_PINS(sdhi1_data_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
SDHI_PFC_DAT4(sdhi1_data_a, SD1_DAT0_A, SD1_DAT1_A,
SD1_DAT2_A, SD1_DAT3_A);
SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
SDHI_PFC_PINS(sdhi1_data_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
SDHI_PFC_DAT4(sdhi1_data_b, SD1_DAT0_B, SD1_DAT1_B,
SD1_DAT2_B, SD1_DAT3_B);
SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
......@@ -1585,17 +1570,13 @@ SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
SDHI_PFC_PINS(sdhi2_data_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
SDHI_PFC_DAT4(sdhi2_data_a, SD2_DAT0_A, SD2_DAT1_A,
SD2_DAT2_A, SD2_DAT3_A);
SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
SDHI_PFC_PINS(sdhi2_data_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
SDHI_PFC_DAT4(sdhi2_data_b, SD2_DAT0_B, SD2_DAT1_B,
SD2_DAT2_B, SD2_DAT3_B);
SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
......@@ -1744,9 +1725,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(i2c3_c),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_data_b),
......@@ -1781,27 +1762,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_cd_a),
SH_PFC_PIN_GROUP(sdhi1_cd_b),
SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
SH_PFC_PIN_GROUP(sdhi1_data1_a),
SH_PFC_PIN_GROUP(sdhi1_data1_b),
SH_PFC_PIN_GROUP(sdhi1_data4_a),
SH_PFC_PIN_GROUP(sdhi1_data4_b),
BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a),
BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b),
BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a),
BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b),
SH_PFC_PIN_GROUP(sdhi1_wp_a),
SH_PFC_PIN_GROUP(sdhi1_wp_b),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
SH_PFC_PIN_GROUP(sdhi2_data1_a),
SH_PFC_PIN_GROUP(sdhi2_data1_b),
SH_PFC_PIN_GROUP(sdhi2_data4_a),
SH_PFC_PIN_GROUP(sdhi2_data4_b),
BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a),
BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b),
BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a),
BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(ssi012_ctrl),
......
drivers/pinctrl/renesas/pfc-r8a7779.c
View file @ 1f02c8ef
......@@ -1928,28 +1928,13 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
EX_CS5_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(0, 19),
};
static const unsigned int mmc0_data1_mux[] = {
MMC0_D0_MARK,
};
static const unsigned int mmc0_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 2),
};
static const unsigned int mmc0_data4_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
};
static const unsigned int mmc0_data8_pins[] = {
static const unsigned int mmc0_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
};
static const unsigned int mmc0_data8_mux[] = {
static const unsigned int mmc0_data_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
};
......@@ -1960,28 +1945,13 @@ static const unsigned int mmc0_ctrl_pins[] = {
static const unsigned int mmc0_ctrl_mux[] = {
MMC0_CMD_MARK, MMC0_CLK_MARK,
};
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(2, 8),
};
static const unsigned int mmc1_data1_mux[] = {
MMC1_D0_MARK,
};
static const unsigned int mmc1_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11),
};
static const unsigned int mmc1_data4_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
};
static const unsigned int mmc1_data8_pins[] = {
static const unsigned int mmc1_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
};
static const unsigned int mmc1_data8_mux[] = {
static const unsigned int mmc1_data_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
};
......@@ -2386,19 +2356,12 @@ static const unsigned int scif_clk_d_mux[] = {
SCIF_CLK_D_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 21),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 24),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
......@@ -2423,19 +2386,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(0, 19),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 2),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
......@@ -2460,19 +2416,12 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 1),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4),
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
......@@ -2497,19 +2446,12 @@ static const unsigned int sdhi2_wp_mux[] = {
SD2_WP_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(1, 18),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 21),
};
static const unsigned int sdhi3_data4_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_ctrl_pins[] = {
......@@ -2749,13 +2691,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lbsc_ex_cs3),
SH_PFC_PIN_GROUP(lbsc_ex_cs4),
SH_PFC_PIN_GROUP(lbsc_ex_cs5),
SH_PFC_PIN_GROUP(mmc0_data1),
SH_PFC_PIN_GROUP(mmc0_data4),
SH_PFC_PIN_GROUP(mmc0_data8),
BUS_DATA_PIN_GROUP(mmc0_data, 1),
BUS_DATA_PIN_GROUP(mmc0_data, 4),
BUS_DATA_PIN_GROUP(mmc0_data, 8),
SH_PFC_PIN_GROUP(mmc0_ctrl),
SH_PFC_PIN_GROUP(mmc1_data1),
SH_PFC_PIN_GROUP(mmc1_data4),
SH_PFC_PIN_GROUP(mmc1_data8),
BUS_DATA_PIN_GROUP(mmc1_data, 1),
BUS_DATA_PIN_GROUP(mmc1_data, 4),
BUS_DATA_PIN_GROUP(mmc1_data, 8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
......@@ -2812,23 +2754,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(scif_clk_c),
SH_PFC_PIN_GROUP(scif_clk_d),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
......
drivers/pinctrl/renesas/pfc-r8a7790.c
View file @ 1f02c8ef
This diff is collapsed.
drivers/pinctrl/renesas/pfc-r8a7791.c
View file @ 1f02c8ef
This diff is collapsed.
drivers/pinctrl/renesas/pfc-r8a7792.c
View file @ 1f02c8ef
This diff is collapsed.
drivers/pinctrl/renesas/pfc-r8a7794.c
View file @ 1f02c8ef
This diff is collapsed.
drivers/pinctrl/renesas/pfc-r8a77950.c
View file @ 1f02c8ef
......@@ -3140,18 +3140,11 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
......@@ -3163,18 +3156,11 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
......@@ -3395,19 +3381,12 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
......@@ -3433,19 +3412,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 8),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
......@@ -3471,30 +3443,14 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 2),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int sdhi2_data4_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_data8_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi2_data8_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
......@@ -3543,30 +3499,14 @@ static const unsigned int sdhi2_ds_mux[] = {
SD2_DS_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 9),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
};
static const unsigned int sdhi3_data4_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_data8_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_data8_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
......@@ -4103,11 +4043,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
......@@ -4137,28 +4077,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_clk),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_data8),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
SH_PFC_PIN_GROUP(sdhi3_data8),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
......@@ -5574,8 +5514,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
......@@ -5832,7 +5771,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77950_pfc_ops = {
.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
......@@ -5840,7 +5779,7 @@ static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
const struct sh_pfc_soc_info r8a77950_pinmux_info = {
.name = "r8a77950_pfc",
.ops = &r8a77950_pinmux_ops,
.ops = &r8a77950_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
......
drivers/pinctrl/renesas/pfc-r8a77951.c
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drivers/pinctrl/renesas/pfc-r8a7796.c
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drivers/pinctrl/renesas/pfc-r8a77965.c
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drivers/pinctrl/renesas/pfc-r8a77970.c
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......@@ -1102,30 +1102,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 6),
};
static const unsigned int mmc_data1_mux[] = {
MMC_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
};
static const unsigned int mmc_data4_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
......@@ -1393,22 +1377,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
};
static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
......@@ -1418,36 +1386,14 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
/* - RPC -------------------------------------------------------------------- */
static const unsigned int rpc_clk1_pins[] = {
static const unsigned int rpc_clk_pins[] = {
/* Octal-SPI flash: C/SCLK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int rpc_clk1_mux[] = {
QSPI0_SPCLK_MARK,
};
static const unsigned int rpc_clk2_pins[] = {
/* HyperFlash: CK, CK# */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
};
static const unsigned int rpc_clk2_mux[] = {
static const unsigned int rpc_clk_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
};
static const unsigned int rpc_ctrl_pins[] = {
......@@ -1639,25 +1585,21 @@ static const unsigned int tmu_tclk2_b_mux[] = {
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data12 vin0_data_pins = {
.data12 = {
static const unsigned int vin0_data_pins[] = {
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
},
};
static const union vin_data12 vin0_data_mux = {
.data12 = {
static const unsigned int vin0_data_mux[] = {
VI0_DATA0_MARK, VI0_DATA1_MARK,
VI0_DATA2_MARK, VI0_DATA3_MARK,
VI0_DATA4_MARK, VI0_DATA5_MARK,
VI0_DATA6_MARK, VI0_DATA7_MARK,
VI0_DATA8_MARK, VI0_DATA9_MARK,
VI0_DATA10_MARK, VI0_DATA11_MARK,
},
};
static const unsigned int vin0_sync_pins[] = {
/* HSYNC#, VSYNC# */
......@@ -1689,25 +1631,21 @@ static const unsigned int vin0_clk_mux[] = {
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data12 vin1_data_pins = {
.data12 = {
static const unsigned int vin1_data_pins[] = {
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
},
};
static const union vin_data12 vin1_data_mux = {
.data12 = {
static const unsigned int vin1_data_mux[] = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
},
};
static const unsigned int vin1_sync_pins[] = {
/* HSYNC#, VSYNC# */
......@@ -1783,9 +1721,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
......@@ -1822,13 +1760,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(rpc_clk1),
SH_PFC_PIN_GROUP(rpc_clk2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
BUS_DATA_PIN_GROUP(rpc_clk, 1),
BUS_DATA_PIN_GROUP(rpc_clk, 2),
SH_PFC_PIN_GROUP(rpc_ctrl),
SH_PFC_PIN_GROUP(rpc_data),
SH_PFC_PIN_GROUP(rpc_reset),
......@@ -1853,16 +1791,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
VIN_DATA_PIN_GROUP(vin0_data, 8),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 12),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 8),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 12),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
......@@ -2496,8 +2434,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
......@@ -2656,7 +2593,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77970_pfc_ops = {
.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
......@@ -2664,7 +2601,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = {
const struct sh_pfc_soc_info r8a77970_pinmux_info = {
.name = "r8a77970_pfc",
.ops = &pinmux_ops,
.ops = &r8a77970_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
......
drivers/pinctrl/renesas/pfc-r8a77980.c
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drivers/pinctrl/renesas/pfc-r8a77990.c
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drivers/pinctrl/renesas/pfc-r8a77995.c
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......@@ -1266,30 +1266,14 @@ static const unsigned int mlb_3pin_mux[] = {
};
/* - MMC ------------------------------------------------------------------- */
static const unsigned int mmc_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int mmc_data1_mux[] = {
MMC_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int mmc_data4_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
......@@ -1958,8 +1942,7 @@ static const unsigned int vin4_data18_mux[] = {
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_pins = {
.data24 = {
static const unsigned int vin4_data_pins[] = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
......@@ -1972,10 +1955,8 @@ static const union vin_data vin4_data_pins = {
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
},
};
static const union vin_data vin4_data_mux = {
.data24 = {
static const unsigned int vin4_data_mux[] = {
VI4_DATA0_MARK, VI4_DATA1_MARK,
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
......@@ -1988,7 +1969,6 @@ static const union vin_data vin4_data_mux = {
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
......@@ -2058,9 +2038,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_a),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(mlb_3pin),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
......@@ -2137,13 +2117,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
SH_PFC_PIN_GROUP(ssi4_data_b),
SH_PFC_PIN_GROUP(usb0),
VIN_DATA_PIN_GROUP(vin4_data, 8),
VIN_DATA_PIN_GROUP(vin4_data, 10),
VIN_DATA_PIN_GROUP(vin4_data, 12),
VIN_DATA_PIN_GROUP(vin4_data, 16),
BUS_DATA_PIN_GROUP(vin4_data, 8),
BUS_DATA_PIN_GROUP(vin4_data, 10),
BUS_DATA_PIN_GROUP(vin4_data, 12),
BUS_DATA_PIN_GROUP(vin4_data, 16),
SH_PFC_PIN_GROUP(vin4_data18),
VIN_DATA_PIN_GROUP(vin4_data, 20),
VIN_DATA_PIN_GROUP(vin4_data, 24),
BUS_DATA_PIN_GROUP(vin4_data, 20),
BUS_DATA_PIN_GROUP(vin4_data, 24),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
......@@ -2856,7 +2836,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
......@@ -3092,7 +3072,7 @@ r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
const struct pinmux_bias_reg *reg;
unsigned int bit;
reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
if (!reg)
return reg;
......@@ -3158,7 +3138,7 @@ static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
sh_pfc_write(pfc, reg->puen, enable);
}
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77995_pfc_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
.get_bias = r8a77995_pinmux_get_bias,
.set_bias = r8a77995_pinmux_set_bias,
......@@ -3166,7 +3146,7 @@ static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
const struct sh_pfc_soc_info r8a77995_pinmux_info = {
.name = "r8a77995_pfc",
.ops = &r8a77995_pinmux_ops,
.ops = &r8a77995_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
......
drivers/pinctrl/renesas/pfc-r8a779a0.c
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drivers/pinctrl/renesas/pfc-r8a779f0.c 0 → 100644
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drivers/pinctrl/renesas/pfc-sh7203.c
View file @ 1f02c8ef
......@@ -6,7 +6,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7203.h>
#include "sh_pfc.h"
......
drivers/pinctrl/renesas/pfc-sh7264.c
View file @ 1f02c8ef
......@@ -6,7 +6,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7264.h>
#include "sh_pfc.h"
......
drivers/pinctrl/renesas/pfc-sh7269.c
View file @ 1f02c8ef
......@@ -7,7 +7,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7269.h>
#include "sh_pfc.h"
......
drivers/pinctrl/renesas/pfc-sh73a0.c
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drivers/pinctrl/renesas/pfc-sh7720.c
View file @ 1f02c8ef
......@@ -6,7 +6,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7720.h>
#include "sh_pfc.h"
......
drivers/pinctrl/renesas/pfc-sh7722.c
View file @ 1f02c8ef
// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7722.h>
#include "sh_pfc.h"
......
drivers/pinctrl/renesas/pinctrl.c
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drivers/pinctrl/renesas/sh_pfc.h
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