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Commit 1fa774f7 authored by Arnd Bergmann's avatar Arnd Bergmann
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usb: gadget: remove s3c24xx drivers 

The s3c24xx platform is gone, so both the udc and hsudc drivers
can be removed as well.
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 7d1ec119
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drivers/usb/gadget/udc/Kconfig
View file @ 1fa774f7
......@@ -206,31 +206,6 @@ config USB_PXA27X
dynamically linked module called "pxa27x_udc" and force all
gadget drivers to also be dynamically linked.
config USB_S3C2410
tristate "S3C2410 USB Device Controller"
depends on ARCH_S3C24XX
help
Samsung's S3C2410 is an ARM-4 processor with an integrated
full speed USB 1.1 device controller. It has 4 configurable
endpoints, as well as endpoint zero (for control transfers).
This driver has been tested on the S3C2410, S3C2412, and
S3C2440 processors.
config USB_S3C2410_DEBUG
bool "S3C2410 udc debug messages"
depends on USB_S3C2410
config USB_S3C_HSUDC
tristate "S3C2416, S3C2443 and S3C2450 USB Device Controller"
depends on ARCH_S3C24XX
help
Samsung's S3C2416, S3C2443 and S3C2450 is an ARM9 based SoC
integrated with dual speed USB 2.0 device controller. It has
8 endpoints, as well as endpoint zero.
This driver has been tested on S3C2416 and S3C2450 processors.
config USB_MV_UDC
tristate "Marvell USB2.0 Device Controller"
depends on HAS_DMA
......
drivers/usb/gadget/udc/Makefile
View file @ 1fa774f7
......@@ -17,7 +17,6 @@ obj-$(CONFIG_USB_PXA25X) += pxa25x_udc.o
obj-$(CONFIG_USB_PXA27X) += pxa27x_udc.o
obj-$(CONFIG_USB_GOKU) += goku_udc.o
obj-$(CONFIG_USB_OMAP) += omap_udc.o
obj-$(CONFIG_USB_S3C2410) += s3c2410_udc.o
obj-$(CONFIG_USB_AT91) += at91_udc.o
obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_BCM63XX_UDC) += bcm63xx_udc.o
......@@ -28,7 +27,6 @@ obj-$(CONFIG_USB_M66592) += m66592-udc.o
obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
obj-$(CONFIG_USB_RENESAS_USB3) += renesas_usb3.o
obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o
obj-$(CONFIG_USB_EG20T) += pch_udc.o
obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
......
drivers/usb/gadget/udc/s3c-hsudc.c deleted 100644 → 0
View file @ 7d1ec119
// SPDX-License-Identifier: GPL-2.0
/* linux/drivers/usb/gadget/s3c-hsudc.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S3C24XX USB 2.0 High-speed USB controller gadget driver
*
* The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
* Each endpoint can be configured as either in or out endpoint. Endpoints
* can be configured for Bulk or Interrupt transfer mode.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/prefetch.h>
#include <linux/platform_data/s3c-hsudc.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#define S3C_HSUDC_REG(x) (x)
/* Non-Indexed Registers */
#define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
#define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
#define S3C_EIR_EP0 (1<<0)
#define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
#define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
#define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
#define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
#define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
#define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
#define S3C_SSR_DTZIEN_EN (0xff8f)
#define S3C_SSR_ERR (0xff80)
#define S3C_SSR_VBUSON (1 << 8)
#define S3C_SSR_HSP (1 << 4)
#define S3C_SSR_SDE (1 << 3)
#define S3C_SSR_RESUME (1 << 2)
#define S3C_SSR_SUSPEND (1 << 1)
#define S3C_SSR_RESET (1 << 0)
#define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
#define S3C_SCR_DTZIEN_EN (1 << 14)
#define S3C_SCR_RRD_EN (1 << 5)
#define S3C_SCR_SUS_EN (1 << 1)
#define S3C_SCR_RST_EN (1 << 0)
#define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
#define S3C_EP0SR_EP0_LWO (1 << 6)
#define S3C_EP0SR_STALL (1 << 4)
#define S3C_EP0SR_TX_SUCCESS (1 << 1)
#define S3C_EP0SR_RX_SUCCESS (1 << 0)
#define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
#define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
/* Indexed Registers */
#define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
#define S3C_ESR_FLUSH (1 << 6)
#define S3C_ESR_STALL (1 << 5)
#define S3C_ESR_LWO (1 << 4)
#define S3C_ESR_PSIF_ONE (1 << 2)
#define S3C_ESR_PSIF_TWO (2 << 2)
#define S3C_ESR_TX_SUCCESS (1 << 1)
#define S3C_ESR_RX_SUCCESS (1 << 0)
#define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
#define S3C_ECR_DUEN (1 << 7)
#define S3C_ECR_FLUSH (1 << 6)
#define S3C_ECR_STALL (1 << 1)
#define S3C_ECR_IEMS (1 << 0)
#define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
#define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
#define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
#define WAIT_FOR_SETUP (0)
#define DATA_STATE_XMIT (1)
#define DATA_STATE_RECV (2)
static const char * const s3c_hsudc_supply_names[] = {
"vdda", /* analog phy supply, 3.3V */
"vddi", /* digital phy supply, 1.2V */
"vddosc", /* oscillator supply, 1.8V - 3.3V */
};
/**
* struct s3c_hsudc_ep - Endpoint representation used by driver.
* @ep: USB gadget layer representation of device endpoint.
* @name: Endpoint name (as required by ep autoconfiguration).
* @dev: Reference to the device controller to which this EP belongs.
* @desc: Endpoint descriptor obtained from the gadget driver.
* @queue: Transfer request queue for the endpoint.
* @stopped: Maintains state of endpoint, set if EP is halted.
* @bEndpointAddress: EP address (including direction bit).
* @fifo: Base address of EP FIFO.
*/
struct s3c_hsudc_ep {
struct usb_ep ep;
char name[20];
struct s3c_hsudc *dev;
struct list_head queue;
u8 stopped;
u8 wedge;
u8 bEndpointAddress;
void __iomem *fifo;
};
/**
* struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
* @req: Reference to USB gadget transfer request.
* @queue: Used for inserting this request to the endpoint request queue.
*/
struct s3c_hsudc_req {
struct usb_request req;
struct list_head queue;
};
/**
* struct s3c_hsudc - Driver's abstraction of the device controller.
* @gadget: Instance of usb_gadget which is referenced by gadget driver.
* @driver: Reference to currently active gadget driver.
* @dev: The device reference used by probe function.
* @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
* @regs: Remapped base address of controller's register space.
* irq: IRQ number used by the controller.
* uclk: Reference to the controller clock.
* ep0state: Current state of EP0.
* ep: List of endpoints supported by the controller.
*/
struct s3c_hsudc {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct device *dev;
struct s3c24xx_hsudc_platdata *pd;
struct usb_phy *transceiver;
struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
spinlock_t lock;
void __iomem *regs;
int irq;
struct clk *uclk;
int ep0state;
struct s3c_hsudc_ep ep[];
};
#define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
#define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
#define ep_index(_ep) ((_ep)->bEndpointAddress & \
USB_ENDPOINT_NUMBER_MASK)
static const char driver_name[] = "s3c-udc";
static const char ep0name[] = "ep0-control";
static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
{
return container_of(req, struct s3c_hsudc_req, req);
}
static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
{
return container_of(ep, struct s3c_hsudc_ep, ep);
}
static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
{
return container_of(gadget, struct s3c_hsudc, gadget);
}
static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
{
ep_addr &= USB_ENDPOINT_NUMBER_MASK;
writel(ep_addr, hsudc->regs + S3C_IR);
}
static inline void __orr32(void __iomem *ptr, u32 val)
{
writel(readl(ptr) | val, ptr);
}
/**
* s3c_hsudc_complete_request - Complete a transfer request.
* @hsep: Endpoint to which the request belongs.
* @hsreq: Transfer request to be completed.
* @status: Transfer completion status for the transfer request.
*/
static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
struct s3c_hsudc_req *hsreq, int status)
{
unsigned int stopped = hsep->stopped;
struct s3c_hsudc *hsudc = hsep->dev;
list_del_init(&hsreq->queue);
hsreq->req.status = status;
if (!ep_index(hsep)) {
hsudc->ep0state = WAIT_FOR_SETUP;
hsep->bEndpointAddress &= ~USB_DIR_IN;
}
hsep->stopped = 1;
spin_unlock(&hsudc->lock);
usb_gadget_giveback_request(&hsep->ep, &hsreq->req);
spin_lock(&hsudc->lock);
hsep->stopped = stopped;
}
/**
* s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
* @hsep: Endpoint for which queued requests have to be terminated.
* @status: Transfer completion status for the transfer request.
*/
static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
{
struct s3c_hsudc_req *hsreq;
while (!list_empty(&hsep->queue)) {
hsreq = list_entry(hsep->queue.next,
struct s3c_hsudc_req, queue);
s3c_hsudc_complete_request(hsep, hsreq, status);
}
}
/**
* s3c_hsudc_stop_activity - Stop activity on all endpoints.
* @hsudc: Device controller for which EP activity is to be stopped.
*
* All the endpoints are stopped and any pending transfer requests if any on
* the endpoint are terminated.
*/
static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
{
struct s3c_hsudc_ep *hsep;
int epnum;
hsudc->gadget.speed = USB_SPEED_UNKNOWN;
for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
hsep = &hsudc->ep[epnum];
hsep->stopped = 1;
s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
}
}
/**
* s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
* @hsudc: Device controller from which setup packet is to be read.
* @buf: The buffer into which the setup packet is read.
*
* The setup packet received in the EP0 fifo is read and stored into a
* given buffer address.
*/
static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
{
int count;
count = readl(hsudc->regs + S3C_BRCR);
while (count--)
*buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
}
/**
* s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
* @hsep: Endpoint to which the data is to be written.
* @hsreq: Transfer request from which the next chunk of data is written.
*
* Write the next chunk of data from a transfer request to the endpoint FIFO.
* If the transfer request completes, 1 is returned, otherwise 0 is returned.
*/
static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
struct s3c_hsudc_req *hsreq)
{
u16 *buf;
u32 max = ep_maxpacket(hsep);
u32 count, length;
bool is_last;
void __iomem *fifo = hsep->fifo;
buf = hsreq->req.buf + hsreq->req.actual;
prefetch(buf);
length = hsreq->req.length - hsreq->req.actual;
length = min(length, max);
hsreq->req.actual += length;
writel(length, hsep->dev->regs + S3C_BWCR);
for (count = 0; count < length; count += 2)
writel(*buf++, fifo);
if (count != max) {
is_last = true;
} else {
if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
is_last = false;
else
is_last = true;
}
if (is_last) {
s3c_hsudc_complete_request(hsep, hsreq, 0);
return 1;
}
return 0;
}
/**
* s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
* @hsep: Endpoint from which the data is to be read.
* @hsreq: Transfer request to which the next chunk of data read is written.
*
* Read the next chunk of data from the endpoint FIFO and a write it to the
* transfer request buffer. If the transfer request completes, 1 is returned,
* otherwise 0 is returned.
*/
static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
struct s3c_hsudc_req *hsreq)
{
struct s3c_hsudc *hsudc = hsep->dev;
u32 csr, offset;
u16 *buf, word;
u32 buflen, rcnt, rlen;
void __iomem *fifo = hsep->fifo;
u32 is_short = 0;
offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
csr = readl(hsudc->regs + offset);
if (!(csr & S3C_ESR_RX_SUCCESS))
return -EINVAL;
buf = hsreq->req.buf + hsreq->req.actual;
prefetchw(buf);
buflen = hsreq->req.length - hsreq->req.actual;
rcnt = readl(hsudc->regs + S3C_BRCR);
rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
hsreq->req.actual += min(rlen, buflen);
is_short = (rlen < hsep->ep.maxpacket);
while (rcnt-- != 0) {
word = (u16)readl(fifo);
if (buflen) {
*buf++ = word;
buflen--;
} else {
hsreq->req.status = -EOVERFLOW;
}
}
writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
if (is_short || hsreq->req.actual == hsreq->req.length) {
s3c_hsudc_complete_request(hsep, hsreq, 0);
return 1;
}
return 0;
}
/**
* s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
* @hsudc - Device controller for which the interrupt is to be handled.
* @ep_idx - Endpoint number on which an interrupt is pending.
*
* Handles interrupt for a in-endpoint. The interrupts that are handled are
* stall and data transmit complete interrupt.
*/
static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
{
struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
struct s3c_hsudc_req *hsreq;
u32 csr;
csr = readl(hsudc->regs + S3C_ESR);
if (csr & S3C_ESR_STALL) {
writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
return;
}
if (csr & S3C_ESR_TX_SUCCESS) {
writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
if (list_empty(&hsep->queue))
return;
hsreq = list_entry(hsep->queue.next,
struct s3c_hsudc_req, queue);
if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
(csr & S3C_ESR_PSIF_TWO))
s3c_hsudc_write_fifo(hsep, hsreq);
}
}
/**
* s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
* @hsudc - Device controller for which the interrupt is to be handled.
* @ep_idx - Endpoint number on which an interrupt is pending.
*
* Handles interrupt for a out-endpoint. The interrupts that are handled are
* stall, flush and data ready interrupt.
*/
static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
{
struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
struct s3c_hsudc_req *hsreq;
u32 csr;
csr = readl(hsudc->regs + S3C_ESR);
if (csr & S3C_ESR_STALL) {
writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
return;
}
if (csr & S3C_ESR_FLUSH) {
__orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
return;
}
if (csr & S3C_ESR_RX_SUCCESS) {
if (list_empty(&hsep->queue))
return;
hsreq = list_entry(hsep->queue.next,
struct s3c_hsudc_req, queue);
if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
(csr & S3C_ESR_PSIF_TWO))
s3c_hsudc_read_fifo(hsep, hsreq);
}
}
/** s3c_hsudc_set_halt - Set or clear a endpoint halt.
* @_ep: Endpoint on which halt has to be set or cleared.
* @value: 1 for setting halt on endpoint, 0 to clear halt.
*
* Set or clear endpoint halt. If halt is set, the endpoint is stopped.
* If halt is cleared, for in-endpoints, if there are any pending
* transfer requests, transfers are started.
*/
static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
{
struct s3c_hsudc_ep *hsep = our_ep(_ep);
struct s3c_hsudc *hsudc = hsep->dev;
struct s3c_hsudc_req *hsreq;
unsigned long irqflags;
u32 ecr;
u32 offset;
if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
return -EAGAIN;
spin_lock_irqsave(&hsudc->lock, irqflags);
set_index(hsudc, ep_index(hsep));
offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
ecr = readl(hsudc->regs + offset);
if (value) {
ecr |= S3C_ECR_STALL;
if (ep_index(hsep))
ecr |= S3C_ECR_FLUSH;
hsep->stopped = 1;
} else {
ecr &= ~S3C_ECR_STALL;
hsep->stopped = hsep->wedge = 0;
}
writel(ecr, hsudc->regs + offset);
if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
hsreq = list_entry(hsep->queue.next,
struct s3c_hsudc_req, queue);
if (hsreq)
s3c_hsudc_write_fifo(hsep, hsreq);
}
spin_unlock_irqrestore(&hsudc->lock, irqflags);
return 0;
}
/** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
* @_ep: Endpoint on which wedge has to be set.
*
* Sets the halt feature with the clear requests ignored.
*/
static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
{
struct s3c_hsudc_ep *hsep = our_ep(_ep);
if (!hsep)
return -EINVAL;
hsep->wedge = 1;
return usb_ep_set_halt(_ep);
}
/** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
* @_ep: Device controller on which the set/clear feature needs to be handled.
* @ctrl: Control request as received on the endpoint 0.
*
* Handle set feature or clear feature control requests on the control endpoint.
*/
static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
struct usb_ctrlrequest *ctrl)
{
struct s3c_hsudc_ep *hsep;
bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
hsep = &hsudc->ep[ep_num];
switch (le16_to_cpu(ctrl->wValue)) {
case USB_ENDPOINT_HALT:
if (set || !hsep->wedge)
s3c_hsudc_set_halt(&hsep->ep, set);
return 0;
}
}
return -ENOENT;
}
/**
* s3c_hsudc_process_req_status - Handle get status control request.
* @hsudc: Device controller on which get status request has be handled.
* @ctrl: Control request as received on the endpoint 0.
*
* Handle get status control request received on control endpoint.
*/
static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
struct usb_ctrlrequest *ctrl)
{
struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
struct s3c_hsudc_req hsreq;
struct s3c_hsudc_ep *hsep;
__le16 reply;
u8 epnum;
switch (ctrl->bRequestType & USB_RECIP_MASK) {
case USB_RECIP_DEVICE:
reply = cpu_to_le16(0);
break;
case USB_RECIP_INTERFACE:
reply = cpu_to_le16(0);
break;
case USB_RECIP_ENDPOINT:
epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
hsep = &hsudc->ep[epnum];
reply = cpu_to_le16(hsep->stopped ? 1 : 0);
break;
}
INIT_LIST_HEAD(&hsreq.queue);
hsreq.req.length = 2;
hsreq.req.buf = &reply;
hsreq.req.actual = 0;
hsreq.req.complete = NULL;
s3c_hsudc_write_fifo(hsep0, &hsreq);
}
/**
* s3c_hsudc_process_setup - Process control request received on endpoint 0.
* @hsudc: Device controller on which control request has been received.
*
* Read the control request received on endpoint 0, decode it and handle
* the request.
*/
static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
{
struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
struct usb_ctrlrequest ctrl = {0};
int ret;
s3c_hsudc_nuke_ep(hsep, -EPROTO);
s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
if (ctrl.bRequestType & USB_DIR_IN) {
hsep->bEndpointAddress |= USB_DIR_IN;
hsudc->ep0state = DATA_STATE_XMIT;
} else {
hsep->bEndpointAddress &= ~USB_DIR_IN;
hsudc->ep0state = DATA_STATE_RECV;
}
switch (ctrl.bRequest) {
case USB_REQ_SET_ADDRESS:
if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
break;
hsudc->ep0state = WAIT_FOR_SETUP;
return;
case USB_REQ_GET_STATUS:
if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
break;
s3c_hsudc_process_req_status(hsudc, &ctrl);
return;
case USB_REQ_SET_FEATURE:
case USB_REQ_CLEAR_FEATURE:
if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
break;
s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
hsudc->ep0state = WAIT_FOR_SETUP;
return;
}
if (hsudc->driver) {
spin_unlock(&hsudc->lock);
ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
spin_lock(&hsudc->lock);
if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
hsep->bEndpointAddress &= ~USB_DIR_IN;
hsudc->ep0state = WAIT_FOR_SETUP;
}
if (ret < 0) {
dev_err(hsudc->dev, "setup failed, returned %d\n",
ret);
s3c_hsudc_set_halt(&hsep->ep, 1);
hsudc->ep0state = WAIT_FOR_SETUP;
hsep->bEndpointAddress &= ~USB_DIR_IN;
}
}
}
/** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
* @hsudc: Device controller on which endpoint 0 interrupt has occurred.
*
* Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
* when a stall handshake is sent to host or data is sent/received on
* endpoint 0.
*/
static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
{
struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
struct s3c_hsudc_req *hsreq;
u32 csr = readl(hsudc->regs + S3C_EP0SR);
u32 ecr;
if (csr & S3C_EP0SR_STALL) {
ecr = readl(hsudc->regs + S3C_EP0CR);
ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
writel(ecr, hsudc->regs + S3C_EP0CR);
writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
hsep->stopped = 0;
s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
hsudc->ep0state = WAIT_FOR_SETUP;
hsep->bEndpointAddress &= ~USB_DIR_IN;
return;
}
if (csr & S3C_EP0SR_TX_SUCCESS) {
writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
if (ep_is_in(hsep)) {
if (list_empty(&hsep->queue))
return;
hsreq = list_entry(hsep->queue.next,
struct s3c_hsudc_req, queue);
s3c_hsudc_write_fifo(hsep, hsreq);
}
}
if (csr & S3C_EP0SR_RX_SUCCESS) {
if (hsudc->ep0state == WAIT_FOR_SETUP)
s3c_hsudc_process_setup(hsudc);
else {
if (!ep_is_in(hsep)) {
if (list_empty(&hsep->queue))
return;
hsreq = list_entry(hsep->queue.next,
struct s3c_hsudc_req, queue);
s3c_hsudc_read_fifo(hsep, hsreq);
}
}
}
}
/**
* s3c_hsudc_ep_enable - Enable a endpoint.
* @_ep: The endpoint to be enabled.
* @desc: Endpoint descriptor.
*
* Enables a endpoint when called from the gadget driver. Endpoint stall if
* any is cleared, transfer type is configured and endpoint interrupt is
* enabled.
*/
static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
const struct usb_endpoint_descriptor *desc)
{
struct s3c_hsudc_ep *hsep;
struct s3c_hsudc *hsudc;
unsigned long flags;
u32 ecr = 0;
hsep = our_ep(_ep);
if (!_ep || !desc || _ep->name == ep0name
|| desc->bDescriptorType != USB_DT_ENDPOINT
|| hsep->bEndpointAddress != desc->bEndpointAddress
|| ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
return -EINVAL;
if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
&& usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
|| !desc->wMaxPacketSize)
return -ERANGE;
hsudc = hsep->dev;
if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
return -ESHUTDOWN;
spin_lock_irqsave(&hsudc->lock, flags);
set_index(hsudc, hsep->bEndpointAddress);
ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
writel(ecr, hsudc->regs + S3C_ECR);
hsep->stopped = hsep->wedge = 0;
hsep->ep.desc = desc;
hsep->ep.maxpacket = usb_endpoint_maxp(desc);
s3c_hsudc_set_halt(_ep, 0);
__set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
spin_unlock_irqrestore(&hsudc->lock, flags);
return 0;
}
/**
* s3c_hsudc_ep_disable - Disable a endpoint.
* @_ep: The endpoint to be disabled.
* @desc: Endpoint descriptor.
*
* Disables a endpoint when called from the gadget driver.
*/
static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
{
struct s3c_hsudc_ep *hsep = our_ep(_ep);
struct s3c_hsudc *hsudc = hsep->dev;
unsigned long flags;
if (!_ep || !hsep->ep.desc)
return -EINVAL;
spin_lock_irqsave(&hsudc->lock, flags);
set_index(hsudc, hsep->bEndpointAddress);
__clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
hsep->ep.desc = NULL;
hsep->stopped = 1;
spin_unlock_irqrestore(&hsudc->lock, flags);
return 0;
}
/**
* s3c_hsudc_alloc_request - Allocate a new request.
* @_ep: Endpoint for which request is allocated (not used).
* @gfp_flags: Flags used for the allocation.
*
* Allocates a single transfer request structure when called from gadget driver.
*/
static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
gfp_t gfp_flags)
{
struct s3c_hsudc_req *hsreq;
hsreq = kzalloc(sizeof(*hsreq), gfp_flags);
if (!hsreq)
return NULL;
INIT_LIST_HEAD(&hsreq->queue);
return &hsreq->req;
}
/**
* s3c_hsudc_free_request - Deallocate a request.
* @ep: Endpoint for which request is deallocated (not used).
* @_req: Request to be deallocated.
*
* Allocates a single transfer request structure when called from gadget driver.
*/
static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
{
struct s3c_hsudc_req *hsreq;
hsreq = our_req(_req);
WARN_ON(!list_empty(&hsreq->queue));
kfree(hsreq);
}
/**
* s3c_hsudc_queue - Queue a transfer request for the endpoint.
* @_ep: Endpoint for which the request is queued.
* @_req: Request to be queued.
* @gfp_flags: Not used.
*
* Start or enqueue a request for a endpoint when called from gadget driver.
*/
static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
gfp_t gfp_flags)
{
struct s3c_hsudc_req *hsreq;
struct s3c_hsudc_ep *hsep;
struct s3c_hsudc *hsudc;
unsigned long flags;
u32 offset;
u32 csr;
hsreq = our_req(_req);
if ((!_req || !_req->complete || !_req->buf ||
!list_empty(&hsreq->queue)))
return -EINVAL;
hsep = our_ep(_ep);
hsudc = hsep->dev;
if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
return -ESHUTDOWN;
spin_lock_irqsave(&hsudc->lock, flags);
set_index(hsudc, hsep->bEndpointAddress);
_req->status = -EINPROGRESS;
_req->actual = 0;
if (!ep_index(hsep) && _req->length == 0) {
hsudc->ep0state = WAIT_FOR_SETUP;
s3c_hsudc_complete_request(hsep, hsreq, 0);
spin_unlock_irqrestore(&hsudc->lock, flags);
return 0;
}
if (list_empty(&hsep->queue) && !hsep->stopped) {
offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
if (ep_is_in(hsep)) {
csr = readl(hsudc->regs + offset);
if (!(csr & S3C_ESR_TX_SUCCESS) &&
(s3c_hsudc_write_fifo(hsep, hsreq) == 1))
hsreq = NULL;
} else {
csr = readl(hsudc->regs + offset);
if ((csr & S3C_ESR_RX_SUCCESS)
&& (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
hsreq = NULL;
}
}
if (hsreq)
list_add_tail(&hsreq->queue, &hsep->queue);
spin_unlock_irqrestore(&hsudc->lock, flags);
return 0;
}
/**
* s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
* @_ep: Endpoint from which the request is dequeued.
* @_req: Request to be dequeued.
*
* Dequeue a request from a endpoint when called from gadget driver.
*/
static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
{
struct s3c_hsudc_ep *hsep = our_ep(_ep);
struct s3c_hsudc *hsudc = hsep->dev;
struct s3c_hsudc_req *hsreq = NULL, *iter;
unsigned long flags;
hsep = our_ep(_ep);
if (!_ep || hsep->ep.name == ep0name)
return -EINVAL;
spin_lock_irqsave(&hsudc->lock, flags);
list_for_each_entry(iter, &hsep->queue, queue) {
if (&iter->req != _req)
continue;
hsreq = iter;
break;
}
if (!hsreq) {
spin_unlock_irqrestore(&hsudc->lock, flags);
return -EINVAL;
}
set_index(hsudc, hsep->bEndpointAddress);
s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
spin_unlock_irqrestore(&hsudc->lock, flags);
return 0;
}
static const struct usb_ep_ops s3c_hsudc_ep_ops = {
.enable = s3c_hsudc_ep_enable,
.disable = s3c_hsudc_ep_disable,
.alloc_request = s3c_hsudc_alloc_request,
.free_request = s3c_hsudc_free_request,
.queue = s3c_hsudc_queue,
.dequeue = s3c_hsudc_dequeue,
.set_halt = s3c_hsudc_set_halt,
.set_wedge = s3c_hsudc_set_wedge,
};
/**
* s3c_hsudc_initep - Initialize a endpoint to default state.
* @hsudc - Reference to the device controller.
* @hsep - Endpoint to be initialized.
* @epnum - Address to be assigned to the endpoint.
*
* Initialize a endpoint with default configuration.
*/
static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
struct s3c_hsudc_ep *hsep, int epnum)
{
char *dir;
if ((epnum % 2) == 0) {
dir = "out";
} else {
dir = "in";
hsep->bEndpointAddress = USB_DIR_IN;
}
hsep->bEndpointAddress |= epnum;
if (epnum)
snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
else
snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
INIT_LIST_HEAD(&hsep->queue);
INIT_LIST_HEAD(&hsep->ep.ep_list);
if (epnum)
list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
hsep->dev = hsudc;
hsep->ep.name = hsep->name;
usb_ep_set_maxpacket_limit(&hsep->ep, epnum ? 512 : 64);
hsep->ep.ops = &s3c_hsudc_ep_ops;
hsep->fifo = hsudc->regs + S3C_BR(epnum);
hsep->ep.desc = NULL;
hsep->stopped = 0;
hsep->wedge = 0;
if (epnum == 0) {
hsep->ep.caps.type_control = true;
hsep->ep.caps.dir_in = true;
hsep->ep.caps.dir_out = true;
} else {
hsep->ep.caps.type_iso = true;
hsep->ep.caps.type_bulk = true;
hsep->ep.caps.type_int = true;
}
if (epnum & 1)
hsep->ep.caps.dir_in = true;
else
hsep->ep.caps.dir_out = true;
set_index(hsudc, epnum);
writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
}
/**
* s3c_hsudc_setup_ep - Configure all endpoints to default state.
* @hsudc: Reference to device controller.
*
* Configures all endpoints to default state.
*/
static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
{
int epnum;
hsudc->ep0state = WAIT_FOR_SETUP;
INIT_LIST_HEAD(&hsudc->gadget.ep_list);
for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
}
/**
* s3c_hsudc_reconfig - Reconfigure the device controller to default state.
* @hsudc: Reference to device controller.
*
* Reconfigures the device controller registers to a default state.
*/
static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
{
writel(0xAA, hsudc->regs + S3C_EDR);
writel(1, hsudc->regs + S3C_EIER);
writel(0, hsudc->regs + S3C_TR);
writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
writel(0, hsudc->regs + S3C_EP0CR);
s3c_hsudc_setup_ep(hsudc);
}
/**
* s3c_hsudc_irq - Interrupt handler for device controller.
* @irq: Not used.
* @_dev: Reference to the device controller.
*
* Interrupt handler for the device controller. This handler handles controller
* interrupts and endpoint interrupts.
*/
static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
{
struct s3c_hsudc *hsudc = _dev;
struct s3c_hsudc_ep *hsep;
u32 ep_intr;
u32 sys_status;
u32 ep_idx;
spin_lock(&hsudc->lock);
sys_status = readl(hsudc->regs + S3C_SSR);
ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
spin_unlock(&hsudc->lock);
return IRQ_HANDLED;
}
if (sys_status) {
if (sys_status & S3C_SSR_VBUSON)
writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
if (sys_status & S3C_SSR_ERR)
writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
if (sys_status & S3C_SSR_SDE) {
writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
USB_SPEED_HIGH : USB_SPEED_FULL;
}
if (sys_status & S3C_SSR_SUSPEND) {
writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
&& hsudc->driver && hsudc->driver->suspend)
hsudc->driver->suspend(&hsudc->gadget);
}
if (sys_status & S3C_SSR_RESUME) {
writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
&& hsudc->driver && hsudc->driver->resume)
hsudc->driver->resume(&hsudc->gadget);
}
if (sys_status & S3C_SSR_RESET) {
writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
hsep = &hsudc->ep[ep_idx];
hsep->stopped = 1;
s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
}
s3c_hsudc_reconfig(hsudc);
hsudc->ep0state = WAIT_FOR_SETUP;
}
}
if (ep_intr & S3C_EIR_EP0) {
writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
set_index(hsudc, 0);
s3c_hsudc_handle_ep0_intr(hsudc);
}
ep_intr >>= 1;
ep_idx = 1;
while (ep_intr) {
if (ep_intr & 1) {
hsep = &hsudc->ep[ep_idx];
set_index(hsudc, ep_idx);
writel(1 << ep_idx, hsudc->regs + S3C_EIR);
if (ep_is_in(hsep))
s3c_hsudc_epin_intr(hsudc, ep_idx);
else
s3c_hsudc_epout_intr(hsudc, ep_idx);
}
ep_intr >>= 1;
ep_idx++;
}
spin_unlock(&hsudc->lock);
return IRQ_HANDLED;
}
static int s3c_hsudc_start(struct usb_gadget *gadget,
struct usb_gadget_driver *driver)
{
struct s3c_hsudc *hsudc = to_hsudc(gadget);
int ret;
if (!driver
|| driver->max_speed < USB_SPEED_FULL
|| !driver->setup)
return -EINVAL;
if (!hsudc)
return -ENODEV;
if (hsudc->driver)
return -EBUSY;
hsudc->driver = driver;
ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
hsudc->supplies);
if (ret != 0) {
dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
goto err_supplies;
}
/* connect to bus through transceiver */
if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
ret = otg_set_peripheral(hsudc->transceiver->otg,
&hsudc->gadget);
if (ret) {
dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
hsudc->gadget.name);
goto err_otg;
}
}
enable_irq(hsudc->irq);
s3c_hsudc_reconfig(hsudc);
pm_runtime_get_sync(hsudc->dev);
if (hsudc->pd->phy_init)
hsudc->pd->phy_init();
if (hsudc->pd->gpio_init)
hsudc->pd->gpio_init();
return 0;
err_otg:
regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
err_supplies:
hsudc->driver = NULL;
return ret;
}
static int s3c_hsudc_stop(struct usb_gadget *gadget)
{
struct s3c_hsudc *hsudc = to_hsudc(gadget);
unsigned long flags;
if (!hsudc)
return -ENODEV;
spin_lock_irqsave(&hsudc->lock, flags);
hsudc->gadget.speed = USB_SPEED_UNKNOWN;
if (hsudc->pd->phy_uninit)
hsudc->pd->phy_uninit();
pm_runtime_put(hsudc->dev);
if (hsudc->pd->gpio_uninit)
hsudc->pd->gpio_uninit();
s3c_hsudc_stop_activity(hsudc);
spin_unlock_irqrestore(&hsudc->lock, flags);
if (!IS_ERR_OR_NULL(hsudc->transceiver))
(void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
disable_irq(hsudc->irq);
regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
hsudc->driver = NULL;
return 0;
}
static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
{
return readl(hsudc->regs + S3C_FNR) & 0x3FF;
}
static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
{
return s3c_hsudc_read_frameno(to_hsudc(gadget));
}
static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
{
struct s3c_hsudc *hsudc = to_hsudc(gadget);
if (!hsudc)
return -ENODEV;
if (!IS_ERR_OR_NULL(hsudc->transceiver))
return usb_phy_set_power(hsudc->transceiver, mA);
return -EOPNOTSUPP;
}
static const struct usb_gadget_ops s3c_hsudc_gadget_ops = {
.get_frame = s3c_hsudc_gadget_getframe,
.udc_start = s3c_hsudc_start,
.udc_stop = s3c_hsudc_stop,
.vbus_draw = s3c_hsudc_vbus_draw,
};
static int s3c_hsudc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct s3c_hsudc *hsudc;
struct s3c24xx_hsudc_platdata *pd = dev_get_platdata(&pdev->dev);
int ret, i;
hsudc = devm_kzalloc(&pdev->dev, struct_size(hsudc, ep, pd->epnum),
GFP_KERNEL);
if (!hsudc)
return -ENOMEM;
platform_set_drvdata(pdev, dev);
hsudc->dev = dev;
hsudc->pd = dev_get_platdata(&pdev->dev);
hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
hsudc->supplies);
if (ret != 0) {
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to request supplies: %d\n", ret);
goto err_supplies;
}
hsudc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hsudc->regs)) {
ret = PTR_ERR(hsudc->regs);
goto err_res;
}
spin_lock_init(&hsudc->lock);
hsudc->gadget.max_speed = USB_SPEED_HIGH;
hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
hsudc->gadget.name = dev_name(dev);
hsudc->gadget.ep0 = &hsudc->ep[0].ep;
hsudc->gadget.is_otg = 0;
hsudc->gadget.is_a_peripheral = 0;
hsudc->gadget.speed = USB_SPEED_UNKNOWN;
s3c_hsudc_setup_ep(hsudc);
ret = platform_get_irq(pdev, 0);
if (ret < 0)
goto err_res;
hsudc->irq = ret;
ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0,
driver_name, hsudc);
if (ret < 0) {
dev_err(dev, "irq request failed\n");
goto err_res;
}
hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device");
if (IS_ERR(hsudc->uclk)) {
dev_err(dev, "failed to find usb-device clock source\n");
ret = PTR_ERR(hsudc->uclk);
goto err_res;
}
clk_enable(hsudc->uclk);
local_irq_disable();
disable_irq(hsudc->irq);
local_irq_enable();
ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
if (ret)
goto err_add_udc;
pm_runtime_enable(dev);
return 0;
err_add_udc:
clk_disable(hsudc->uclk);
err_res:
if (!IS_ERR_OR_NULL(hsudc->transceiver))
usb_put_phy(hsudc->transceiver);
err_supplies:
return ret;
}
static struct platform_driver s3c_hsudc_driver = {
.driver = {
.name = "s3c-hsudc",
},
.probe = s3c_hsudc_probe,
};
module_platform_driver(s3c_hsudc_driver);
MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:s3c-hsudc");
drivers/usb/gadget/udc/s3c2410_udc.c deleted 100644 → 0
View file @ 7d1ec119
// SPDX-License-Identifier: GPL-2.0+
/*
* linux/drivers/usb/gadget/s3c2410_udc.c
*
* Samsung S3C24xx series on-chip full speed USB device controllers
*
* Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
* Additional cleanups by Ben Dooks <ben-linux@fluff.org>
*/
#define pr_fmt(fmt) "s3c2410_udc: " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/timer.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/prefetch.h>
#include <linux/io.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/usb.h>
#include <linux/usb/gadget.h>
#include <asm/byteorder.h>
#include <asm/irq.h>
#include <asm/unaligned.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include "s3c2410_udc.h"
#include "s3c2410_udc_regs.h"
#define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
#define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
"Arnaud Patard <arnaud.patard@rtp-net.org>"
static const char gadget_name[] = "s3c2410_udc";
static const char driver_desc[] = DRIVER_DESC;
static struct s3c2410_udc *the_controller;
static struct clk *udc_clock;
static struct clk *usb_bus_clock;
static void __iomem *base_addr;
static int irq_usbd;
static struct dentry *s3c2410_udc_debugfs_root;
static inline u32 udc_read(u32 reg)
{
return readb(base_addr + reg);
}
static inline void udc_write(u32 value, u32 reg)
{
writeb(value, base_addr + reg);
}
static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
{
writeb(value, base + reg);
}
static struct s3c2410_udc_mach_info *udc_info;
/*************************** DEBUG FUNCTION ***************************/
#define DEBUG_NORMAL 1
#define DEBUG_VERBOSE 2
#ifdef CONFIG_USB_S3C2410_DEBUG
#define USB_S3C2410_DEBUG_LEVEL 0
static uint32_t s3c2410_ticks = 0;
__printf(2, 3)
static void dprintk(int level, const char *fmt, ...)
{
static long prevticks;
static int invocation;
struct va_format vaf;
va_list args;
if (level > USB_S3C2410_DEBUG_LEVEL)
return;
va_start(args, fmt);
vaf.fmt = fmt;
vaf.va = &args;
if (s3c2410_ticks != prevticks) {
prevticks = s3c2410_ticks;
invocation = 0;
}
pr_debug("%1lu.%02d USB: %pV", prevticks, invocation++, &vaf);
va_end(args);
}
#else
__printf(2, 3)
static void dprintk(int level, const char *fmt, ...)
{
}
#endif
static int s3c2410_udc_debugfs_show(struct seq_file *m, void *p)
{
u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg;
u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
u32 ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2;
u32 ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2;
addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
udc_write(0, S3C2410_UDC_INDEX_REG);
ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
udc_write(1, S3C2410_UDC_INDEX_REG);
ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
udc_write(2, S3C2410_UDC_INDEX_REG);
ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
"PWR_REG : 0x%04X\n"
"EP_INT_REG : 0x%04X\n"
"USB_INT_REG : 0x%04X\n"
"EP_INT_EN_REG : 0x%04X\n"
"USB_INT_EN_REG : 0x%04X\n"
"EP0_CSR : 0x%04X\n"
"EP1_I_CSR1 : 0x%04X\n"
"EP1_I_CSR2 : 0x%04X\n"
"EP1_O_CSR1 : 0x%04X\n"
"EP1_O_CSR2 : 0x%04X\n"
"EP2_I_CSR1 : 0x%04X\n"
"EP2_I_CSR2 : 0x%04X\n"
"EP2_O_CSR1 : 0x%04X\n"
"EP2_O_CSR2 : 0x%04X\n",
addr_reg, pwr_reg, ep_int_reg, usb_int_reg,
ep_int_en_reg, usb_int_en_reg, ep0_csr,
ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2,
ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2
);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(s3c2410_udc_debugfs);
/* io macros */
static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
{
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
S3C2410_UDC_EP0_CSR_REG);
}
static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
{
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
}
static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
{
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
}
static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
{
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
}
static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
{
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
}
static inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
{
udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
}
static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
{
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
| S3C2410_UDC_EP0_CSR_DE),
S3C2410_UDC_EP0_CSR_REG);
}
static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
{
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
| S3C2410_UDC_EP0_CSR_DE),
S3C2410_UDC_EP0_CSR_REG);
}
/*------------------------- I/O ----------------------------------*/
/*
* s3c2410_udc_done
*/
static void s3c2410_udc_done(struct s3c2410_ep *ep,
struct s3c2410_request *req, int status)
{
unsigned halted = ep->halted;
list_del_init(&req->queue);
if (likely(req->req.status == -EINPROGRESS))
req->req.status = status;
else
status = req->req.status;
ep->halted = 1;
usb_gadget_giveback_request(&ep->ep, &req->req);
ep->halted = halted;
}
static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
struct s3c2410_ep *ep, int status)
{
while (!list_empty(&ep->queue)) {
struct s3c2410_request *req;
req = list_entry(ep->queue.next, struct s3c2410_request,
queue);
s3c2410_udc_done(ep, req, status);
}
}
static inline int s3c2410_udc_fifo_count_out(void)
{
int tmp;
tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
return tmp;
}
/*
* s3c2410_udc_write_packet
*/
static inline int s3c2410_udc_write_packet(int fifo,
struct s3c2410_request *req,
unsigned max)
{
unsigned len = min(req->req.length - req->req.actual, max);
u8 *buf = req->req.buf + req->req.actual;
prefetch(buf);
dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
req->req.actual, req->req.length, len, req->req.actual + len);
req->req.actual += len;
udelay(5);
writesb(base_addr + fifo, buf, len);
return len;
}
/*
* s3c2410_udc_write_fifo
*
* return: 0 = still running, 1 = completed, negative = errno
*/
static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
struct s3c2410_request *req)
{
unsigned count;
int is_last;
u32 idx;
int fifo_reg;
u32 ep_csr;
idx = ep->bEndpointAddress & 0x7F;
switch (idx) {
default:
idx = 0;
fallthrough;
case 0:
fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
break;
case 1:
fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
break;
case 2:
fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
break;
case 3:
fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
break;
case 4:
fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
break;
}
count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
/* last packet is often short (sometimes a zlp) */
if (count != ep->ep.maxpacket)
is_last = 1;
else if (req->req.length != req->req.actual || req->req.zero)
is_last = 0;
else
is_last = 2;
/* Only ep0 debug messages are interesting */
if (idx == 0)
dprintk(DEBUG_NORMAL,
"Written ep%d %d.%d of %d b [last %d,z %d]\n",
idx, count, req->req.actual, req->req.length,
is_last, req->req.zero);
if (is_last) {
/* The order is important. It prevents sending 2 packets
* at the same time */
if (idx == 0) {
/* Reset signal => no need to say 'data sent' */
if (!(udc_read(S3C2410_UDC_USB_INT_REG)
& S3C2410_UDC_USBINT_RESET))
s3c2410_udc_set_ep0_de_in(base_addr);
ep->dev->ep0state = EP0_IDLE;
} else {
udc_write(idx, S3C2410_UDC_INDEX_REG);
ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
udc_write(idx, S3C2410_UDC_INDEX_REG);
udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
S3C2410_UDC_IN_CSR1_REG);
}
s3c2410_udc_done(ep, req, 0);
is_last = 1;
} else {
if (idx == 0) {
/* Reset signal => no need to say 'data sent' */
if (!(udc_read(S3C2410_UDC_USB_INT_REG)
& S3C2410_UDC_USBINT_RESET))
s3c2410_udc_set_ep0_ipr(base_addr);
} else {
udc_write(idx, S3C2410_UDC_INDEX_REG);
ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
udc_write(idx, S3C2410_UDC_INDEX_REG);
udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
S3C2410_UDC_IN_CSR1_REG);
}
}
return is_last;
}
static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
struct s3c2410_request *req, unsigned avail)
{
unsigned len;
len = min(req->req.length - req->req.actual, avail);
req->req.actual += len;
readsb(fifo + base_addr, buf, len);
return len;
}
/*
* return: 0 = still running, 1 = queue empty, negative = errno
*/
static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
struct s3c2410_request *req)
{
u8 *buf;
u32 ep_csr;
unsigned bufferspace;
int is_last = 1;
unsigned avail;
int fifo_count = 0;
u32 idx;
int fifo_reg;
idx = ep->bEndpointAddress & 0x7F;
switch (idx) {
default:
idx = 0;
fallthrough;
case 0:
fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
break;
case 1:
fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
break;
case 2:
fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
break;
case 3:
fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
break;
case 4:
fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
break;
}
if (!req->req.length)
return 1;
buf = req->req.buf + req->req.actual;
bufferspace = req->req.length - req->req.actual;
if (!bufferspace) {
dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
return -1;
}
udc_write(idx, S3C2410_UDC_INDEX_REG);
fifo_count = s3c2410_udc_fifo_count_out();
dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
if (fifo_count > ep->ep.maxpacket)
avail = ep->ep.maxpacket;
else
avail = fifo_count;
fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
/* checking this with ep0 is not accurate as we already
* read a control request
**/
if (idx != 0 && fifo_count < ep->ep.maxpacket) {
is_last = 1;
/* overflowed this request? flush extra data */
if (fifo_count != avail)
req->req.status = -EOVERFLOW;
} else {
is_last = (req->req.length <= req->req.actual) ? 1 : 0;
}
udc_write(idx, S3C2410_UDC_INDEX_REG);
fifo_count = s3c2410_udc_fifo_count_out();
/* Only ep0 debug messages are interesting */
if (idx == 0)
dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
__func__, fifo_count, is_last);
if (is_last) {
if (idx == 0) {
s3c2410_udc_set_ep0_de_out(base_addr);
ep->dev->ep0state = EP0_IDLE;
} else {
udc_write(idx, S3C2410_UDC_INDEX_REG);
ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
udc_write(idx, S3C2410_UDC_INDEX_REG);
udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
S3C2410_UDC_OUT_CSR1_REG);
}
s3c2410_udc_done(ep, req, 0);
} else {
if (idx == 0) {
s3c2410_udc_clear_ep0_opr(base_addr);
} else {
udc_write(idx, S3C2410_UDC_INDEX_REG);
ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
udc_write(idx, S3C2410_UDC_INDEX_REG);
udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
S3C2410_UDC_OUT_CSR1_REG);
}
}
return is_last;
}
static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
{
unsigned char *outbuf = (unsigned char *)crq;
int bytes_read = 0;
udc_write(0, S3C2410_UDC_INDEX_REG);
bytes_read = s3c2410_udc_fifo_count_out();
dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
if (bytes_read > sizeof(struct usb_ctrlrequest))
bytes_read = sizeof(struct usb_ctrlrequest);
readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
bytes_read, crq->bRequest, crq->bRequestType,
crq->wValue, crq->wIndex, crq->wLength);
return bytes_read;
}
static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
struct usb_ctrlrequest *crq)
{
u16 status = 0;
u8 ep_num = crq->wIndex & 0x7F;
u8 is_in = crq->wIndex & USB_DIR_IN;
switch (crq->bRequestType & USB_RECIP_MASK) {
case USB_RECIP_INTERFACE:
break;
case USB_RECIP_DEVICE:
status = dev->devstatus;
break;
case USB_RECIP_ENDPOINT:
if (ep_num > 4 || crq->wLength > 2)
return 1;
if (ep_num == 0) {
udc_write(0, S3C2410_UDC_INDEX_REG);
status = udc_read(S3C2410_UDC_IN_CSR1_REG);
status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
} else {
udc_write(ep_num, S3C2410_UDC_INDEX_REG);
if (is_in) {
status = udc_read(S3C2410_UDC_IN_CSR1_REG);
status = status & S3C2410_UDC_ICSR1_SENDSTL;
} else {
status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
status = status & S3C2410_UDC_OCSR1_SENDSTL;
}
}
status = status ? 1 : 0;
break;
default:
return 1;
}
/* Seems to be needed to get it working. ouch :( */
udelay(5);
udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
s3c2410_udc_set_ep0_de_in(base_addr);
return 0;
}
/*------------------------- usb state machine -------------------------------*/
static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
struct s3c2410_ep *ep,
struct usb_ctrlrequest *crq,
u32 ep0csr)
{
int len, ret, tmp;
/* start control request? */
if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
return;
s3c2410_udc_nuke(dev, ep, -EPROTO);
len = s3c2410_udc_read_fifo_crq(crq);
if (len != sizeof(*crq)) {
dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
" wanted %d bytes got %d. Stalling out...\n",
sizeof(*crq), len);
s3c2410_udc_set_ep0_ss(base_addr);
return;
}
dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
crq->bRequest, crq->bRequestType, crq->wLength);
/* cope with automagic for some standard requests. */
dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
== USB_TYPE_STANDARD;
dev->req_config = 0;
dev->req_pending = 1;
switch (crq->bRequest) {
case USB_REQ_SET_CONFIGURATION:
dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ...\n");
if (crq->bRequestType == USB_RECIP_DEVICE) {
dev->req_config = 1;
s3c2410_udc_set_ep0_de_out(base_addr);
}
break;
case USB_REQ_SET_INTERFACE:
dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ...\n");
if (crq->bRequestType == USB_RECIP_INTERFACE) {
dev->req_config = 1;
s3c2410_udc_set_ep0_de_out(base_addr);
}
break;
case USB_REQ_SET_ADDRESS:
dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ...\n");
if (crq->bRequestType == USB_RECIP_DEVICE) {
tmp = crq->wValue & 0x7F;
dev->address = tmp;
udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
S3C2410_UDC_FUNC_ADDR_REG);
s3c2410_udc_set_ep0_de_out(base_addr);
return;
}
break;
case USB_REQ_GET_STATUS:
dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ...\n");
s3c2410_udc_clear_ep0_opr(base_addr);
if (dev->req_std) {
if (!s3c2410_udc_get_status(dev, crq))
return;
}
break;
case USB_REQ_CLEAR_FEATURE:
s3c2410_udc_clear_ep0_opr(base_addr);
if (crq->bRequestType != USB_RECIP_ENDPOINT)
break;
if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
break;
s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
s3c2410_udc_set_ep0_de_out(base_addr);
return;
case USB_REQ_SET_FEATURE:
s3c2410_udc_clear_ep0_opr(base_addr);
if (crq->bRequestType != USB_RECIP_ENDPOINT)
break;
if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
break;
s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
s3c2410_udc_set_ep0_de_out(base_addr);
return;
default:
s3c2410_udc_clear_ep0_opr(base_addr);
break;
}
if (crq->bRequestType & USB_DIR_IN)
dev->ep0state = EP0_IN_DATA_PHASE;
else
dev->ep0state = EP0_OUT_DATA_PHASE;
if (!dev->driver)
return;
/* deliver the request to the gadget driver */
ret = dev->driver->setup(&dev->gadget, crq);
if (ret < 0) {
if (dev->req_config) {
dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
crq->bRequest, ret);
return;
}
if (ret == -EOPNOTSUPP)
dprintk(DEBUG_NORMAL, "Operation not supported\n");
else
dprintk(DEBUG_NORMAL,
"dev->driver->setup failed. (%d)\n", ret);
udelay(5);
s3c2410_udc_set_ep0_ss(base_addr);
s3c2410_udc_set_ep0_de_out(base_addr);
dev->ep0state = EP0_IDLE;
/* deferred i/o == no response yet */
} else if (dev->req_pending) {
dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
dev->req_pending = 0;
}
dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
}
static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
{
u32 ep0csr;
struct s3c2410_ep *ep = &dev->ep[0];
struct s3c2410_request *req;
struct usb_ctrlrequest crq;
if (list_empty(&ep->queue))
req = NULL;
else
req = list_entry(ep->queue.next, struct s3c2410_request, queue);
/* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
* S3C2410_UDC_EP0_CSR_REG when index is zero */
udc_write(0, S3C2410_UDC_INDEX_REG);
ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
ep0csr, ep0states[dev->ep0state]);
/* clear stall status */
if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
s3c2410_udc_nuke(dev, ep, -EPIPE);
dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
s3c2410_udc_clear_ep0_sst(base_addr);
dev->ep0state = EP0_IDLE;
return;
}
/* clear setup end */
if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
s3c2410_udc_nuke(dev, ep, 0);
s3c2410_udc_clear_ep0_se(base_addr);
dev->ep0state = EP0_IDLE;
}
switch (dev->ep0state) {
case EP0_IDLE:
s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
break;
case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req)
s3c2410_udc_write_fifo(ep, req);
break;
case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req)
s3c2410_udc_read_fifo(ep, req);
break;
case EP0_END_XFER:
dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
dev->ep0state = EP0_IDLE;
break;
case EP0_STALL:
dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
dev->ep0state = EP0_IDLE;
break;
}
}
/*
* handle_ep - Manage I/O endpoints
*/
static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
{
struct s3c2410_request *req;
int is_in = ep->bEndpointAddress & USB_DIR_IN;
u32 ep_csr1;
u32 idx;
if (likely(!list_empty(&ep->queue)))
req = list_entry(ep->queue.next,
struct s3c2410_request, queue);
else
req = NULL;
idx = ep->bEndpointAddress & 0x7F;
if (is_in) {
udc_write(idx, S3C2410_UDC_INDEX_REG);
ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
idx, ep_csr1, req ? 1 : 0);
if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
dprintk(DEBUG_VERBOSE, "st\n");
udc_write(idx, S3C2410_UDC_INDEX_REG);
udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
S3C2410_UDC_IN_CSR1_REG);
return;
}
if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req)
s3c2410_udc_write_fifo(ep, req);
} else {
udc_write(idx, S3C2410_UDC_INDEX_REG);
ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
udc_write(idx, S3C2410_UDC_INDEX_REG);
udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
S3C2410_UDC_OUT_CSR1_REG);
return;
}
if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req)
s3c2410_udc_read_fifo(ep, req);
}
}
/*
* s3c2410_udc_irq - interrupt handler
*/
static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
{
struct s3c2410_udc *dev = _dev;
int usb_status;
int usbd_status;
int pwr_reg;
int ep0csr;
int i;
u32 idx, idx2;
unsigned long flags;
spin_lock_irqsave(&dev->lock, flags);
/* Driver connected ? */
if (!dev->driver) {
/* Clear interrupts */
udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
S3C2410_UDC_USB_INT_REG);
udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
S3C2410_UDC_EP_INT_REG);
}
/* Save index */
idx = udc_read(S3C2410_UDC_INDEX_REG);
/* Read status registers */
usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
usb_status, usbd_status, pwr_reg, ep0csr);
/*
* Now, handle interrupts. There's two types :
* - Reset, Resume, Suspend coming -> usb_int_reg
* - EP -> ep_int_reg
*/
/* RESET */
if (usb_status & S3C2410_UDC_USBINT_RESET) {
/* two kind of reset :
* - reset start -> pwr reg = 8
* - reset end -> pwr reg = 0
**/
dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
ep0csr, pwr_reg);
dev->gadget.speed = USB_SPEED_UNKNOWN;
udc_write(0x00, S3C2410_UDC_INDEX_REG);
udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
S3C2410_UDC_MAXP_REG);
dev->address = 0;
dev->ep0state = EP0_IDLE;
dev->gadget.speed = USB_SPEED_FULL;
/* clear interrupt */
udc_write(S3C2410_UDC_USBINT_RESET,
S3C2410_UDC_USB_INT_REG);
udc_write(idx, S3C2410_UDC_INDEX_REG);
spin_unlock_irqrestore(&dev->lock, flags);
return IRQ_HANDLED;
}
/* RESUME */
if (usb_status & S3C2410_UDC_USBINT_RESUME) {
dprintk(DEBUG_NORMAL, "USB resume\n");
/* clear interrupt */
udc_write(S3C2410_UDC_USBINT_RESUME,
S3C2410_UDC_USB_INT_REG);
if (dev->gadget.speed != USB_SPEED_UNKNOWN
&& dev->driver
&& dev->driver->resume)
dev->driver->resume(&dev->gadget);
}
/* SUSPEND */
if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
dprintk(DEBUG_NORMAL, "USB suspend\n");
/* clear interrupt */
udc_write(S3C2410_UDC_USBINT_SUSPEND,
S3C2410_UDC_USB_INT_REG);
if (dev->gadget.speed != USB_SPEED_UNKNOWN
&& dev->driver
&& dev->driver->suspend)
dev->driver->suspend(&dev->gadget);
dev->ep0state = EP0_IDLE;
}
/* EP */
/* control traffic */
/* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
* generate an interrupt
*/
if (usbd_status & S3C2410_UDC_INT_EP0) {
dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
/* Clear the interrupt bit by setting it to 1 */
udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
s3c2410_udc_handle_ep0(dev);
}
/* endpoint data transfers */
for (i = 1; i < S3C2410_ENDPOINTS; i++) {
u32 tmp = 1 << i;
if (usbd_status & tmp) {
dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
/* Clear the interrupt bit by setting it to 1 */
udc_write(tmp, S3C2410_UDC_EP_INT_REG);
s3c2410_udc_handle_ep(&dev->ep[i]);
}
}
/* what else causes this interrupt? a receive! who is it? */
if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
for (i = 1; i < S3C2410_ENDPOINTS; i++) {
idx2 = udc_read(S3C2410_UDC_INDEX_REG);
udc_write(i, S3C2410_UDC_INDEX_REG);
if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
s3c2410_udc_handle_ep(&dev->ep[i]);
/* restore index */
udc_write(idx2, S3C2410_UDC_INDEX_REG);
}
}
dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", irq_usbd);
/* Restore old index */
udc_write(idx, S3C2410_UDC_INDEX_REG);
spin_unlock_irqrestore(&dev->lock, flags);
return IRQ_HANDLED;
}
/*------------------------- s3c2410_ep_ops ----------------------------------*/
static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
{
return container_of(ep, struct s3c2410_ep, ep);
}
static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
{
return container_of(gadget, struct s3c2410_udc, gadget);
}
static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
{
return container_of(req, struct s3c2410_request, req);
}
/*
* s3c2410_udc_ep_enable
*/
static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
const struct usb_endpoint_descriptor *desc)
{
struct s3c2410_udc *dev;
struct s3c2410_ep *ep;
u32 max, tmp;
unsigned long flags;
u32 csr1, csr2;
u32 int_en_reg;
ep = to_s3c2410_ep(_ep);
if (!_ep || !desc
|| _ep->name == ep0name
|| desc->bDescriptorType != USB_DT_ENDPOINT)
return -EINVAL;
dev = ep->dev;
if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
return -ESHUTDOWN;
max = usb_endpoint_maxp(desc);
local_irq_save(flags);
_ep->maxpacket = max;
ep->ep.desc = desc;
ep->halted = 0;
ep->bEndpointAddress = desc->bEndpointAddress;
/* set max packet */
udc_write(ep->num, S3C2410_UDC_INDEX_REG);
udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
/* set type, direction, address; reset fifo counters */
if (desc->bEndpointAddress & USB_DIR_IN) {
csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
udc_write(ep->num, S3C2410_UDC_INDEX_REG);
udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
udc_write(ep->num, S3C2410_UDC_INDEX_REG);
udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
} else {
/* don't flush in fifo or it will cause endpoint interrupt */
csr1 = S3C2410_UDC_ICSR1_CLRDT;
csr2 = S3C2410_UDC_ICSR2_DMAIEN;
udc_write(ep->num, S3C2410_UDC_INDEX_REG);
udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
udc_write(ep->num, S3C2410_UDC_INDEX_REG);
udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
csr2 = S3C2410_UDC_OCSR2_DMAIEN;
udc_write(ep->num, S3C2410_UDC_INDEX_REG);
udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
udc_write(ep->num, S3C2410_UDC_INDEX_REG);
udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
}
/* enable irqs */
int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
/* print some debug message */
tmp = desc->bEndpointAddress;
dprintk(DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
_ep->name, ep->num, tmp,
desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
local_irq_restore(flags);
s3c2410_udc_set_halt(_ep, 0);
return 0;
}
/*
* s3c2410_udc_ep_disable
*/
static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
{
struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
unsigned long flags;
u32 int_en_reg;
if (!_ep || !ep->ep.desc) {
dprintk(DEBUG_NORMAL, "%s not enabled\n",
_ep ? ep->ep.name : NULL);
return -EINVAL;
}
local_irq_save(flags);
dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
ep->ep.desc = NULL;
ep->halted = 1;
s3c2410_udc_nuke(ep->dev, ep, -ESHUTDOWN);
/* disable irqs */
int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
local_irq_restore(flags);
dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
return 0;
}
/*
* s3c2410_udc_alloc_request
*/
static struct usb_request *
s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
{
struct s3c2410_request *req;
dprintk(DEBUG_VERBOSE, "%s(%p,%d)\n", __func__, _ep, mem_flags);
if (!_ep)
return NULL;
req = kzalloc(sizeof(struct s3c2410_request), mem_flags);
if (!req)
return NULL;
INIT_LIST_HEAD(&req->queue);
return &req->req;
}
/*
* s3c2410_udc_free_request
*/
static void
s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
{
struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
struct s3c2410_request *req = to_s3c2410_req(_req);
dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
if (!ep || !_req || (!ep->ep.desc && _ep->name != ep0name))
return;
WARN_ON(!list_empty(&req->queue));
kfree(req);
}
/*
* s3c2410_udc_queue
*/
static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
gfp_t gfp_flags)
{
struct s3c2410_request *req = to_s3c2410_req(_req);
struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
struct s3c2410_udc *dev;
u32 ep_csr = 0;
int fifo_count = 0;
unsigned long flags;
if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
return -EINVAL;
}
dev = ep->dev;
if (unlikely(!dev->driver
|| dev->gadget.speed == USB_SPEED_UNKNOWN)) {
return -ESHUTDOWN;
}
local_irq_save(flags);
if (unlikely(!_req || !_req->complete
|| !_req->buf || !list_empty(&req->queue))) {
if (!_req)
dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
else {
dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
__func__, !_req->complete, !_req->buf,
!list_empty(&req->queue));
}
local_irq_restore(flags);
return -EINVAL;
}
_req->status = -EINPROGRESS;
_req->actual = 0;
dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
__func__, ep->bEndpointAddress, _req->length);
if (ep->bEndpointAddress) {
udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
? S3C2410_UDC_IN_CSR1_REG
: S3C2410_UDC_OUT_CSR1_REG);
fifo_count = s3c2410_udc_fifo_count_out();
} else {
udc_write(0, S3C2410_UDC_INDEX_REG);
ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
fifo_count = s3c2410_udc_fifo_count_out();
}
/* kickstart this i/o queue? */
if (list_empty(&ep->queue) && !ep->halted) {
if (ep->bEndpointAddress == 0 /* ep0 */) {
switch (dev->ep0state) {
case EP0_IN_DATA_PHASE:
if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
&& s3c2410_udc_write_fifo(ep,
req)) {
dev->ep0state = EP0_IDLE;
req = NULL;
}
break;
case EP0_OUT_DATA_PHASE:
if ((!_req->length)
|| ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
&& s3c2410_udc_read_fifo(ep,
req))) {
dev->ep0state = EP0_IDLE;
req = NULL;
}
break;
default:
local_irq_restore(flags);
return -EL2HLT;
}
} else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
&& (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
&& s3c2410_udc_write_fifo(ep, req)) {
req = NULL;
} else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
&& fifo_count
&& s3c2410_udc_read_fifo(ep, req)) {
req = NULL;
}
}
/* pio or dma irq handler advances the queue. */
if (likely(req))
list_add_tail(&req->queue, &ep->queue);
local_irq_restore(flags);
dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
return 0;
}
/*
* s3c2410_udc_dequeue
*/
static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
{
struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
int retval = -EINVAL;
unsigned long flags;
struct s3c2410_request *req = NULL, *iter;
dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
if (!the_controller->driver)
return -ESHUTDOWN;
if (!_ep || !_req)
return retval;
local_irq_save(flags);
list_for_each_entry(iter, &ep->queue, queue) {
if (&iter->req != _req)
continue;
list_del_init(&iter->queue);
_req->status = -ECONNRESET;
req = iter;
retval = 0;
break;
}
if (retval == 0) {
dprintk(DEBUG_VERBOSE,
"dequeued req %p from %s, len %d buf %p\n",
req, _ep->name, _req->length, _req->buf);
s3c2410_udc_done(ep, req, -ECONNRESET);
}
local_irq_restore(flags);
return retval;
}
/*
* s3c2410_udc_set_halt
*/
static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
{
struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
u32 ep_csr = 0;
unsigned long flags;
u32 idx;
if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
return -EINVAL;
}
local_irq_save(flags);
idx = ep->bEndpointAddress & 0x7F;
if (idx == 0) {
s3c2410_udc_set_ep0_ss(base_addr);
s3c2410_udc_set_ep0_de_out(base_addr);
} else {
udc_write(idx, S3C2410_UDC_INDEX_REG);
ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
? S3C2410_UDC_IN_CSR1_REG
: S3C2410_UDC_OUT_CSR1_REG);
if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
if (value)
udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
S3C2410_UDC_IN_CSR1_REG);
else {
ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
}
} else {
if (value)
udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
S3C2410_UDC_OUT_CSR1_REG);
else {
ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
}
}
}
ep->halted = value ? 1 : 0;
local_irq_restore(flags);
return 0;
}
static const struct usb_ep_ops s3c2410_ep_ops = {
.enable = s3c2410_udc_ep_enable,
.disable = s3c2410_udc_ep_disable,
.alloc_request = s3c2410_udc_alloc_request,
.free_request = s3c2410_udc_free_request,
.queue = s3c2410_udc_queue,
.dequeue = s3c2410_udc_dequeue,
.set_halt = s3c2410_udc_set_halt,
};
/*------------------------- usb_gadget_ops ----------------------------------*/
/*
* s3c2410_udc_get_frame
*/
static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
{
int tmp;
dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
return tmp;
}
/*
* s3c2410_udc_wakeup
*/
static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
{
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
return 0;
}
/*
* s3c2410_udc_set_selfpowered
*/
static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
{
struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
gadget->is_selfpowered = (value != 0);
if (value)
udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
else
udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
return 0;
}
static void s3c2410_udc_disable(struct s3c2410_udc *dev);
static void s3c2410_udc_enable(struct s3c2410_udc *dev);
static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
{
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
if (udc_info && (udc_info->udc_command || udc->pullup_gpiod)) {
if (is_on)
s3c2410_udc_enable(udc);
else {
if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
if (udc->driver && udc->driver->disconnect)
udc->driver->disconnect(&udc->gadget);
}
s3c2410_udc_disable(udc);
}
} else {
return -EOPNOTSUPP;
}
return 0;
}
static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
{
struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
udc->vbus = (is_active != 0);
s3c2410_udc_set_pullup(udc, is_active);
return 0;
}
static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
{
struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
s3c2410_udc_set_pullup(udc, is_on);
return 0;
}
static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
{
struct s3c2410_udc *dev = _dev;
unsigned int value;
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
value = gpiod_get_value(dev->vbus_gpiod);
if (value != dev->vbus)
s3c2410_udc_vbus_session(&dev->gadget, value);
return IRQ_HANDLED;
}
static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
{
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
if (udc_info && udc_info->vbus_draw) {
udc_info->vbus_draw(ma);
return 0;
}
return -ENOTSUPP;
}
static int s3c2410_udc_start(struct usb_gadget *g,
struct usb_gadget_driver *driver);
static int s3c2410_udc_stop(struct usb_gadget *g);
static const struct usb_gadget_ops s3c2410_ops = {
.get_frame = s3c2410_udc_get_frame,
.wakeup = s3c2410_udc_wakeup,
.set_selfpowered = s3c2410_udc_set_selfpowered,
.pullup = s3c2410_udc_pullup,
.vbus_session = s3c2410_udc_vbus_session,
.vbus_draw = s3c2410_vbus_draw,
.udc_start = s3c2410_udc_start,
.udc_stop = s3c2410_udc_stop,
};
static void s3c2410_udc_command(struct s3c2410_udc *udc,
enum s3c2410_udc_cmd_e cmd)
{
if (!udc_info)
return;
if (udc_info->udc_command) {
udc_info->udc_command(cmd);
} else if (udc->pullup_gpiod) {
int value;
switch (cmd) {
case S3C2410_UDC_P_ENABLE:
value = 1;
break;
case S3C2410_UDC_P_DISABLE:
value = 0;
break;
default:
return;
}
gpiod_set_value(udc->pullup_gpiod, value);
}
}
/*------------------------- gadget driver handling---------------------------*/
/*
* s3c2410_udc_disable
*/
static void s3c2410_udc_disable(struct s3c2410_udc *dev)
{
dprintk(DEBUG_NORMAL, "%s()\n", __func__);
/* Disable all interrupts */
udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
/* Clear the interrupt registers */
udc_write(S3C2410_UDC_USBINT_RESET
| S3C2410_UDC_USBINT_RESUME
| S3C2410_UDC_USBINT_SUSPEND,
S3C2410_UDC_USB_INT_REG);
udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
/* Good bye, cruel world */
s3c2410_udc_command(dev, S3C2410_UDC_P_DISABLE);
/* Set speed to unknown */
dev->gadget.speed = USB_SPEED_UNKNOWN;
}
/*
* s3c2410_udc_reinit
*/
static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
{
u32 i;
/* device/ep0 records init */
INIT_LIST_HEAD(&dev->gadget.ep_list);
INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
dev->ep0state = EP0_IDLE;
for (i = 0; i < S3C2410_ENDPOINTS; i++) {
struct s3c2410_ep *ep = &dev->ep[i];
if (i != 0)
list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
ep->dev = dev;
ep->ep.desc = NULL;
ep->halted = 0;
INIT_LIST_HEAD(&ep->queue);
usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
}
}
/*
* s3c2410_udc_enable
*/
static void s3c2410_udc_enable(struct s3c2410_udc *dev)
{
int i;
dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
/* dev->gadget.speed = USB_SPEED_UNKNOWN; */
dev->gadget.speed = USB_SPEED_FULL;
/* Set MAXP for all endpoints */
for (i = 0; i < S3C2410_ENDPOINTS; i++) {
udc_write(i, S3C2410_UDC_INDEX_REG);
udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
S3C2410_UDC_MAXP_REG);
}
/* Set default power state */
udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
/* Enable reset and suspend interrupt interrupts */
udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
S3C2410_UDC_USB_INT_EN_REG);
/* Enable ep0 interrupt */
udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
/* time to say "hello, world" */
s3c2410_udc_command(dev, S3C2410_UDC_P_ENABLE);
}
static int s3c2410_udc_start(struct usb_gadget *g,
struct usb_gadget_driver *driver)
{
struct s3c2410_udc *udc = to_s3c2410(g);
dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
/* Hook the driver */
udc->driver = driver;
/* Enable udc */
s3c2410_udc_enable(udc);
return 0;
}
static int s3c2410_udc_stop(struct usb_gadget *g)
{
struct s3c2410_udc *udc = to_s3c2410(g);
udc->driver = NULL;
/* Disable udc */
s3c2410_udc_disable(udc);
return 0;
}
/*---------------------------------------------------------------------------*/
static struct s3c2410_udc memory = {
.gadget = {
.ops = &s3c2410_ops,
.ep0 = &memory.ep[0].ep,
.name = gadget_name,
.dev = {
.init_name = "gadget",
},
},
/* control endpoint */
.ep[0] = {
.num = 0,
.ep = {
.name = ep0name,
.ops = &s3c2410_ep_ops,
.maxpacket = EP0_FIFO_SIZE,
.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
USB_EP_CAPS_DIR_ALL),
},
.dev = &memory,
},
/* first group of endpoints */
.ep[1] = {
.num = 1,
.ep = {
.name = "ep1-bulk",
.ops = &s3c2410_ep_ops,
.maxpacket = EP_FIFO_SIZE,
.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
USB_EP_CAPS_DIR_ALL),
},
.dev = &memory,
.fifo_size = EP_FIFO_SIZE,
.bEndpointAddress = 1,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
},
.ep[2] = {
.num = 2,
.ep = {
.name = "ep2-bulk",
.ops = &s3c2410_ep_ops,
.maxpacket = EP_FIFO_SIZE,
.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
USB_EP_CAPS_DIR_ALL),
},
.dev = &memory,
.fifo_size = EP_FIFO_SIZE,
.bEndpointAddress = 2,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
},
.ep[3] = {
.num = 3,
.ep = {
.name = "ep3-bulk",
.ops = &s3c2410_ep_ops,
.maxpacket = EP_FIFO_SIZE,
.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
USB_EP_CAPS_DIR_ALL),
},
.dev = &memory,
.fifo_size = EP_FIFO_SIZE,
.bEndpointAddress = 3,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
},
.ep[4] = {
.num = 4,
.ep = {
.name = "ep4-bulk",
.ops = &s3c2410_ep_ops,
.maxpacket = EP_FIFO_SIZE,
.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
USB_EP_CAPS_DIR_ALL),
},
.dev = &memory,
.fifo_size = EP_FIFO_SIZE,
.bEndpointAddress = 4,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
}
};
/*
* probe - binds to the platform device
*/
static int s3c2410_udc_probe(struct platform_device *pdev)
{
struct s3c2410_udc *udc = &memory;
struct device *dev = &pdev->dev;
int retval;
int irq;
dev_dbg(dev, "%s()\n", __func__);
usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
if (IS_ERR(usb_bus_clock)) {
dev_err(dev, "failed to get usb bus clock source\n");
return PTR_ERR(usb_bus_clock);
}
clk_prepare_enable(usb_bus_clock);
udc_clock = clk_get(NULL, "usb-device");
if (IS_ERR(udc_clock)) {
dev_err(dev, "failed to get udc clock source\n");
retval = PTR_ERR(udc_clock);
goto err_usb_bus_clk;
}
clk_prepare_enable(udc_clock);
mdelay(10);
dev_dbg(dev, "got and enabled clocks\n");
if (strncmp(pdev->name, "s3c2440", 7) == 0) {
dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
}
spin_lock_init(&udc->lock);
udc_info = dev_get_platdata(&pdev->dev);
base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base_addr)) {
retval = PTR_ERR(base_addr);
goto err_udc_clk;
}
the_controller = udc;
platform_set_drvdata(pdev, udc);
s3c2410_udc_disable(udc);
s3c2410_udc_reinit(udc);
irq_usbd = platform_get_irq(pdev, 0);
if (irq_usbd < 0) {
retval = irq_usbd;
goto err_udc_clk;
}
/* irq setup after old hardware state is cleaned up */
retval = request_irq(irq_usbd, s3c2410_udc_irq,
0, gadget_name, udc);
if (retval != 0) {
dev_err(dev, "cannot get irq %i, err %d\n", irq_usbd, retval);
retval = -EBUSY;
goto err_udc_clk;
}
dev_dbg(dev, "got irq %i\n", irq_usbd);
udc->vbus_gpiod = gpiod_get_optional(dev, "vbus", GPIOD_IN);
if (IS_ERR(udc->vbus_gpiod)) {
retval = PTR_ERR(udc->vbus_gpiod);
goto err_int;
}
if (udc->vbus_gpiod) {
gpiod_set_consumer_name(udc->vbus_gpiod, "udc vbus");
irq = gpiod_to_irq(udc->vbus_gpiod);
if (irq < 0) {
dev_err(dev, "no irq for gpio vbus pin\n");
retval = irq;
goto err_gpio_claim;
}
retval = request_irq(irq, s3c2410_udc_vbus_irq,
IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING | IRQF_SHARED,
gadget_name, udc);
if (retval != 0) {
dev_err(dev, "can't get vbus irq %d, err %d\n",
irq, retval);
retval = -EBUSY;
goto err_gpio_claim;
}
dev_dbg(dev, "got irq %i\n", irq);
} else {
udc->vbus = 1;
}
udc->pullup_gpiod = gpiod_get_optional(dev, "pullup", GPIOD_OUT_LOW);
if (IS_ERR(udc->pullup_gpiod)) {
retval = PTR_ERR(udc->pullup_gpiod);
goto err_vbus_irq;
}
gpiod_set_consumer_name(udc->pullup_gpiod, "udc pullup");
retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
if (retval)
goto err_add_udc;
debugfs_create_file("registers", S_IRUGO, s3c2410_udc_debugfs_root, udc,
&s3c2410_udc_debugfs_fops);
dev_dbg(dev, "probe ok\n");
return 0;
err_add_udc:
err_vbus_irq:
if (udc->vbus_gpiod)
free_irq(gpiod_to_irq(udc->vbus_gpiod), udc);
err_gpio_claim:
err_int:
free_irq(irq_usbd, udc);
err_udc_clk:
clk_disable_unprepare(udc_clock);
clk_put(udc_clock);
udc_clock = NULL;
err_usb_bus_clk:
clk_disable_unprepare(usb_bus_clock);
clk_put(usb_bus_clock);
usb_bus_clock = NULL;
return retval;
}
/*
* s3c2410_udc_remove
*/
static int s3c2410_udc_remove(struct platform_device *pdev)
{
struct s3c2410_udc *udc = platform_get_drvdata(pdev);
dev_dbg(&pdev->dev, "%s()\n", __func__);
if (udc->driver)
return -EBUSY;
usb_del_gadget_udc(&udc->gadget);
debugfs_remove(debugfs_lookup("registers", s3c2410_udc_debugfs_root));
if (udc->vbus_gpiod)
free_irq(gpiod_to_irq(udc->vbus_gpiod), udc);
free_irq(irq_usbd, udc);
if (!IS_ERR(udc_clock) && udc_clock != NULL) {
clk_disable_unprepare(udc_clock);
clk_put(udc_clock);
udc_clock = NULL;
}
if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
clk_disable_unprepare(usb_bus_clock);
clk_put(usb_bus_clock);
usb_bus_clock = NULL;
}
dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
return 0;
}
#ifdef CONFIG_PM
static int
s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
{
struct s3c2410_udc *udc = platform_get_drvdata(pdev);
s3c2410_udc_command(udc, S3C2410_UDC_P_DISABLE);
return 0;
}
static int s3c2410_udc_resume(struct platform_device *pdev)
{
struct s3c2410_udc *udc = platform_get_drvdata(pdev);
s3c2410_udc_command(udc, S3C2410_UDC_P_ENABLE);
return 0;
}
#else
#define s3c2410_udc_suspend NULL
#define s3c2410_udc_resume NULL
#endif
static const struct platform_device_id s3c_udc_ids[] = {
{ "s3c2410-usbgadget", },
{ "s3c2440-usbgadget", },
{ }
};
MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
static struct platform_driver udc_driver_24x0 = {
.driver = {
.name = "s3c24x0-usbgadget",
},
.probe = s3c2410_udc_probe,
.remove = s3c2410_udc_remove,
.suspend = s3c2410_udc_suspend,
.resume = s3c2410_udc_resume,
.id_table = s3c_udc_ids,
};
static int __init udc_init(void)
{
int retval;
dprintk(DEBUG_NORMAL, "%s\n", gadget_name);
s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name,
usb_debug_root);
retval = platform_driver_register(&udc_driver_24x0);
if (retval)
goto err;
return 0;
err:
debugfs_remove(s3c2410_udc_debugfs_root);
return retval;
}
static void __exit udc_exit(void)
{
platform_driver_unregister(&udc_driver_24x0);
debugfs_remove_recursive(s3c2410_udc_debugfs_root);
}
module_init(udc_init);
module_exit(udc_exit);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
drivers/usb/gadget/udc/s3c2410_udc.h deleted 100644 → 0
View file @ 7d1ec119
// SPDX-License-Identifier: GPL-2.0+
/*
* linux/drivers/usb/gadget/s3c2410_udc.h
* Samsung on-chip full speed USB device controllers
*
* Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
* Additional cleanups by Ben Dooks <ben-linux@fluff.org>
*/
#ifndef _S3C2410_UDC_H
#define _S3C2410_UDC_H
struct s3c2410_ep {
struct list_head queue;
unsigned long last_io; /* jiffies timestamp */
struct usb_gadget *gadget;
struct s3c2410_udc *dev;
struct usb_ep ep;
u8 num;
unsigned short fifo_size;
u8 bEndpointAddress;
u8 bmAttributes;
unsigned halted : 1;
unsigned already_seen : 1;
unsigned setup_stage : 1;
};
/* Warning : ep0 has a fifo of 16 bytes */
/* Don't try to set 32 or 64 */
/* also testusb 14 fails wit 16 but is */
/* fine with 8 */
#define EP0_FIFO_SIZE 8
#define EP_FIFO_SIZE 64
#define DEFAULT_POWER_STATE 0x00
#define S3C2440_EP_FIFO_SIZE 128
static const char ep0name [] = "ep0";
static const char *const ep_name[] = {
ep0name, /* everyone has ep0 */
/* s3c2410 four bidirectional bulk endpoints */
"ep1-bulk", "ep2-bulk", "ep3-bulk", "ep4-bulk",
};
#define S3C2410_ENDPOINTS ARRAY_SIZE(ep_name)
struct s3c2410_request {
struct list_head queue; /* ep's requests */
struct usb_request req;
};
enum ep0_state {
EP0_IDLE,
EP0_IN_DATA_PHASE,
EP0_OUT_DATA_PHASE,
EP0_END_XFER,
EP0_STALL,
};
static const char *ep0states[]= {
"EP0_IDLE",
"EP0_IN_DATA_PHASE",
"EP0_OUT_DATA_PHASE",
"EP0_END_XFER",
"EP0_STALL",
};
struct s3c2410_udc {
spinlock_t lock;
struct s3c2410_ep ep[S3C2410_ENDPOINTS];
int address;
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct s3c2410_request fifo_req;
u8 fifo_buf[EP_FIFO_SIZE];
u16 devstatus;
u32 port_status;
int ep0state;
struct gpio_desc *vbus_gpiod;
struct gpio_desc *pullup_gpiod;
unsigned got_irq : 1;
unsigned req_std : 1;
unsigned req_config : 1;
unsigned req_pending : 1;
u8 vbus;
int irq;
};
#define to_s3c2410(g) (container_of((g), struct s3c2410_udc, gadget))
#endif
drivers/usb/gadget/udc/s3c2410_udc_regs.h deleted 100644 → 0
View file @ 7d1ec119
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
*/
#ifndef __ASM_ARCH_REGS_UDC_H
#define __ASM_ARCH_REGS_UDC_H
#define S3C2410_USBDREG(x) (x)
#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
/* indexed registers */
#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)
#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */
#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */
#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */
#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */
#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */
#define S3C2410_UDC_PWR_DEFAULT (0x00)
#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */
#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */
#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */
#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */
#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */
#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */
#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */
#define S3C2410_UDC_INDEX_EP0 (0x00)
#define S3C2410_UDC_INDEX_EP1 (0x01)
#define S3C2410_UDC_INDEX_EP2 (0x02)
#define S3C2410_UDC_INDEX_EP3 (0x03)
#define S3C2410_UDC_INDEX_EP4 (0x04)
#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */
#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */
#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */
#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */
#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */
#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */
#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */
#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */
#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */
#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */
#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */
#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */
#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */
#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */
#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)
#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)
#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)
#define S3C2410_UDC_EP0_CSR_DE (1 << 3)
#define S3C2410_UDC_EP0_CSR_SE (1 << 4)
#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)
#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)
#define S3C2410_UDC_EP0_CSR_SSE (1 << 7)
#define S3C2410_UDC_MAXP_8 (1 << 0)
#define S3C2410_UDC_MAXP_16 (1 << 1)
#define S3C2410_UDC_MAXP_32 (1 << 2)
#define S3C2410_UDC_MAXP_64 (1 << 3)
#endif
include/linux/platform_data/s3c-hsudc.h deleted 100644 → 0
View file @ 7d1ec119
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* S3C24XX USB 2.0 High-speed USB controller gadget driver
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
* Each endpoint can be configured as either in or out endpoint. Endpoints
* can be configured for Bulk or Interrupt transfer mode.
*/
#ifndef __LINUX_USB_S3C_HSUDC_H
#define __LINUX_USB_S3C_HSUDC_H
/**
* s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller.
* @epnum: Number of endpoints to be instantiated by the controller driver.
* @gpio_init: Platform specific USB related GPIO initialization.
* @gpio_uninit: Platform specific USB releted GPIO uninitialzation.
*
* Representation of platform data for the S3C24XX USB 2.0 High Speed gadget
* controllers.
*/
struct s3c24xx_hsudc_platdata {
unsigned int epnum;
void (*gpio_init)(void);
void (*gpio_uninit)(void);
void (*phy_init)(void);
void (*phy_uninit)(void);
};
#endif /* __LINUX_USB_S3C_HSUDC_H */
include/linux/platform_data/usb-s3c2410_udc.h deleted 100644 → 0
View file @ 7d1ec119
/* SPDX-License-Identifier: GPL-2.0-only */
/* arch/arm/plat-samsung/include/plat/udc.h
*
* Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
*
* Changelog:
* 14-Mar-2005 RTP Created file
* 02-Aug-2005 RTP File rename
* 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
* 18-Jan-2007 HMW Add per-platform vbus_draw function
*/
#ifndef __ASM_ARM_ARCH_UDC_H
#define __ASM_ARM_ARCH_UDC_H
enum s3c2410_udc_cmd_e {
S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
};
struct s3c2410_udc_mach_info {
void (*udc_command)(enum s3c2410_udc_cmd_e);
void (*vbus_draw)(unsigned int ma);
};
extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
struct s3c24xx_hsudc_platdata;
extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
#endif /* __ASM_ARM_ARCH_UDC_H */
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