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Commit 217eab8a authored by Deepak Saxena's avatar Deepak Saxena
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[ARM] Add IXP2000 header files (include/asm-arm/arch-ixp2000) 

Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
parent a03327a4
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include/asm-arm/arch-ixp2000/dma.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixdp2400/dma.h
*
* Copyright (C) 2002 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS 0xffffffff
/* No DMA */
#define MAX_DMA_CHANNELS 0
#endif /* _ASM_ARCH_DMA_H */
include/asm-arm/arch-ixp2000/gpio.h 0 → 100644
View file @ 217eab8a
/*
* include/asm-arm/arch-ixp2000/ixp2000-gpio.h
*
* Copyright (C) 2002 Intel Corporation.
*
* This program is free software, you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* IXP2000 GPIO in/out, edge/level detection for IRQs:
* IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
* or both Falling-edge and Rising-edge.
* This must be called *before* the corresponding IRQ is registerd.
* Use this instead of directly setting the GPIO registers.
* GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
*/
#ifndef _ASM_ARCH_IXP2000_GPIO_H_
#define _ASM_ARCH_IXP2000_GPIO_H_
#ifndef __ASSEMBLY__
#define GPIO_OUT 0x0
#define GPIO_IN 0x80
#define IXP2000_GPIO_LOW 0
#define IXP2000_GPIO_HIGH 1
#define GPIO_NO_EDGES 0
#define GPIO_FALLING_EDGE 1
#define GPIO_RISING_EDGE 2
#define GPIO_BOTH_EDGES 3
#define GPIO_LEVEL_LOW 4
#define GPIO_LEVEL_HIGH 8
extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
extern void set_GPIO_IRQ_level(int gpio_nr, int level);
extern void gpio_line_config(int line, int style);
static inline int gpio_line_get(int line)
{
return (((*IXP2000_GPIO_PLR) >> line) & 1);
}
static inline void gpio_line_set(int line, int value)
{
if (value == IXP2000_GPIO_HIGH) {
ixp_reg_write(IXP2000_GPIO_POSR, BIT(line));
} else if (value == IXP2000_GPIO_LOW)
ixp_reg_write(IXP2000_GPIO_POCR, BIT(line));
}
#endif /* !__ASSEMBLY__ */
#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
include/asm-arm/arch-ixp2000/hardware.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2000/hardware.h
*
* Hardware definitions for IXP2400/2800 based systems
*
* Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
*
* Maintainer: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright (C) 2001-2002 Intel Corp.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
/*
* This needs to be platform-specific?
*/
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#include "ixp2000-regs.h" /* Chipset Registers */
#define pcibios_assign_all_busses() 0
/*
* Platform helper functions
*/
#include "platform.h"
/*
* Platform-specific bits
*/
#include "ixdp2x00.h" /* IXDP2400/2800 */
#include "ixdp2x01.h" /* IXDP2401/2801 */
#endif /* _ASM_ARCH_HARDWARE_H__ */
include/asm-arm/arch-ixp2000/io.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixdp2000/io.h
*
* Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002 Intel Corp.
* Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __mem_pci(a) ((unsigned long)(a))
/*
* Pick up VMALLOC_END
*/
#define ___io(p) ((unsigned long)((p)+IXP2000_PCI_IO_VIRT_BASE))
/*
* IXP200 does not do proper byte-lane conversion for PCI addresses,
* so we need to override standard functions.
*/
#define alignb(addr) ((addr & ~3) + (3 - (addr & 3)))
#define alignw(addr) ((addr & ~2) + (2 - (addr & 2)))
#define outb(v,p) __raw_writeb(v,alignb(___io(p)))
#define outw(v,p) __raw_writew((v),alignw(___io(p)))
#define outl(v,p) __raw_writel((v),___io(p))
#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
#define inw(p) \
({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
#define inl(p) \
({ unsigned int __v = (__raw_readl(___io(p))); __v; })
#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
#define insl(p,d,l) __raw_readsl(___io(p),d,l)
#ifdef CONFIG_ARCH_IXDP2X01
/*
* This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort
* of "I/O space" and is just direct mapped into a 32-bit-only addressable
* bus. The address space for this bus is such that we can't really easilly
* make it contigous to the PCI I/O address range, and it also does not
* need swapping like PCI addresses do (IXDP2x01 is a BE platform).
* B/C of this we can't use the standard in/out functions and need to
* runtime check if the incoming address is a PCI address or for
* the CS89x0.
*/
#undef inw
#undef outw
#undef insw
#undef outsw
static inline void insw(u32 ptr, void *buf, int length)
{
register volatile u32 *port = (volatile u32 *)ptr;
/*
* Is this cycle meant for the CS8900?
*/
if (machine_is_ixdp2x01() &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
u8 *buf8 = (u8*)buf;
register u32 tmp32;
do {
tmp32 = *port;
*buf8++ = (u8)tmp32;
*buf8++ = (u8)(tmp32 >> 8);
} while(--length);
return;
}
__raw_readsw(alignw(___io(ptr)),buf,length);
}
static inline void outsw(u32 ptr, void *buf, int length)
{
register volatile u32 *port = (volatile u32 *)ptr;
/*
* Is this cycle meant for the CS8900?
*/
if (machine_is_ixdp2x01() &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
register u32 tmp32;
u8 *buf8 = (u8*)buf;
do {
tmp32 = *buf8++;
tmp32 |= (*buf8++) << 8;
*port = tmp32;
} while(--length);
return;
}
__raw_writesw(alignw(___io(ptr)),buf,length);
}
static inline u16 inw(u32 ptr)
{
register volatile u32 *port = (volatile u32 *)ptr;
/*
* Is this cycle meant for the CS8900?
*/
if (machine_is_ixdp2x01() &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
return (u16)(*port);
}
return __raw_readw(alignw(___io(ptr)));
}
static inline void outw(u16 value, u32 ptr)
{
register volatile u32 *port = (volatile u32 *)ptr;
if (machine_is_ixdp2x01() &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
*port = value;
return;
}
__raw_writew((value),alignw(___io(ptr)));
}
#endif /* IXDP2x01 */
#endif
include/asm-arm/arch-ixp2000/irq.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2000/irq.h
*
* Copyright (C) 2002 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define fixup_irq(irq) (irq)
include/asm-arm/arch-ixp2000/irqs.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2000/irqs.h
*
* Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002 Intel Corp.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _IRQS_H
#define _IRQS_H
/*
* Do NOT add #ifdef MACHINE_FOO in here.
* Simpy add your machine IRQs here and increase NR_IRQS if needed to
* hold your machine's IRQ table.
*/
/*
* Some interrupt numbers go unused b/c the IRQ mask/ummask/status
* register has those bit reserved. We just mark those interrupts
* as invalid and this allows us to do mask/unmask with a single
* shift operation instead of having to map the IRQ number to
* a HW IRQ number.
*/
#define IRQ_IXP2000_SWI 0 /* soft interrupt */
#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/
#define IRQ_IXP2000_UART 2
#define IRQ_IXP2000_GPIO 3
#define IRQ_IXP2000_TIMER1 4
#define IRQ_IXP2000_TIMER2 5
#define IRQ_IXP2000_TIMER3 6
#define IRQ_IXP2000_TIMER4 7
#define IRQ_IXP2000_PMU 8
#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */
#define IRQ_IXP2000_DMA1 10
#define IRQ_IXP2000_DMA2 11
#define IRQ_IXP2000_DMA3 12
#define IRQ_IXP2000_PCI_DOORBELL 13
#define IRQ_IXP2000_ME_ATTN 14
#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */
#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */
#define IRQ_IXP2000_THDA1 17 /* thread 32-63A */
#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */
#define IRQ_IXP2000_THDA3 19 /* thread 96-127A */
#define IRQ_IXP2000_THDB0 24 /* thread 0-31 B */
#define IRQ_IXP2000_THDB1 25 /* thread 32-63B */
/* only 64 threads supported for IXP2400, rest or for IXP2800*/
#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */
#define IRQ_IXP2000_THDB3 27 /* thread 96-127B */
/* define generic GPIOs */
#define IRQ_IXP2000_GPIO0 32
#define IRQ_IXP2000_GPIO1 33
#define IRQ_IXP2000_GPIO2 34
#define IRQ_IXP2000_GPIO3 35
#define IRQ_IXP2000_GPIO4 36
#define IRQ_IXP2000_GPIO5 37
#define IRQ_IXP2000_GPIO6 38
#define IRQ_IXP2000_GPIO7 39
/* split off the 2 PCI sources */
#define IRQ_IXP2000_PCIA 40
#define IRQ_IXP2000_PCIB 41
/* Int sources from IRQ_ERROR_STATUS */
#define IRQ_IXP2000_DRAM0_MIN_ERR 42
#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
#define IRQ_IXP2000_DRAM1_MIN_ERR 44
#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
#define IRQ_IXP2000_DRAM2_MIN_ERR 46
#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
#define IRQ_IXP2000_SRAM0_ERR 48
#define IRQ_IXP2000_SRAM1_ERR 49
#define IRQ_IXP2000_SRAM2_ERR 50
#define IRQ_IXP2000_SRAM3_ERR 51
#define IRQ_IXP2000_MEDIA_ERR 52
#define IRQ_IXP2000_PCI_ERR 53
#define IRQ_IXP2000_SP_INT 54
#define NR_IXP2000_IRQS 55
#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
/*
* This allows for all the on-chip sources plus up to 32 CPLD based
* IRQs. Should be more then enough.
*/
#define IXP2000_BOARD_IRQS 32
#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
/*
* IXDP2400 specific IRQs
*/
#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0)
#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1)
#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2)
#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3)
#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4)
#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5)
#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6)
#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7)
#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1)
#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS
/* IXDP2800 specific IRQs */
#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0)
#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1)
#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2)
#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3)
#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4)
#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5)
#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1)
#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS
/*
* IRQs on both IXDP2x01 boards
*/
#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2)
#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3)
#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4)
#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5)
#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6)
#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7)
#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8)
#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16)
#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17)
#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18)
#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19)
#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21)
#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22)
#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24)
#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25)
#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26)
#define IXDP2X01_VALID_IRQ_MASK ( \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
/*
* IXDP2401 specific IRQs
*/
#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0)
#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1)
#define IXDP2401_VALID_IRQ_MASK ( \
IXDP2X01_VALID_IRQ_MASK | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
/*
* IXDP2801-specific IRQs
*/
#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0)
#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27)
#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28)
#define IXDP2801_VALID_IRQ_MASK ( \
IXDP2X01_VALID_IRQ_MASK | \
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1)
#endif /*_IRQS_H*/
include/asm-arm/arch-ixp2000/ixdp2x00.h 0 → 100644
View file @ 217eab8a
/*
* inclue/asm-arm/arch-ixp2000/ixmb2x00.h
*
* Register and other defines for IXDP2[48]00 platforms
*
* Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002 Intel Corp.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _IXDP2X00_H_
#define _IXDP2X00_H_
/*
* On board CPLD memory map
*/
#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
#define IXDP2X00_VIRT_CPLD_BASE 0xfefdd000
#define IXDP2X00_CPLD_SIZE 0x00001000
#define IXDP2X00_CPLD_REG(x) \
(volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
/*
* IXDP2400 CPLD registers
*/
#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0)
#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4)
#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8)
#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc)
#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10)
#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14)
#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18)
#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48)
/*
* IXDP2800 CPLD registers
*/
#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0)
#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140)
#define IXDP2X00_GPIO_I2C_ENABLE 0x02
#define IXDP2X00_GPIO_SCL 0x07
#define IXDP2X00_GPIO_SDA 0x06
/*
* PCI devfns for on-board devices. We need these to be able to
* properly translte IRQs and for device removal.
*/
#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */
#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */
#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */
#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */
#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */
#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */
#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */
#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */
#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */
#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */
#ifndef __ASSEMBLY__
/*
* Master NPU will always have flash and be PCI master.
* Slave NPU may or may not have flash but will never be PCI master.
*/
static inline unsigned int ixdp2x00_master_npu(void)
{
return ((ixp2000_has_flash()) && (ixp2000_is_pcimaster()));
}
/*
* Helper functions used by ixdp2400 and ixdp2800 specific code
*/
void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
void ixdp2x00_slave_pci_postinit(void);
void ixdp2x00_init_machine(void);
void ixdp2x00_map_io(void);
#endif
#endif /*_IXDP2X00_H_ */
include/asm-arm/arch-ixp2000/ixdp2x01.h 0 → 100644
View file @ 217eab8a
/*
* include/asm/arch/ixdp2x01.h
*
* Platform definitions for IXDP2X01 && IXDP2801 systems
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista Software, Inc.
*
* Based on original code Copyright (c) 2002-2003 Intel Corporation
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __IXDP2X01_H__
#define __IXDP2X01_H__
#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
#define IXDP2X01_VIRT_CPLD_BASE 0xfefdd000
#define IXDP2X01_CPLD_REGION_SIZE 0x1000
#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile u32*)(IXDP2X01_VIRT_CPLD_BASE | reg)
#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60)
#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60)
#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80)
#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16)
#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00)
#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08)
#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C)
#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10)
#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG
#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14)
#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20)
#define IXDP2X01_CPLD_FLASH_INTERN 0x8000
#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF
#define IXDP2X01_FLASH_WINDOW_BITS 25
#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS)
#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1)
#define IXDP2X01_UART_CLK 1843200
#ifndef __ASSEMBLY__
#include <asm/mach-types.h>
#define machine_is_ixdp2x01() (machine_is_ixdp2401() || \
machine_is_ixdp2801())
#endif
#endif /* __IXDP2x01_H__ */
include/asm-arm/arch-ixp2000/ixp2000-regs.h 0 → 100644
View file @ 217eab8a
/*
* include/asm-arm/arch-ixp2000/ixp2000-regs.h
*
* Chipset register definitions for IXP2400/2800 based systems.
*
* Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002 Intel Corp.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _IXP2000_REGS_H_
#define _IXP2000_REGS_H_
/*
* Static I/O regions. The manual defines each region as being several
* MB in size, but all the registers are within the first 4K, so there's
* no purpose in mapping the whole region in.
*/
#define IXP2000_SLOWPORT_CSR_PHYS_BASE 0xc0080000
#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfefff000
#define IXP2000_SLOWPORT_CSR_SIZE 0x1000
#define IXP2000_GLOBAL_REG_PHYS_BASE 0xc0004000
#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfeffe000
#define IXP2000_GLOBAL_REG_SIZE 0x1000
#define IXP2000_UART_PHYS_BASE 0xc0030000
#define IXP2000_UART_VIRT_BASE 0xfef30000
#define IXP2000_UART_SIZE 0x1000
#define IXP2000_TIMER_PHYS_BASE 0xc0020000
#define IXP2000_TIMER_VIRT_BASE 0xfeffc000
#define IXP2000_TIMER_SIZE 0x1000
#define IXP2000_GPIO_PHYS_BASE 0xc0010000
#define IXP2000_GPIO_VIRT_BASE 0xfeffb000
#define IXP2000_GPIO_SIZE 0x1000
#define IXP2000_INTCTL_PHYS_BASE 0xd6000000
#define IXP2000_INTCTL_VIRT_BASE 0xfeffa000
#define IXP2000_INTCTL_SIZE 0x01000
#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000
#define IXP2000_PCI_CREG_VIRT_BASE 0xfeff0000
#define IXP2000_PCI_CREG_SIZE 0x1000
#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000
#define IXP2000_PCI_CSR_VIRT_BASE 0xfefde000
#define IXP2000_PCI_CSR_SIZE 0x1000
#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
#define IXP2000_PCI_IO_SIZE 0x01000000
#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000
#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000
#define IXP2000_PCI_CFG0_SIZE 0x01000000
#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000
#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000
#define IXP2000_PCI_CFG1_SIZE 0x01000000
/*
* Timers
*/
#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
/* Timer control */
#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00)
#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04)
#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08)
#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c)
/* Store initial value */
#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10)
#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14)
#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18)
#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c)
/* Read current value */
#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20)
#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24)
#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28)
#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c)
/* Clear associated timer interrupt */
#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30)
#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34)
#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38)
#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c)
/* Timer watchdog enable for T4 */
#define IXP2000_TWDE IXP2000_TIMER_REG(0x40)
#define WDT_ENABLE 0x00000001
#define TIMER_DIVIDER_256 0x00000008
#define TIMER_ENABLE 0x00000080
/*
* Interrupt controller registers
*/
#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08)
#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10)
#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10)
#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18)
#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14)
#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24)
#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c)
#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30)
#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34)
/*
* Mask of valid IRQs in the 32-bit IRQ register. We use
* this to mark certain IRQs as being in-valid.
*/
#define IXP2000_VALID_IRQ_MASK 0x0f0fffff
/*
* PCI config register access from core
*/
#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04)
#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10)
#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14)
#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18)
/*
* PCI CSRs
*/
#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
/*
* PCI outbound interrupts
*/
#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30)
#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34)
/*
* PCI communications
*/
#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50)
#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54)
#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58)
#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C)
#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60)
#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64)
#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70)
#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74)
/*
* DMA engines
*/
#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80)
#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84)
#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88)
#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C)
#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90)
#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94)
#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0)
#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4)
#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8)
#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC)
#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0)
#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4)
#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0)
#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4)
#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8)
#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC)
#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0)
#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4)
#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0)
/*
* Size masks for BARs
*/
#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
/*
* Control and uEngine related
*/
#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C)
#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140)
#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148)
#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C)
#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150)
#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154)
/*
* Inbound PCI interrupt control
*/
#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158)
#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */
#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
/* These are from the IRQ register in the PCI ISR register */
#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */
#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
#define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */
#define IXP2000_PCI_RST_REL (1 << 2)
#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
#define CFG_PCI_BOOT_HOST (1 << 2)
#define CFG_BOOT_PROM (1 << 1)
/*
* SlowPort CSRs
*
* The slowport is used to access things like flash, SONET framer control
* ports, slave microprocessors, CPLDs, and others of chip memory mapped
* peripherals.
*/
#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00)
#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04)
#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08)
#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c)
#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10)
#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14)
#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18)
#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C)
#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20)
#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24)
#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28)
/*
* CCR values.
* The CCR configures the clock division for the slowport interface.
*/
#define SLOWPORT_CCR_DIV_1 0x00
#define SLOWPORT_CCR_DIV_2 0x01
#define SLOWPORT_CCR_DIV_4 0x02
#define SLOWPORT_CCR_DIV_6 0x03
#define SLOWPORT_CCR_DIV_8 0x04
#define SLOWPORT_CCR_DIV_10 0x05
#define SLOWPORT_CCR_DIV_12 0x06
#define SLOWPORT_CCR_DIV_14 0x07
#define SLOWPORT_CCR_DIV_16 0x08
#define SLOWPORT_CCR_DIV_18 0x09
#define SLOWPORT_CCR_DIV_20 0x0a
#define SLOWPORT_CCR_DIV_22 0x0b
#define SLOWPORT_CCR_DIV_24 0x0c
#define SLOWPORT_CCR_DIV_26 0x0d
#define SLOWPORT_CCR_DIV_28 0x0e
#define SLOWPORT_CCR_DIV_30 0x0f
/*
* PCR values. PCR configure the mode of the interfac3
*/
#define SLOWPORT_MODE_FLASH 0x00
#define SLOWPORT_MODE_LUCENT 0x01
#define SLOWPORT_MODE_PMC_SIERRA 0x02
#define SLOWPORT_MODE_INTEL_UP 0x03
#define SLOWPORT_MODE_MOTOROLA_UP 0x04
/*
* ADC values. Defines data and address bus widths
*/
#define SLOWPORT_ADDR_WIDTH_8 0x00
#define SLOWPORT_ADDR_WIDTH_16 0x01
#define SLOWPORT_ADDR_WIDTH_24 0x02
#define SLOWPORT_ADDR_WIDTH_32 0x03
#define SLOWPORT_DATA_WIDTH_8 0x00
#define SLOWPORT_DATA_WIDTH_16 0x10
#define SLOWPORT_DATA_WIDTH_24 0x20
#define SLOWPORT_DATA_WIDTH_32 0x30
/*
* Masks and shifts for various fields in the WTC and RTC registers
*/
#define SLOWPORT_WRTC_MASK_HD 0x0003
#define SLOWPORT_WRTC_MASK_SU 0x003c
#define SLOWPORT_WRTC_MASK_PW 0x03c0
#define SLOWPORT_WRTC_SHIFT_HD 0x00
#define SLOWPORT_WRTC_SHIFT_SU 0x02
#define SLOWPORT_WRTC_SHFIT_PW 0x06
/*
* GPIO registers & GPIO interface
*/
#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00)
#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04)
#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08)
#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c)
#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10)
#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14)
#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18)
#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c)
#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20)
#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24)
#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28)
#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c)
#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30)
#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34)
#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38)
#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c)
#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40)
/*
* "Global" registers...whatever that's supposed to mean.
*/
#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
#define IXP2000_PROD_ID GLOBAL_REG(0x00)
#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000
#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000
#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00
#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200
#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100
#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000
#define IXP2000_MAJ_REV_MASK 0x000000F0
#define IXP2000_MIN_REV_MASK 0x0000000F
#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
#define IXP2000_MSF_ClK_CNTRL GLOBAL_REG(0x08)
#define IXP2000_RESET0 GLOBAL_REG(0x0c)
#define IXP2000_RESET1 GLOBAL_REG(0x10)
#define IXP2000_CCR GLOBAL_REG(0x14)
#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18)
#define RSTALL (1 << 16)
#define WDT_RESET_ENABLE 0x01000000
#endif /* _IXP2000_H_ */
include/asm-arm/arch-ixp2000/memory.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2000/memory.h
*
* Copyright (c) 2002 Intel Corp.
* Copyright (c) 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET (0x00000000UL)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#include <asm/arch/ixp2000-regs.h>
#define __virt_to_bus(v) \
(((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
#define __bus_to_virt(b) \
__phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
#endif
include/asm-arm/arch-ixp2000/platform.h 0 → 100644
View file @ 217eab8a
/*
* include/asm-arh/arch-ixp2000/platform.h
*
* Various bits of code used by platform-level code.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASSEMBLY__
/*
* The IXP2400B0 silicon contains an errata that causes writes to
* on-chip I/O register to not complete fully. What this means is
* that if you have a write to on-chip I/O followed by a back-to-back
* read or write, the first write will happend twice. OR...if it's
* not a back-to-back trasaction, the read or write will generate
* incorrect data.
*
* The official work around for this is to set the on-chip I/O regions
* as XCB=101 and then force a read-back from the register.
*
*/
#if defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
#include <asm/system.h> /* Pickup local_irq_ functions */
static inline void ixp2000_reg_write(volatile unsigned long *reg, unsigned long val)
{
volatile unsigned long dummy;
unsigned long flags;
local_irq_save(flags);
*reg = val;
__asm__ __volatile__("":::"memory");
dummy = *reg;
local_irq_restore(flags);
}
#else
#define ixp2000_reg_write(reg, val) (*reg = val)
#endif /* IXDP2400 || IXDP2401 */
/*
* Boards may multiplex different devices on the 2nd channel of
* the slowport interface that each need different configuration
* settings. For example, the IXDP2400 uses channel 2 on the interface
* to access the CPLD, the switch fabric card, and te media card. Each
* one needs a different mode so drivers must save/restore the mode
* before and after each operation.
*
* acquire_slowport(&your_config);
* ...
* do slowport operations
* ...
* release_slowport();
*
* Note that while you have the slowport, you are holding a spinlock,
* so your code should be written as if you explicitly acquired a lock.
*
* The configuration only affects device 2 on the slowport, so the
* MTD map driver does not acquire/release the slowport.
*/
struct slowport_cfg {
unsigned long CCR; /* Clock divide */
unsigned long WTC; /* Write Timing Control */
unsigned long RTC; /* Read Timing Control */
unsigned long PCR; /* Protocol Control Register */
unsigned long ADC; /* Address/Data Width Control */
};
void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
void ixp2000_release_slowport(struct slowport_cfg *);
/*
* IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires
* tweaking of addresses in the MTD driver.
*/
static inline unsigned ixp2000_has_broken_slowport(void)
{
unsigned long id = *IXP2000_PROD_ID;
unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
IXP2000_MIN_PROD_TYPE_MASK);
return (((id_prod ==
/* fixed in IXP2400-B0 */
(IXP2000_MAJ_PROD_TYPE_IXP2000 |
IXP2000_MIN_PROD_TYPE_IXP2400)) &&
((id & IXP2000_MAJ_REV_MASK) == 0)) ||
((id_prod ==
/* fixed in IXP2800-B0 */
(IXP2000_MAJ_PROD_TYPE_IXP2000 |
IXP2000_MIN_PROD_TYPE_IXP2800)) &&
((id & IXP2000_MAJ_REV_MASK) == 0)) ||
((id_prod ==
/* fixed in IXP2850-B0 */
(IXP2000_MAJ_PROD_TYPE_IXP2000 |
IXP2000_MIN_PROD_TYPE_IXP2850)) &&
((id & IXP2000_MAJ_REV_MASK) == 0)));
}
static inline unsigned int ixp2000_has_flash(void)
{
return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
}
static inline unsigned int ixp2000_is_pcimaster(void)
{
return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
}
void ixp2000_map_io(void);
void ixp2000_init_irq(void);
void ixp2000_init_time(unsigned long);
struct pci_sys_data;
void ixp2000_pci_preinit(void);
int ixp2000_pci_setup(int, struct pci_sys_data*);
struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
/*
* Several of the IXP2000 systems have banked flash so we need to extend the
* flash_platform_data structure with some private pointers
*/
struct ixp2000_flash_data {
struct flash_platform_data *platform_data;
int nr_banks;
unsigned long (*bank_setup)(unsigned long);
};
/*
* GPIO helper functions
*/
#define GPIO_IN 0
#define GPIO_OUT 1
extern void gpio_line_config(int line, int style);
static inline int gpio_line_get(int line)
{
return (((*IXP2000_GPIO_PLR) >> line) & 1);
}
static inline void gpio_line_set(int line, int value)
{
if (value)
ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
else
ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
}
struct ixp2000_i2c_pins {
unsigned long sda_pin;
unsigned long scl_pin;
};
#endif /* !__ASSEMBLY__ */
include/asm-arm/arch-ixp2000/serial.h 0 → 100644
View file @ 217eab8a
/*
* include/asm-arm/arch-ixp2000/serial.h
*
* Serial port defn for ixp2000 based systems.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (c) 2002-2004 MontaVista Software, Inc.
*
* We do not register serial ports staticly b/c there is no easy way
* to autodetect an XScale port. Instead we register them at runtime
* via early_serial_init().
*/
#ifndef _ARCH_SERIAL_H_
#define _ARCH_SERIAL_H_
#define BASE_BAUD (50000000/ 16)
/*
* Currently no IXP2000 systems with > 3 serial ports.
* If you add a system that does, just up this.
*/
#define STD_SERIAL_PORT_DEFNS
#define EXTRA_SERIAL_PORT_DEFNS
#endif // __ARCH_SERIAL_H_
include/asm-arm/arch-ixp2000/system.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2400/system.h
*
* Copyright (C) 2002 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/hardware.h>
#include <asm/mach-types.h>
static inline void arch_idle(void)
{
#if 0
while (!current->need_resched && !hlt_counter) {
cpu_do_idle(IDLE_CLOCK_SLOW);
cpu_do_idle(IDLE_WAIT_FAST);
cpu_do_idle(IDLE_CLOCK_FAST);
}
#endif
}
static inline void arch_reset(char mode)
{
cli();
if (machine_is_ixdp2401() || machine_is_ixdp2801()) {
*IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN);
*IXDP2X01_CPLD_RESET_REG = 0xffffffff;
}
/*
* We do a reset all if we are PCI master. We could be a slave and we
* don't want to do anything funky on the PCI bus.
*/
if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
*(IXP2000_RESET0) |= (RSTALL);
}
}
include/asm-arm/arch-ixp2000/timex.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2000/timex.h
*
* IXP2000 architecture timex specifications
*/
/*
* Default clock is 50MHz APB, but platform code can override this
*/
#define CLOCK_TICK_RATE 50000000
include/asm-arm/arch-ixp2000/uncompress.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2000/uncompress.h
*
*
* Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2002 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/serial_reg.h>
#define UART_BASE 0xc0030000
#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x))
#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */
#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/
#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/
#define UARTIER PHYS(0x04) /* Interrupt enable reg */
#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/
#define UARTLCR PHYS(0x0c) /* Control reg */
#define UARTSR PHYS(0x14) /* Status reg */
static __inline__ void putc(char c)
{
int j = 0x1000;
while (--j && !(*UARTSR & UART_LSR_THRE));
*UARTDR = c;
}
static void puts(const char *s)
{
while (*s)
{
putc(*s);
if (*s == '\n')
putc('\r');
s++;
}
}
#define arch_decomp_setup()
#define arch_decomp_wdog()
include/asm-arm/arch-ixp2000/vmalloc.h 0 → 100644
View file @ 217eab8a
/*
* linux/include/asm-arm/arch-ixp2000/vmalloc.h
*
* Author: Naeem Afzal <naeem.m.afzal@intel.com>
*
* Copyright 2002 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END 0xfb000000
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