Commit 2219b0ce authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC updates from Arnd Bergmann:
 "The SoC updates this time are mainly removing obsolete code from the
  OMAP2 platform, another step in the eternal cleanup of that platform.

  There are two new SoCs getting added: STMicroelectronics stm32mp13 and
  Microchip lan966. Both fit into existing platforms and require minimal
  changes here.

  A couple of MAINTAINER file updates relate to those changes, and
  update some file paths"

* tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (28 commits)
  MAINTAINERS: Update BCM7XXX entry with additional patterns
  MAINTAINERS: add pinctrl-apple-gpio to ARM/APPLE MACHINE
  MAINTAINERS: Add pasemi i2c to ARM/APPLE MACHINE
  ARM: SPEAr: Update MAINTAINERS entries
  ARM: OMAP2+: Drop unused CM defines for am3
  ARM: OMAP2+: Drop unused CM and SCRM defines for omap4
  ARM: OMAP2+: Drop unused CM and SCRM defines for omap5
  ARM: OMAP2+: Drop unused CM defines for dra7
  ARM: OMAP2+: Drop unused PRM defines for am3
  ARM: OMAP2+: Drop unused PRM defines for am4
  ARM: OMAP2+: Drop unused PRM defines for omap4
  ARM: OMAP2+: Drop unused PRM defines for omap5
  ARM: OMAP2+: Drop unused PRM defines for dra7
  ARM: OMAP2+: Fix comment typo
  ARM: OMAP2+: Fix typo in some comments
  ARM: at91: add basic support for new SoC family lan966
  dt-bindings: arm: at91: Document lan966 pcb8291 and pcb8290 boards
  ARM: at91: Documentation: add lan966 family
  ARM: at91: Documentation: add sama7g5 family
  MAINTAINERS: add an entry for NXP S32G boards
  ...
parents 43e1b129 fc3d4aeb
......@@ -55,6 +55,7 @@ SoC-specific documents
stm32/stm32h750-overview
stm32/stm32f769-overview
stm32/stm32f429-overview
stm32/stm32mp13-overview
stm32/stm32mp157-overview
sunxi
......
......@@ -137,6 +137,26 @@ the Microchip website: http://www.microchip.com.
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001476B.pdf
* ARM Cortex-A7 based SoCs
- sama7g5 family
- sama7g51
- sama7g52
- sama7g53
- sama7g54 (device superset)
* Datasheet
Coming soon
- lan966 family
- lan9662
- lan9668
* Datasheet
Coming soon
* ARM Cortex-M7 MCUs
- sams70 family
......
===================
STM32MP13 Overview
===================
Introduction
------------
The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications.
They feature:
- One Cortex-A7 application core
- Standard memories interface support
- Standard connectivity, widely inherited from the STM32 MCU family
- Comprehensive security support
More details:
- Cortex-A7 core running up to @900MHz
- FMC controller to connect SDRAM, NOR and NAND memories
- QSPI
- SD/MMC/SDIO support
- 2*Ethernet controller
- CAN
- ADC/DAC
- USB EHCI/OHCI controllers
- USB OTG
- I2C, SPI, CAN busses support
- Several general purpose timers
- Serial Audio interface
- LCD controller
- DCMIPP
- SPDIFRX
- DFSDM
:Authors:
- Alexandre Torgue <alexandre.torgue@foss.st.com>
......@@ -150,6 +150,18 @@ properties:
- const: microchip,sama7g5
- const: microchip,sama7
- description: Microchip LAN9662 PCB8291 Evaluation Board.
items:
- const: microchip,lan9662-pcb8291
- const: microchip,lan9662
- const: microchip,lan966
- description: Microchip LAN9668 PCB8290 Evaluation Board.
items:
- const: microchip,lan9668-pcb8290
- const: microchip,lan9668
- const: microchip,lan966
- items:
- enum:
- atmel,sams70j19
......
......@@ -1721,13 +1721,17 @@ B: https://github.com/AsahiLinux/linux/issues
C: irc://irc.oftc.net/asahi-dev
T: git https://github.com/AsahiLinux/linux.git
F: Documentation/devicetree/bindings/arm/apple.yaml
F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
F: arch/arm64/boot/dts/apple/
F: drivers/i2c/busses/i2c-pasemi-core.c
F: drivers/i2c/busses/i2c-pasemi-platform.c
F: drivers/irqchip/irq-apple-aic.c
F: drivers/mailbox/apple-mailbox.c
F: drivers/pinctrl/pinctrl-apple-gpio.c
F: include/dt-bindings/interrupt-controller/apple-aic.h
F: include/dt-bindings/pinctrl/apple.h
F: include/linux/apple-mailbox.h
......@@ -2315,6 +2319,14 @@ F: arch/arm/boot/dts/nuvoton-wpcm450*
F: arch/arm/mach-npcm/wpcm450.c
F: drivers/*/*wpcm*
ARM/NXP S32G ARCHITECTURE
M: Chester Lin <clin@suse.com>
R: Andreas Färber <afaerber@suse.de>
R: Matthias Brugger <mbrugger@suse.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/freescale/s32g*.dts*
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
L: openmoko-kernel@lists.openmoko.org (subscribers-only)
S: Orphan
......@@ -3633,6 +3645,8 @@ F: arch/arm/mm/cache-b15-rac.c
F: drivers/bus/brcmstb_gisb.c
F: drivers/pci/controller/pcie-brcmstb.c
N: brcmstb
N: bcm7038
N: bcm7120
BROADCOM BDC DRIVER
M: Al Cooper <alcooperx@gmail.com>
......@@ -14987,13 +15001,6 @@ L: linux-omap@vger.kernel.org
S: Maintained
F: drivers/pinctrl/pinctrl-single.c
PIN CONTROLLER - ST SPEAR
M: Viresh Kumar <vireshk@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://www.st.com/spear
F: drivers/pinctrl/spear/
PKTCDVD DRIVER
M: linux-block@vger.kernel.org
S: Orphan
......@@ -17771,21 +17778,17 @@ W: https://github.com/linux-speakup/speakup
B: https://github.com/linux-speakup/speakup/issues
F: drivers/accessibility/speakup/
SPEAR CLOCK FRAMEWORK SUPPORT
M: Viresh Kumar <vireshk@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://www.st.com/spear
F: drivers/clk/spear/
SPEAR PLATFORM SUPPORT
SPEAR PLATFORM/CLOCK/PINCTRL SUPPORT
M: Viresh Kumar <vireshk@kernel.org>
M: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
M: soc@kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://www.st.com/spear
F: arch/arm/boot/dts/spear*
F: arch/arm/mach-spear/
F: drivers/clk/spear/
F: drivers/pinctrl/spear/
SPI NOR SUBSYSTEM
M: Tudor Ambarus <tudor.ambarus@microchip.com>
......
......@@ -67,6 +67,15 @@ config SOC_SAMA7G5
help
Select this if you are using one of Microchip's SAMA7G5 family SoC.
config SOC_LAN966
bool "ARMv7 based Microchip LAN966 SoC family"
depends on ARCH_MULTI_V7
select DW_APB_TIMER_OF
select ARM_GIC
select MEMORY
help
This enables support for ARMv7 based Microchip LAN966 SoC family.
config SOC_AT91RM9200
bool "AT91RM9200"
depends on ARCH_MULTI_V4T
......
......@@ -20,71 +20,11 @@
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define OMAP4430_ABE_STATDEP_SHIFT 3
#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
#define OMAP4430_CLKSEL_SHIFT 24
#define OMAP4430_CLKSEL_WIDTH 0x1
#define OMAP4430_CLKSEL_MASK (1 << 24)
#define OMAP4430_CLKSEL_0_0_SHIFT 0
#define OMAP4430_CLKSEL_0_0_WIDTH 0x1
#define OMAP4430_CLKSEL_0_1_SHIFT 0
#define OMAP4430_CLKSEL_0_1_WIDTH 0x2
#define OMAP4430_CLKSEL_24_25_SHIFT 24
#define OMAP4430_CLKSEL_24_25_WIDTH 0x2
#define OMAP4430_CLKSEL_60M_SHIFT 24
#define OMAP4430_CLKSEL_60M_WIDTH 0x1
#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1
#define OMAP4430_CLKSEL_CORE_SHIFT 0
#define OMAP4430_CLKSEL_CORE_WIDTH 0x1
#define OMAP4430_CLKSEL_DIV_SHIFT 24
#define OMAP4430_CLKSEL_DIV_WIDTH 0x1
#define OMAP4430_CLKSEL_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1
#define OMAP4430_CLKSEL_L3_SHIFT 4
#define OMAP4430_CLKSEL_L3_WIDTH 0x1
#define OMAP4430_CLKSEL_L4_SHIFT 8
#define OMAP4430_CLKSEL_L4_WIDTH 0x1
#define OMAP4430_CLKSEL_OPP_SHIFT 0
#define OMAP4430_CLKSEL_OPP_WIDTH 0x2
#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1
#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1
#define OMAP4430_CLKTRCTRL_SHIFT 0
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5
#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
#define OMAP4430_DSS_STATDEP_SHIFT 8
#define OMAP4430_DUCATI_STATDEP_SHIFT 0
#define OMAP4430_GFX_STATDEP_SHIFT 10
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
#define OMAP4430_IDLEST_SHIFT 16
#define OMAP4430_IDLEST_MASK (0x3 << 16)
#define OMAP4430_IVAHD_STATDEP_SHIFT 2
......@@ -98,46 +38,5 @@
#define OMAP4430_MEMIF_STATDEP_SHIFT 4
#define OMAP4430_MODULEMODE_SHIFT 0
#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2
#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2
#define OMAP4430_SCALE_FCLK_SHIFT 0
#define OMAP4430_SCALE_FCLK_WIDTH 0x1
#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
#define OMAP4430_SYS_CLKSEL_SHIFT 0
#define OMAP4430_SYS_CLKSEL_WIDTH 0x3
#define OMAP4430_TESLA_STATDEP_SHIFT 1
#endif
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......@@ -812,7 +812,7 @@ static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh)
}
/**
* _init_main_clk - get a struct clk * for the the hwmod's main functional clk
* _init_main_clk - get a struct clk * for the hwmod's main functional clk
* @oh: struct omap_hwmod *
*
* Called from _init_clocks(). Populates the @oh _clk (main
......@@ -862,7 +862,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
}
/**
* _init_interface_clks - get a struct clk * for the the hwmod's interface clks
* _init_interface_clks - get a struct clk * for the hwmod's interface clks
* @oh: struct omap_hwmod *
*
* Called from _init_clocks(). Populates the @oh OCP slave interface
......@@ -901,7 +901,7 @@ static int _init_interface_clks(struct omap_hwmod *oh)
}
/**
* _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
* _init_opt_clk - get a struct clk * for the hwmod's optional clocks
* @oh: struct omap_hwmod *
*
* Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
......
......@@ -274,34 +274,10 @@ static void __init omap3_pandora_legacy_init(void)
}
#endif /* CONFIG_ARCH_OMAP3 */
#ifdef CONFIG_SOC_OMAP5
static void __init omap5_uevm_legacy_init(void)
{
}
#endif
#ifdef CONFIG_SOC_DRA7XX
static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = {
.set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint,
};
static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1;
static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2;
static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3;
static void __init dra7x_evm_mmc_quirk(void)
{
if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) {
dra7_hsmmc_data_mmc1.version = "rev11";
dra7_hsmmc_data_mmc1.max_freq = 96000000;
dra7_hsmmc_data_mmc2.version = "rev11";
dra7_hsmmc_data_mmc2.max_freq = 48000000;
dra7_hsmmc_data_mmc3.version = "rev11";
dra7_hsmmc_data_mmc3.max_freq = 48000000;
}
}
#endif
static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk)
......@@ -508,12 +484,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
"4a0d9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]),
#endif
#ifdef CONFIG_SOC_DRA7XX
OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc",
&dra7_hsmmc_data_mmc1),
OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc",
&dra7_hsmmc_data_mmc2),
OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc",
&dra7_hsmmc_data_mmc3),
OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu",
&dra7_ipu1_dsp_iommu_pdata),
OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu",
......@@ -548,12 +518,6 @@ static struct pdata_init pdata_quirks[] __initdata = {
{ "technexion,omap3-tao3530", omap3_tao3530_legacy_init, },
{ "openpandora,omap3-pandora-600mhz", omap3_pandora_legacy_init, },
{ "openpandora,omap3-pandora-1ghz", omap3_pandora_legacy_init, },
#endif
#ifdef CONFIG_SOC_OMAP5
{ "ti,omap5-uevm", omap5_uevm_legacy_init, },
#endif
#ifdef CONFIG_SOC_DRA7XX
{ "ti,dra7-evm", dra7x_evm_mmc_quirk, },
#endif
{ /* sentinel */ },
};
......
......@@ -626,7 +626,7 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
* powerdomain @pwrdm will enter when the powerdomain enters retention.
* This will be either RETENTION or OFF, if supported. Returns
* -EINVAL if the powerdomain pointer is null or the target power
* state is not not supported, or returns 0 upon success.
* state is not supported, or returns 0 upon success.
*/
int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
{
......@@ -658,7 +658,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
* state. @bank will be a number from 0 to 3, and represents different
* types of memory, depending on the powerdomain. Returns -EINVAL if
* the powerdomain pointer is null or the target power state is not
* not supported for this memory bank, -EEXIST if the target memory
* supported for this memory bank, -EEXIST if the target memory
* bank does not exist or is not controllable, or returns 0 upon
* success.
*/
......@@ -696,7 +696,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
* different types of memory, depending on the powerdomain. @pwrst
* will be either RETENTION or OFF, if supported. Returns -EINVAL if
* the powerdomain pointer is null or the target power state is not
* not supported for this memory bank, -EEXIST if the target memory
* supported for this memory bank, -EEXIST if the target memory
* bank does not exist or is not controllable, or returns 0 upon
* success.
*/
......
......@@ -32,20 +32,8 @@
/* Other PRM offsets */
#define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024
/* RM RSTCTRL offsets */
#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010
#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010
#define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010
/* RM RSTST offsets */
#define AM43XX_RM_GFX_RSTST_OFFSET 0x0014
#define AM43XX_RM_PER_RSTST_OFFSET 0x0014
#define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014
/* CM instances */
#define AM43XX_CM_WKUP_INST 0x2800
#define AM43XX_CM_DEVICE_INST 0x4100
#define AM43XX_CM_DPLL_INST 0x4200
#define AM43XX_CM_MPU_INST 0x8300
#define AM43XX_CM_GFX_INST 0x8400
#define AM43XX_CM_RTC_INST 0x8500
......@@ -74,89 +62,7 @@
#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
/* CLK CTRL offsets */
#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580
#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588
#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590
#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598
#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0
#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428
#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430
#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468
#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438
#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440
#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448
#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478
#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480
#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488
#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8
#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0
#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8
#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0
#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8
#define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0
#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500
#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508
#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528
#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530
#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538
#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540
#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548
#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550
#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558
#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228
#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360
#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350
#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358
#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348
#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328
#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340
#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368
#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120
#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338
#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220
#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020
#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248
#define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258
#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220
#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238
#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240
#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420
#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020
#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078
#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080
#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088
#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090
#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20
#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320
#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0
#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040
#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050
#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058
#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028
#define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030
#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560
#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568
#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570
#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578
#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230
#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450
#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458
#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460
#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510
#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518
#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520
#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490
#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498
#define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260
#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8
#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268
#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0
#define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068
#define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070
#define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720
#endif
......@@ -35,63 +35,27 @@
#define AM33XX_PRM_GFX_MOD 0x1100
#define AM33XX_PRM_CEFUSE_MOD 0x1200
/* PRM */
/* PRM.OCP_SOCKET_PRM register offsets */
#define AM33XX_REVISION_PRM_OFFSET 0x0000
#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c
#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010
#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
/* PRM.PER_PRM register offsets */
#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
#define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
/* PRM.WKUP_PRM register offsets */
#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000
#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004
#define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
#define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008
#define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c
#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
/* PRM.MPU_PRM register offsets */
#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
#define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
#define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008
#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
/* PRM.DEVICE_PRM register offsets */
#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
#define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
#define AM33XX_PRM_RSTTIME_OFFSET 0x0004
#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
#define AM33XX_PRM_RSTST_OFFSET 0x0008
#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c
#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010
#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014
#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018
#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c
#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
/* PRM.RTC_PRM register offsets */
#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000
......@@ -102,12 +66,8 @@
/* PRM.GFX_PRM register offsets */
#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000
#define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004
#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
#define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010
#define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014
#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
/* PRM.CEFUSE_PRM register offsets */
#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
......
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......@@ -22,72 +22,7 @@
OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
/* Registers offset */
#define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000
#define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000)
#define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100
#define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100)
#define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104
#define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104)
#define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110
#define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110)
#define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118
#define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118)
#define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c
#define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c)
#define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200
#define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200)
#define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204
#define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204)
#define OMAP4_SCRM_PWRREQ_OFFSET 0x0208
#define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208)
#define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210
#define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210)
#define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214
#define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214)
#define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218
#define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218)
#define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c
#define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c)
#define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220
#define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220)
#define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224
#define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224)
#define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234
#define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234)
#define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310
#define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310)
#define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314
#define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314)
#define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318
#define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318)
#define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c
#define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c)
#define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320
#define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320)
#define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324
#define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324)
#define OMAP4_SCRM_RSTTIME_OFFSET 0x0400
#define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400)
#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418
#define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418)
#define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c
#define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c)
#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
#define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420)
#define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510
#define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510)
#define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514
#define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514)
#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518
#define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518)
#define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c
#define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c)
/* Registers shifts and masks */
/* REVISION_SCRM */
#define OMAP4_REV_SHIFT 0
#define OMAP4_REV_MASK (0xff << 0)
/* CLKSETUPTIME */
#define OMAP4_DOWNTIME_SHIFT 16
......@@ -95,80 +30,4 @@
#define OMAP4_SETUPTIME_SHIFT 0
#define OMAP4_SETUPTIME_MASK (0xfff << 0)
/* PMICSETUPTIME */
#define OMAP4_WAKEUPTIME_SHIFT 16
#define OMAP4_WAKEUPTIME_MASK (0x3f << 16)
#define OMAP4_SLEEPTIME_SHIFT 0
#define OMAP4_SLEEPTIME_MASK (0x3f << 0)
/* ALTCLKSRC */
#define OMAP4_ENABLE_EXT_SHIFT 3
#define OMAP4_ENABLE_EXT_MASK (1 << 3)
#define OMAP4_ENABLE_INT_SHIFT 2
#define OMAP4_ENABLE_INT_MASK (1 << 2)
#define OMAP4_ALTCLKSRC_MODE_SHIFT 0
#define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0)
/* MODEMCLKM */
#define OMAP4_CLK_32KHZ_SHIFT 0
#define OMAP4_CLK_32KHZ_MASK (1 << 0)
/* D2DCLKM */
#define OMAP4_SYSCLK_SHIFT 1
#define OMAP4_SYSCLK_MASK (1 << 1)
/* EXTCLKREQ */
#define OMAP4_POLARITY_SHIFT 0
#define OMAP4_POLARITY_MASK (1 << 0)
/* AUXCLKREQ0 */
#define OMAP4_MAPPING_SHIFT 2
#define OMAP4_MAPPING_MASK (0x7 << 2)
#define OMAP4_MAPPING_WIDTH 3
#define OMAP4_ACCURACY_SHIFT 1
#define OMAP4_ACCURACY_MASK (1 << 1)
/* AUXCLK0 */
#define OMAP4_CLKDIV_SHIFT 16
#define OMAP4_CLKDIV_MASK (0xf << 16)
#define OMAP4_CLKDIV_WIDTH 4
#define OMAP4_DISABLECLK_SHIFT 9
#define OMAP4_DISABLECLK_MASK (1 << 9)
#define OMAP4_ENABLE_SHIFT 8
#define OMAP4_ENABLE_MASK (1 << 8)
#define OMAP4_SRCSELECT_SHIFT 1
#define OMAP4_SRCSELECT_MASK (0x3 << 1)
/* RSTTIME */
#define OMAP4_RSTTIME_SHIFT 0
#define OMAP4_RSTTIME_MASK (0xf << 0)
/* MODEMRSTCTRL */
#define OMAP4_WARMRST_SHIFT 1
#define OMAP4_WARMRST_MASK (1 << 1)
#define OMAP4_COLDRST_SHIFT 0
#define OMAP4_COLDRST_MASK (1 << 0)
/* EXTPWRONRSTCTRL */
#define OMAP4_PWRONRST_SHIFT 1
#define OMAP4_PWRONRST_MASK (1 << 1)
#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0
#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0)
/* EXTWARMRSTST */
#define OMAP4_EXTWARMRSTST_SHIFT 0
#define OMAP4_EXTWARMRSTST_MASK (1 << 0)
/* APEWARMRSTST */
#define OMAP4_APEWARMRSTST_SHIFT 1
#define OMAP4_APEWARMRSTST_MASK (1 << 1)
/* MODEMWARMRSTST */
#define OMAP4_MODEMWARMRSTST_SHIFT 2
#define OMAP4_MODEMWARMRSTST_MASK (1 << 2)
/* D2DWARMRSTST */
#define OMAP4_D2DWARMRSTST_SHIFT 3
#define OMAP4_D2DWARMRSTST_MASK (1 << 3)
#endif
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* OMAP54XX SCRM registers and bitfields
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
#define OMAP5_SCRM_BASE 0x4ae0a000
#define OMAP54XX_SCRM_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
/* SCRM */
/* SCRM.SCRM register offsets */
#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
/*
* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
* AUXCLKREQ5, D2DCLKREQ
*/
#define OMAP5_ACCURACY_SHIFT 1
#define OMAP5_ACCURACY_WIDTH 0x1
#define OMAP5_ACCURACY_MASK (1 << 1)
/* Used by APEWARMRSTST */
#define OMAP5_APEWARMRSTST_SHIFT 1
#define OMAP5_APEWARMRSTST_WIDTH 0x1
#define OMAP5_APEWARMRSTST_MASK (1 << 1)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_CLKDIV_SHIFT 16
#define OMAP5_CLKDIV_WIDTH 0x4
#define OMAP5_CLKDIV_MASK (0xf << 16)
/* Used by D2DCLKM, MODEMCLKM */
#define OMAP5_CLK_32KHZ_SHIFT 0
#define OMAP5_CLK_32KHZ_WIDTH 0x1
#define OMAP5_CLK_32KHZ_MASK (1 << 0)
/* Used by D2DRSTCTRL, MODEMRSTCTRL */
#define OMAP5_COLDRST_SHIFT 0
#define OMAP5_COLDRST_WIDTH 0x1
#define OMAP5_COLDRST_MASK (1 << 0)
/* Used by D2DWARMRSTST */
#define OMAP5_D2DWARMRSTST_SHIFT 3
#define OMAP5_D2DWARMRSTST_WIDTH 0x1
#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
/* Used by AUXCLK0 */
#define OMAP5_DISABLECLK_SHIFT 9
#define OMAP5_DISABLECLK_WIDTH 0x1
#define OMAP5_DISABLECLK_MASK (1 << 9)
/* Used by CLKSETUPTIME */
#define OMAP5_DOWNTIME_SHIFT 16
#define OMAP5_DOWNTIME_WIDTH 0x6
#define OMAP5_DOWNTIME_MASK (0x3f << 16)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_ENABLE_SHIFT 8
#define OMAP5_ENABLE_WIDTH 0x1
#define OMAP5_ENABLE_MASK (1 << 8)
/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
#define OMAP5_ENABLE_0_0_SHIFT 0
#define OMAP5_ENABLE_0_0_WIDTH 0x1
#define OMAP5_ENABLE_0_0_MASK (1 << 0)
/* Used by ALTCLKSRC */
#define OMAP5_ENABLE_EXT_SHIFT 3
#define OMAP5_ENABLE_EXT_WIDTH 0x1
#define OMAP5_ENABLE_EXT_MASK (1 << 3)
/* Used by ALTCLKSRC */
#define OMAP5_ENABLE_INT_SHIFT 2
#define OMAP5_ENABLE_INT_WIDTH 0x1
#define OMAP5_ENABLE_INT_MASK (1 << 2)
/* Used by EXTWARMRSTST */
#define OMAP5_EXTWARMRSTST_SHIFT 0
#define OMAP5_EXTWARMRSTST_WIDTH 0x1
#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
/*
* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
* AUXCLKREQ5
*/
#define OMAP5_MAPPING_SHIFT 2
#define OMAP5_MAPPING_WIDTH 0x3
#define OMAP5_MAPPING_MASK (0x7 << 2)
/* Used by ALTCLKSRC */
#define OMAP5_MODE_SHIFT 0
#define OMAP5_MODE_WIDTH 0x2
#define OMAP5_MODE_MASK (0x3 << 0)
/* Used by MODEMWARMRSTST */
#define OMAP5_MODEMWARMRSTST_SHIFT 2
#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
/*
* Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
* AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
* D2DCLKREQ, EXTCLKREQ, PWRREQ
*/
#define OMAP5_POLARITY_SHIFT 0
#define OMAP5_POLARITY_WIDTH 0x1
#define OMAP5_POLARITY_MASK (1 << 0)
/* Used by EXTPWRONRSTCTRL */
#define OMAP5_PWRONRST_SHIFT 1
#define OMAP5_PWRONRST_WIDTH 0x1
#define OMAP5_PWRONRST_MASK (1 << 1)
/* Used by REVISION_SCRM */
#define OMAP5_REV_SHIFT 0
#define OMAP5_REV_WIDTH 0x8
#define OMAP5_REV_MASK (0xff << 0)
/* Used by RSTTIME */
#define OMAP5_RSTTIME_SHIFT 0
#define OMAP5_RSTTIME_WIDTH 0x4
#define OMAP5_RSTTIME_MASK (0xf << 0)
/* Used by CLKSETUPTIME */
#define OMAP5_SETUPTIME_SHIFT 0
#define OMAP5_SETUPTIME_WIDTH 0xc
#define OMAP5_SETUPTIME_MASK (0xfff << 0)
/* Used by PMICSETUPTIME */
#define OMAP5_SLEEPTIME_SHIFT 0
#define OMAP5_SLEEPTIME_WIDTH 0x6
#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_SRCSELECT_SHIFT 1
#define OMAP5_SRCSELECT_WIDTH 0x2
#define OMAP5_SRCSELECT_MASK (0x3 << 1)
/* Used by D2DCLKM */
#define OMAP5_SYSCLK_SHIFT 1
#define OMAP5_SYSCLK_WIDTH 0x1
#define OMAP5_SYSCLK_MASK (1 << 1)
/* Used by PMICSETUPTIME */
#define OMAP5_WAKEUPTIME_SHIFT 16
#define OMAP5_WAKEUPTIME_WIDTH 0x6
#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
/* Used by D2DRSTCTRL, MODEMRSTCTRL */
#define OMAP5_WARMRST_SHIFT 1
#define OMAP5_WARMRST_WIDTH 0x1
#define OMAP5_WARMRST_MASK (1 << 1)
#endif
......@@ -361,11 +361,25 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
static asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
{
do {
if (likely(s3c_intc[0]))
/*
* For platform based machines, neither ERR nor NULL can happen here.
* The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds:
*
* s3c_intc[0] = s3c24xx_init_intc()
*
* If this fails, the next calls to s3c24xx_init_intc() won't be executed.
*
* For DT machine, s3c_init_intc_of() could set the IRQ handler without
* setting s3c_intc[0] only if it was called with num_ctrl=0. There is no
* such code path, so again the s3c_intc[0] will have a valid pointer if
* set_handle_irq() is called.
*
* Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something.
*/
if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
continue;
if (s3c_intc[2])
if (!IS_ERR_OR_NULL(s3c_intc[2]))
if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
continue;
......
......@@ -262,7 +262,7 @@ static char mini6410_features_str[12] __initdata = "0";
static int __init mini6410_features_setup(char *str)
{
if (str)
strlcpy(mini6410_features_str, str,
strscpy(mini6410_features_str, str,
sizeof(mini6410_features_str));
return 1;
}
......
......@@ -48,6 +48,14 @@ config MACH_STM32MP157
select ARM_ERRATA_814220
default y
config MACH_STM32MP13
bool "STMicroelectronics STM32MP13x"
select ARM_ERRATA_814220
default y
help
Support for STM32MP13 SoCs:
STM32MP131, STM32MP133, STM32MP135
endif # ARMv7-A
endif
......@@ -18,6 +18,9 @@ static const char *const stm32_compat[] __initconst = {
"st,stm32f769",
"st,stm32h743",
"st,stm32h750",
"st,stm32mp131",
"st,stm32mp133",
"st,stm32mp135",
"st,stm32mp157",
NULL
};
......
// SPDX-License-Identifier: GPL-2.0
/*
* SMP support for Allwinner SoCs
*
......@@ -8,9 +9,6 @@
* Based on code
* Copyright (C) 2012-2013 Allwinner Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/delay.h>
......
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree support for Allwinner A1X SoCs
*
......@@ -5,9 +6,6 @@
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clocksource.h>
......
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