Merge bk://68.0.152.218/linux-2.5-8xx

into samba.org:/home/paulus/kernel/for-linus-ppc

arch/ppc/8xx_io/Kconfig

@@ -51,6 +51,22 @@ config USE_MDIO
 	  all MII code can be omitted. Say N here if unsure or if you don't
 	  need link status reports.
 
+config  FEC_AM79C874
+	bool "Support AMD79C874 PHY"
+	depends on USE_MDIO
+
+config FEC_LXT970
+	bool "Support LXT970 PHY"
+	depends on USE_MDIO
+
+config FEC_LXT971
+	bool "Support LXT971 PHY"
+	depends on USE_MDIO
+	
+config FEC_QS6612
+	bool "Support QS6612 PHY"
+	depends on USE_MDIO
+	
 config ENET_BIG_BUFFERS
 	bool "Use Big CPM Ethernet Buffers"
 	depends on NET_ETHERNET

arch/ppc/8xx_io/fec.c

@@ -22,15 +22,12 @@
  *
  * Make use of MII for PHY control configurable.
  * Some fixes.
- * Copyright (c) 2000 Wolfgang Denk, DENX Software Engineering.
+ * Copyright (c) 2000-2002 Wolfgang Denk, DENX Software Engineering.
+ *
+ * Support for AMD AM79C874 added.
+ * Thomas Lange, thomas@corelatus.com
  */
 
-/* List of PHYs we wish to support.
-*/
-#undef	CONFIG_FEC_LXT970
-#define	CONFIG_FEC_LXT971
-#undef	CONFIG_FEC_QS6612
-
 #include <linux/config.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -1137,9 +1134,74 @@ static phy_info_t phy_info_qs6612 = {
 	},
 };
 
-
 #endif /* CONFIG_FEC_QS6612 */
 
+/* ------------------------------------------------------------------------- */
+/* The Advanced Micro Devices AM79C874 is used on the ICU862		     */
+
+#ifdef CONFIG_FEC_AM79C874
+
+/* register definitions for the 79C874 */
+
+#define MII_AM79C874_MFR	16  /* Miscellaneous Features Register      */
+#define MII_AM79C874_ICSR	17  /* Interrupt Control/Status Register    */
+#define MII_AM79C874_DR		18  /* Diagnostic Register		    */
+#define MII_AM79C874_PMLR	19  /* Power Management & Loopback Register */
+#define MII_AM79C874_MCR	21  /* Mode Control Register		    */
+#define MII_AM79C874_DC		23  /* Disconnect Counter		    */
+#define MII_AM79C874_REC	24  /* Receiver Error Counter		    */
+
+static void mii_parse_amd79c874_dr(uint mii_reg, struct net_device *dev, uint data)
+{
+	volatile struct fec_enet_private *fep = dev->priv;
+	uint s = fep->phy_status;
+
+	s &= ~(PHY_STAT_SPMASK);
+
+	/* Register 18: Bit 10 is data rate, 11 is Duplex */
+	switch ((mii_reg >> 10) & 3) {
+	case 0:	s |= PHY_STAT_10HDX;	break;
+	case 1:	s |= PHY_STAT_100HDX;	break;
+	case 2:	s |= PHY_STAT_10FDX;	break;
+	case 3:	s |= PHY_STAT_100FDX;	break;
+	}
+
+	fep->phy_status = s;
+}
+
+static phy_info_t phy_info_amd79c874 = {
+	0x00022561,
+	"AM79C874",
+
+	(const phy_cmd_t []) {  /* config */
+//		{ mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10  Mbps, HD */
+		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
+		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
+		{ mk_mii_end, }
+	},
+	(const phy_cmd_t []) {  /* startup - enable interrupts */
+		{ mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
+		{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
+		{ mk_mii_end, }
+	},
+	(const phy_cmd_t []) { /* ack_int */
+		/* find out the current status */
+
+		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
+		{ mk_mii_read(MII_AM79C874_DR), mii_parse_amd79c874_dr },
+
+		/* we only need to read ICSR to acknowledge */
+
+		{ mk_mii_read(MII_AM79C874_ICSR), NULL },
+		{ mk_mii_end, }
+	},
+	(const phy_cmd_t []) {  /* shutdown - disable interrupts */
+		{ mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
+		{ mk_mii_end, }
+	},
+};
+
+#endif /* CONFIG_FEC_AM79C874 */
 
 static phy_info_t *phy_info[] = {
 
@@ -1153,7 +1215,11 @@ static phy_info_t *phy_info[] = {
 
 #ifdef CONFIG_FEC_QS6612
 	&phy_info_qs6612,
-#endif /* CONFIG_FEC_LXT971 */
+#endif /* CONFIG_FEC_QS6612 */
+
+#ifdef CONFIG_FEC_AM79C874
+	&phy_info_amd79c874,
+#endif /* CONFIG_FEC_AM79C874 */
 
 	NULL
 };

arch/ppc/platforms/ccm.h

 /*
  * Siemens Card Controller Module specific definitions
  * 
- * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
+ * Copyright (C) 2001-2002 Wolfgang Denk (wd@denx.de)
  */
 
 #ifndef __MACH_CCM_H
@@ -17,9 +17,9 @@
 #define	IMAP_ADDR     CCM_IMMR_BASE	/* physical base address of IMMR area	*/
 #define IMAP_SIZE     CCM_IMAP_SIZE	/* mapped size of IMMR area		*/
 
-#define	FEC_INTERRUPT	15		/* = SIU_LEVEL7				*/
-#define	DEC_INTERRUPT	13		/* = SIU_LEVEL6				*/
-#define	CPM_INTERRUPT	11		/* = SIU_LEVEL5 (was: SIU_LEVEL2)	*/
+#define	FEC_INTERRUPT	13		/* = SIU_LEVEL6				*/
+#define	DEC_INTERRUPT	11		/* = SIU_LEVEL5				*/
+#define	CPM_INTERRUPT	 9		/* = SIU_LEVEL4				*/
 
 /* We don't use the 8259.
 */

arch/ppc/platforms/tqm8xx.h

 /*
  * TQM8xx(L) board specific definitions
  * 
- * Copyright (c) 1999,2000,2001 Wolfgang Denk (wd@denx.de)
+ * Copyright (c) 1999-2002 Wolfgang Denk (wd@denx.de)
  */
 
 #ifdef __KERNEL__
@@ -26,7 +26,27 @@
  */
 #define PCMCIA_MEM_SIZE		( 64 << 20 )
 
-#define	MAX_HWIFS	1	/* overwrite default in include/asm-ppc/ide.h */
+#ifndef CONFIG_KUP4K
+# define	MAX_HWIFS	1	/* overwrite default in include/asm-ppc/ide.h	*/
+
+#else	/* CONFIG_KUP4K */
+
+# define	MAX_HWIFS	2	/* overwrite default in include/asm-ppc/ide.h	*/
+# ifndef __ASSEMBLY__
+# include <asm/8xx_immap.h>
+static __inline__ void ide_led(int on)
+{
+	volatile immap_t	*immap = (immap_t *)IMAP_ADDR;
+
+	if (on) {
+		immap->im_ioport.iop_padat &= ~0x80;
+	} else {
+		immap->im_ioport.iop_padat |= 0x80;
+	}
+}
+# endif	/* __ASSEMBLY__ */
+# define IDE_LED(x) ide_led((x))
+#endif	/* CONFIG_KUP4K */
 
 /*
  * Definitions for IDE0 Interface
@@ -43,8 +63,18 @@
 #define IDE0_CONTROL_REG_OFFSET		0x0106
 #define IDE0_IRQ_REG_OFFSET		0x000A	/* not used */
 
+/* define IO_BASE for PCMCIA */
+#define _IO_BASE 0x80000000
+#define _IO_BASE_SIZE  (64<<10)
+
+#define	FEC_INTERRUPT		 9	/* = SIU_LEVEL4			*/
+#define PHY_INTERRUPT		12	/* = IRQ6			*/
 #define	IDE0_INTERRUPT		13
 
+#ifdef CONFIG_IDE
+#define ide_request_irq(irq,hand,flg,dev,id)    \
+        request_8xxirq((irq),(hand),(flg),(dev),(id))
+#endif
 
 /*-----------------------------------------------------------------------
  * CPM Ethernet through SCCx.

include/asm-ppc/commproc.h

@@ -35,7 +35,9 @@
 #define CPM_CR_HUNT_MODE	((ushort)0x0003)
 #define CPM_CR_STOP_TX		((ushort)0x0004)
 #define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_CLOSE_RX_BD	((ushort)0x0007)
 #define CPM_CR_SET_GADDR	((ushort)0x0008)
+#define CPM_CR_SET_TIMER	CPM_CR_SET_GADDR
 
 /* Channel numbers.
 */
@@ -43,6 +45,7 @@
 #define CPM_CR_CH_I2C		((ushort)0x0001)	/* I2C and IDMA1 */
 #define CPM_CR_CH_SCC2		((ushort)0x0004)
 #define CPM_CR_CH_SPI		((ushort)0x0005)	/* SPI / IDMA2 / Timers */
+#define CPM_CR_CH_TIMER		CPM_CR_CH_SPI
 #define CPM_CR_CH_SCC3		((ushort)0x0008)
 #define CPM_CR_CH_SMC1		((ushort)0x0009)	/* SMC1 / DSP1 */
 #define CPM_CR_CH_SCC4		((ushort)0x000c)
@@ -80,20 +83,25 @@ typedef struct cpm_buf_desc {
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
 #define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
 #define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_NAK	((ushort)0x0004)	/* NAK - did not respond */
 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_UN	((ushort)0x0002)	/* Underrun */
 #define BD_SC_CD	((ushort)0x0001)	/* ?? */
+#define BD_SC_CL	((ushort)0x0001)	/* Collision */
 
 /* Parameter RAM offsets.
 */
 #define PROFF_SCC1	((uint)0x0000)
 #define PROFF_IIC	((uint)0x0080)
 #define PROFF_SCC2	((uint)0x0100)
+#define PROFF_SPI	((uint)0x0180)
 #define PROFF_SCC3	((uint)0x0200)
 #define PROFF_SMC1	((uint)0x0280)
 #define PROFF_SCC4	((uint)0x0300)
@@ -208,6 +216,17 @@ typedef struct smc_centronics {
 #define CPM_BRG_CD_MASK		((uint)0x00001ffe)
 #define CPM_BRG_DIV16		((uint)0x00000001)
 
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
+
 /* SCCs.
 */
 #define SCC_GSMRH_IRP		((uint)0x00040000)
@@ -417,6 +436,8 @@ typedef struct scc_enet {
 #define BD_ENET_RX_CR		((ushort)0x0004)
 #define BD_ENET_RX_OV		((ushort)0x0002)
 #define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_BC		((ushort)0x0080)	/* DA is Broadcast */
+#define BD_ENET_RX_MC		((ushort)0x0040)	/* DA is Multicast */
 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
 
 /* Buffer descriptor control/status used by Ethernet transmit.
@@ -525,10 +546,84 @@ typedef struct iic {
 	ushort	iic_tbptr;	/* Internal */
 	ushort	iic_tbc;	/* Internal */
 	uint	iic_txtmp;	/* Internal */
+	uint	iic_res;	/* reserved */
+  	ushort	iic_rpbase;	/* Relocation pointer */
+	ushort	iic_res2;	/* reserved */
 } iic_t;
 
 #define BD_IIC_START		((ushort)0x0400)
  
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;
+	ushort	spi_rpbase;	/* Relocation pointer */
+	ushort	spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_LEN4	((ushort)0x0030)	/*  4 bits per char */
+#define SPMODE_LEN8	((ushort)0x0070)	/*  8 bits per char */
+#define SPMODE_LEN16	((ushort)0x00f0)	/* 16 bits per char */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+/* SPIE fields */
+#define SPIE_MME	0x20
+#define SPIE_TXE	0x10
+#define SPIE_BSY	0x04
+#define SPIE_TXB	0x02
+#define SPIE_RXB	0x01
+
+/*
+ * RISC Controller Configuration Register definitons
+ */
+#define RCCR_TIME	0x8000			/* RISC Timer Enable */
+#define RCCR_TIMEP(t)	(((t) & 0x3F)<<8)	/* RISC Timer Period */
+#define RCCR_TIME_MASK	0x00FF			/* not RISC Timer related bits */
+
+/* RISC Timer Parameter RAM offset */
+#define PROFF_RTMR	((uint)0x01B0)
+
+typedef struct risc_timer_pram {
+	unsigned short	tm_base;	/* RISC Timer Table Base Address */
+	unsigned short	tm_ptr;		/* RISC Timer Table Pointer (internal) */
+	unsigned short	r_tmr;		/* RISC Timer Mode Register */
+	unsigned short	r_tmv;		/* RISC Timer Valid Register */
+	unsigned long	tm_cmd;		/* RISC Timer Command Register */
+	unsigned long	tm_cnt;		/* RISC Timer Internal Count */
+} rt_pram_t;
+
+/* Bits in RISC Timer Command Register */
+#define TM_CMD_VALID	0x80000000	/* Valid - Enables the timer */
+#define TM_CMD_RESTART	0x40000000	/* Restart - for automatic restart */
+#define TM_CMD_PWM	0x20000000	/* Run in Pulse Width Modulation Mode */
+#define TM_CMD_NUM(n)	(((n)&0xF)<<16)	/* Timer Number */
+#define TM_CMD_PERIOD(p) ((p)&0xFFFF)	/* Timer Period */
+
 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
  * channels or devices.  All of these are presented to the PPC core
  * as a single interrupt.  The CPM interrupt handler dispatches its