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Commit 22e9af4e authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://kernel.bkbits.net/davem/sparc-2.6 

into ppc970.osdl.org:/home/torvalds/v2.5/linux
parents 558dadec 333876f3
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Showing with 136 additions and 790 deletions
drivers/ide/ide-disk.c
View file @ 22e9af4e
This diff is collapsed.
drivers/ide/ide-io.c
View file @ 22e9af4e
......@@ -197,7 +197,7 @@ void ide_end_drive_cmd (ide_drive_t *drive, u8 stat, u8 err)
if (args->tf_in_flags.b.data) {
u16 data = hwif->INW(IDE_DATA_REG);
args->tfRegister[IDE_DATA_OFFSET] = (data) & 0xFF;
args->hobRegister[IDE_DATA_OFFSET_HOB] = (data >> 8) & 0xFF;
args->hobRegister[IDE_DATA_OFFSET] = (data >> 8) & 0xFF;
}
args->tfRegister[IDE_ERROR_OFFSET] = err;
args->tfRegister[IDE_NSECTOR_OFFSET] = hwif->INB(IDE_NSECTOR_REG);
......@@ -208,12 +208,12 @@ void ide_end_drive_cmd (ide_drive_t *drive, u8 stat, u8 err)
args->tfRegister[IDE_STATUS_OFFSET] = stat;
if (drive->addressing == 1) {
hwif->OUTB(drive->ctl|0x80, IDE_CONTROL_REG_HOB);
args->hobRegister[IDE_FEATURE_OFFSET_HOB] = hwif->INB(IDE_FEATURE_REG);
args->hobRegister[IDE_NSECTOR_OFFSET_HOB] = hwif->INB(IDE_NSECTOR_REG);
args->hobRegister[IDE_SECTOR_OFFSET_HOB] = hwif->INB(IDE_SECTOR_REG);
args->hobRegister[IDE_LCYL_OFFSET_HOB] = hwif->INB(IDE_LCYL_REG);
args->hobRegister[IDE_HCYL_OFFSET_HOB] = hwif->INB(IDE_HCYL_REG);
hwif->OUTB(drive->ctl|0x80, IDE_CONTROL_REG);
args->hobRegister[IDE_FEATURE_OFFSET] = hwif->INB(IDE_FEATURE_REG);
args->hobRegister[IDE_NSECTOR_OFFSET] = hwif->INB(IDE_NSECTOR_REG);
args->hobRegister[IDE_SECTOR_OFFSET] = hwif->INB(IDE_SECTOR_REG);
args->hobRegister[IDE_LCYL_OFFSET] = hwif->INB(IDE_LCYL_REG);
args->hobRegister[IDE_HCYL_OFFSET] = hwif->INB(IDE_HCYL_REG);
}
}
} else if (blk_pm_request(rq)) {
......
drivers/ide/ide-taskfile.c
View file @ 22e9af4e
This diff is collapsed.
drivers/ide/ide-tcq.c
View file @ 22e9af4e
......@@ -483,7 +483,7 @@ static int ide_tcq_check_autopoll(ide_drive_t *drive)
args->tfRegister[IDE_FEATURE_OFFSET] = 0x01;
args->tfRegister[IDE_COMMAND_OFFSET] = WIN_NOP;
args->command_type = ide_cmd_type_parser(args);
args->command_type = IDE_DRIVE_TASK_NO_DATA;
args->handler = ide_tcq_nop_handler;
return ide_raw_taskfile(drive, args, NULL);
}
......@@ -513,7 +513,8 @@ static int ide_tcq_configure(ide_drive_t *drive)
memset(args, 0, sizeof(ide_task_t));
args->tfRegister[IDE_COMMAND_OFFSET] = WIN_SETFEATURES;
args->tfRegister[IDE_FEATURE_OFFSET] = SETFEATURES_EN_WCACHE;
args->command_type = ide_cmd_type_parser(args);
args->command_type = IDE_DRIVE_TASK_NO_DATA;
args->handler = &task_no_data_intr;
if (ide_raw_taskfile(drive, args, NULL)) {
printk(KERN_WARNING "%s: failed to enable write cache\n", drive->name);
......@@ -527,7 +528,8 @@ static int ide_tcq_configure(ide_drive_t *drive)
memset(args, 0, sizeof(ide_task_t));
args->tfRegister[IDE_COMMAND_OFFSET] = WIN_SETFEATURES;
args->tfRegister[IDE_FEATURE_OFFSET] = SETFEATURES_DIS_RI;
args->command_type = ide_cmd_type_parser(args);
args->command_type = IDE_DRIVE_TASK_NO_DATA;
args->handler = &task_no_data_intr;
if (ide_raw_taskfile(drive, args, NULL)) {
printk(KERN_ERR "%s: disabling release interrupt fail\n", drive->name);
......@@ -541,7 +543,8 @@ static int ide_tcq_configure(ide_drive_t *drive)
memset(args, 0, sizeof(ide_task_t));
args->tfRegister[IDE_COMMAND_OFFSET] = WIN_SETFEATURES;
args->tfRegister[IDE_FEATURE_OFFSET] = SETFEATURES_EN_SI;
args->command_type = ide_cmd_type_parser(args);
args->command_type = IDE_DRIVE_TASK_NO_DATA;
args->handler = &task_no_data_intr;
if (ide_raw_taskfile(drive, args, NULL)) {
printk(KERN_ERR "%s: enabling service interrupt fail\n", drive->name);
......
drivers/ide/legacy/pdc4030.c
View file @ 22e9af4e
......@@ -814,10 +814,9 @@ static ide_startstop_t promise_rw_disk (ide_drive_t *drive, struct request *rq,
memcpy(args.tfRegister, &taskfile, sizeof(struct hd_drive_task_hdr));
memset(args.hobRegister, 0, sizeof(struct hd_drive_hob_hdr));
/* We can't call ide_cmd_type_parser here, since it won't understand
our command, but that doesn't matter, since we don't use the
generic interrupt handlers either. Setup the bits of args that we
do need.
/*
* Setup the bits of args that we do need.
* Note that we don't use the generic interrupt handlers.
*/
args.handler = NULL;
args.rq = (struct request *) rq;
......
drivers/ide/pci/pdc202xx_new.c
View file @ 22e9af4e
......@@ -140,108 +140,6 @@ static int check_in_drive_lists (ide_drive_t *drive, const char **list)
return 0;
}
static int pdcnew_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
u8 drive_pci = 0x60 + (drive->dn << 2);
u8 speed = ide_rate_filter(pdcnew_ratemask(drive), xferspeed);
u32 drive_conf;
u8 AP, BP, CP, DP;
u8 TA = 0, TB = 0, TC = 0;
if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
return -1;
pci_read_config_dword(dev, drive_pci, &drive_conf);
pci_read_config_byte(dev, (drive_pci), &AP);
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
if (speed < XFER_SW_DMA_0) {
if ((AP & 0x0F) || (BP & 0x07)) {
/* clear PIO modes of lower 8421 bits of A Register */
pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
pci_read_config_byte(dev, (drive_pci), &AP);
/* clear PIO modes of lower 421 bits of B Register */
pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
pci_read_config_byte(dev, (drive_pci), &AP);
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
}
} else {
if ((BP & 0xF0) && (CP & 0x0F)) {
/* clear DMA modes of upper 842 bits of B Register */
/* clear PIO forced mode upper 1 bit of B Register */
pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
/* clear DMA modes of lower 8421 bits of C Register */
pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
}
}
pci_read_config_byte(dev, (drive_pci), &AP);
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
switch(speed) {
case XFER_UDMA_6: speed = XFER_UDMA_5;
case XFER_UDMA_5:
case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
case XFER_UDMA_3:
case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
case XFER_UDMA_0:
case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
case XFER_MW_DMA_0:
case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
case XFER_PIO_0:
default: TA = 0x09; TB = 0x13; break;
}
if (speed < XFER_SW_DMA_0) {
pci_write_config_byte(dev, (drive_pci), AP|TA);
pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
} else {
pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
}
#if PDC202XX_DECODE_REGISTER_INFO
pci_read_config_byte(dev, (drive_pci), &AP);
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
decode_registers(REG_A, AP);
decode_registers(REG_B, BP);
decode_registers(REG_C, CP);
decode_registers(REG_D, DP);
#endif /* PDC202XX_DECODE_REGISTER_INFO */
#if PDC202XX_DEBUG_DRIVE_INFO
printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
drive->name, ide_xfer_verbose(speed),
drive->dn, drive_conf);
pci_read_config_dword(dev, drive_pci, &drive_conf);
printk("0x%08x\n", drive_conf);
#endif /* PDC202XX_DEBUG_DRIVE_INFO */
return (ide_config_drive_speed(drive, speed));
}
static int pdcnew_new_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
ide_hwif_t *hwif = HWIF(drive);
......@@ -288,19 +186,14 @@ static int pdcnew_new_tune_chipset (ide_drive_t *drive, u8 xferspeed)
* 180, 120, 90, 90, 90, 60, 30
* 11, 5, 4, 3, 2, 1, 0
*/
static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
{
u8 speed = 0;
u8 speed;
if (pio == 5) pio = 4;
speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
return ((int) pdcnew_tune_chipset(drive, speed));
}
static void pdcnew_tune_drive (ide_drive_t *drive, u8 pio)
{
(void) config_chipset_for_pio(drive, pio);
(void)pdcnew_new_tune_chipset(drive, speed);
}
static u8 pdcnew_new_cable_detect (ide_hwif_t *hwif)
......@@ -312,56 +205,15 @@ static int config_chipset_for_dma (ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
u8 speed = -1;
u8 cable = 0;
u8 cable;
u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
(id->dma_ultra & 0x0008)) ? 1 : 0;
switch(dev->device) {
case PCI_DEVICE_ID_PROMISE_20277:
case PCI_DEVICE_ID_PROMISE_20276:
case PCI_DEVICE_ID_PROMISE_20275:
case PCI_DEVICE_ID_PROMISE_20271:
case PCI_DEVICE_ID_PROMISE_20269:
case PCI_DEVICE_ID_PROMISE_20270:
case PCI_DEVICE_ID_PROMISE_20268:
cable = pdcnew_new_cable_detect(hwif);
#if PDC202_DEBUG_CABLE
printk(KERN_DEBUG "%s: %s-pin cable, %s-pin cable, %d\n",
hwif->name, hwif->udma_four ? "80" : "40",
cable ? "40" : "80", cable);
#endif /* PDC202_DEBUG_CABLE */
break;
default:
/* If it's not one we know we should never
arrive here.. */
BUG();
}
/*
* Set the control register to use the 66Mhz system
* clock for UDMA 3/4 mode operation. If one drive on
* a channel is U66 capable but the other isn't we
* fall back to U33 mode. The BIOS INT 13 hooks turn
* the clock on then off for each read/write issued. I don't
* do that here because it would require modifying the
* kernel, separating the fop routines from the kernel or
* somehow hooking the fops calls. It may also be possible to
* leave the 66Mhz clock on and readjust the timing
* parameters.
*/
if ((ultra_66) && (cable)) {
#ifdef DEBUG
printk(KERN_DEBUG "ULTRA 66/100/133: %s channel of Ultra 66/100/133 "
"requires an 80-pin cable for Ultra66 operation.\n",
hwif->channel ? "Secondary" : "Primary");
printk(KERN_DEBUG " Switching to Ultra33 mode.\n");
#endif /* DEBUG */
/* Primary : zero out second bit */
/* Secondary : zero out fourth bit */
if (ultra_66 && cable) {
printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
}
......@@ -590,10 +442,7 @@ static void __init init_hwif_pdc202new (ide_hwif_t *hwif)
hwif->speedproc = &pdcnew_new_tune_chipset;
hwif->resetproc = &pdcnew_new_reset;
if (!hwif->dma_base) {
hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
return;
}
hwif->ultra_mask = 0x7f;
hwif->mwdma_mask = 0x07;
......
drivers/ide/pci/pdc202xx_new.h
View file @ 22e9af4e
......@@ -5,15 +5,6 @@
#include <linux/pci.h>
#include <linux/ide.h>
#define DISPLAY_PDC202XX_TIMINGS
#ifndef SPLIT_BYTE
#define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
#endif
#define PDC202XX_DEBUG_DRIVE_INFO 0
#define PDC202XX_DECODE_REGISTER_INFO 0
const static char *pdc_quirk_drives[] = {
"QUANTUM FIREBALLlct08 08",
"QUANTUM FIREBALLP KA6.4",
......@@ -26,116 +17,6 @@ const static char *pdc_quirk_drives[] = {
NULL
};
/* A Register */
#define SYNC_ERRDY_EN 0xC0
#define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
#define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
#define IORDY_EN 0x20 /* PIO: IOREADY */
#define PREFETCH_EN 0x10 /* PIO: PREFETCH */
#define PA3 0x08 /* PIO"A" timing */
#define PA2 0x04 /* PIO"A" timing */
#define PA1 0x02 /* PIO"A" timing */
#define PA0 0x01 /* PIO"A" timing */
/* B Register */
#define MB2 0x80 /* DMA"B" timing */
#define MB1 0x40 /* DMA"B" timing */
#define MB0 0x20 /* DMA"B" timing */
#define PB4 0x10 /* PIO_FORCE 1:0 */
#define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
#define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
#define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
#define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
/* C Register */
#define IORDYp_NO_SPEED 0x4F
#define SPEED_DIS 0x0F
#define DMARQp 0x80
#define IORDYp 0x40
#define DMAR_EN 0x20
#define DMAW_EN 0x10
#define MC3 0x08 /* DMA"C" timing */
#define MC2 0x04 /* DMA"C" timing */
#define MC1 0x02 /* DMA"C" timing */
#define MC0 0x01 /* DMA"C" timing */
#if PDC202XX_DECODE_REGISTER_INFO
#define REG_A 0x01
#define REG_B 0x02
#define REG_C 0x04
#define REG_D 0x08
static void decode_registers (u8 registers, u8 value)
{
u8 bit = 0, bit1 = 0, bit2 = 0;
switch(registers) {
case REG_A:
bit2 = 0;
printk("A Register ");
if (value & 0x80) printk("SYNC_IN ");
if (value & 0x40) printk("ERRDY_EN ");
if (value & 0x20) printk("IORDY_EN ");
if (value & 0x10) printk("PREFETCH_EN ");
if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
printk("PIO(A) = %d ", bit2);
break;
case REG_B:
bit1 = 0;bit2 = 0;
printk("B Register ");
if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
printk("DMA(B) = %d ", bit1 >> 5);
if (value & 0x10) printk("PIO_FORCED/PB4 ");
if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
printk("PIO(B) = %d ", bit2);
break;
case REG_C:
bit2 = 0;
printk("C Register ");
if (value & 0x80) printk("DMARQp ");
if (value & 0x40) printk("IORDYp ");
if (value & 0x20) printk("DMAR_EN ");
if (value & 0x10) printk("DMAW_EN ");
if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
printk("DMA(C) = %d ", bit2);
break;
case REG_D:
printk("D Register ");
break;
default:
return;
}
printk("\n %s ", (registers & REG_D) ? "DP" :
(registers & REG_C) ? "CP" :
(registers & REG_B) ? "BP" :
(registers & REG_A) ? "AP" : "ERROR");
for (bit=128;bit>0;bit/=2)
printk("%s", (value & bit) ? "1" : "0");
printk("\n");
}
#endif /* PDC202XX_DECODE_REGISTER_INFO */
#define set_2regs(a, b) \
do { \
hwif->OUTB((a + adj), indexreg); \
......
drivers/ide/pci/piix.c
View file @ 22e9af4e
......@@ -814,7 +814,7 @@ static struct pci_driver driver = {
.probe = piix_init_one,
};
static int piix_ide_init(void)
static int __init piix_ide_init(void)
{
piix_check_450nx();
return ide_pci_register_driver(&driver);
......
drivers/scsi/sata_promise.c
View file @ 22e9af4e
......@@ -1791,13 +1791,7 @@ static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *
static int __init pdc_sata_init(void)
{
int rc;
rc = pci_module_init(&pdc_sata_pci_driver);
if (rc)
return rc;
return 0;
return pci_module_init(&pdc_sata_pci_driver);
}
......
drivers/scsi/sata_sil.c
View file @ 22e9af4e
......@@ -244,13 +244,9 @@ static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
{
unsigned int n, quirks = 0;
u32 class_rev = 0;
const char *s = &dev->product[0];
unsigned int len = strnlen(s, sizeof(dev->product));
pci_read_config_dword(ap->host_set->pdev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
/* ATAPI specifies that empty space is blank-filled; remove blanks */
while ((len > 0) && (s[len - 1] == ' '))
len--;
......@@ -263,7 +259,7 @@ static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
}
/* limit requests to 15 sectors */
if ((class_rev <= 0x01) && (quirks & SIL_QUIRK_MOD15WRITE)) {
if (quirks & SIL_QUIRK_MOD15WRITE) {
printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
ap->id, dev->devno);
ap->host->max_sectors = 15;
......@@ -272,7 +268,6 @@ static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
}
/* limit to udma5 */
/* is this for (class_rev <= 0x01) only, too? */
if (quirks & SIL_QUIRK_UDMA5MAX) {
printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
ap->id, dev->devno, s);
......@@ -405,13 +400,7 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
static int __init sil_init(void)
{
int rc;
rc = pci_module_init(&sil_pci_driver);
if (rc)
return rc;
return 0;
return pci_module_init(&sil_pci_driver);
}
static void __exit sil_exit(void)
......
drivers/scsi/sata_svw.c
View file @ 22e9af4e
......@@ -375,16 +375,9 @@ static struct pci_driver k2_sata_pci_driver = {
static int __init k2_sata_init(void)
{
int rc;
rc = pci_module_init(&k2_sata_pci_driver);
if (rc)
return rc;
return 0;
return pci_module_init(&k2_sata_pci_driver);
}
static void __exit k2_sata_exit(void)
{
pci_unregister_driver(&k2_sata_pci_driver);
......
drivers/scsi/sata_vsc.c
View file @ 22e9af4e
......@@ -5,25 +5,11 @@
*
* Bits from Jeff Garzik, Copyright RedHat, Inc.
*
* The contents of this file are subject to the Open
* Software License version 1.1 that can be found at
* http://www.opensource.org/licenses/osl-1.1.txt and is included herein
* by reference.
*
* Alternatively, the contents of this file may be used under the terms
* of the GNU General Public License version 2 (the "GPL") as distributed
* in the kernel source COPYING file, in which case the provisions of
* the GPL are applicable instead of the above. If you wish to allow
* the use of your version of this file only under the terms of the
* GPL and not to allow others to use your version of this file under
* the OSL, indicate your decision by deleting the provisions above and
* replace them with the notice and other provisions required by the GPL.
* If you do not delete the provisions above, a recipient may use your
* version of this file under either the OSL or the GPL.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
......@@ -232,7 +218,7 @@ static struct ata_port_operations vsc_sata_ops = {
.port_stop = ata_port_stop,
};
static void vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
{
port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
......@@ -252,7 +238,7 @@ static void vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
}
static int vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
static int printed_version;
struct ata_probe_ent *probe_ent = NULL;
......@@ -350,6 +336,11 @@ static int vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *
}
/*
* 0x1725/0x7174 is the Vitesse VSC-7174
* 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
* compatibility is untested as of yet
*/
static struct pci_device_id vsc_sata_pci_tbl[] = {
{ 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
{ 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
......@@ -367,13 +358,7 @@ static struct pci_driver vsc_sata_pci_driver = {
static int __init vsc_sata_init(void)
{
int rc;
rc = pci_module_init(&vsc_sata_pci_driver);
if (rc)
return rc;
return 0;
return pci_module_init(&vsc_sata_pci_driver);
}
......
include/linux/ide.h
View file @ 22e9af4e
......@@ -143,17 +143,8 @@ typedef unsigned char byte; /* used everywhere */
#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
#define IDE_DATA_OFFSET_HOB (0)
#define IDE_ERROR_OFFSET_HOB (1)
#define IDE_NSECTOR_OFFSET_HOB (2)
#define IDE_SECTOR_OFFSET_HOB (3)
#define IDE_LCYL_OFFSET_HOB (4)
#define IDE_HCYL_OFFSET_HOB (5)
#define IDE_SELECT_OFFSET_HOB (6)
#define IDE_CONTROL_OFFSET_HOB (7)
#define IDE_FEATURE_OFFSET_HOB IDE_ERROR_OFFSET_HOB
#define IDE_DATA_REG (HWIF(drive)->io_ports[IDE_DATA_OFFSET])
#define IDE_ERROR_REG (HWIF(drive)->io_ports[IDE_ERROR_OFFSET])
#define IDE_NSECTOR_REG (HWIF(drive)->io_ports[IDE_NSECTOR_OFFSET])
......@@ -165,16 +156,6 @@ typedef unsigned char byte; /* used everywhere */
#define IDE_CONTROL_REG (HWIF(drive)->io_ports[IDE_CONTROL_OFFSET])
#define IDE_IRQ_REG (HWIF(drive)->io_ports[IDE_IRQ_OFFSET])
#define IDE_DATA_REG_HOB (HWIF(drive)->io_ports[IDE_DATA_OFFSET])
#define IDE_ERROR_REG_HOB (HWIF(drive)->io_ports[IDE_ERROR_OFFSET])
#define IDE_NSECTOR_REG_HOB (HWIF(drive)->io_ports[IDE_NSECTOR_OFFSET])
#define IDE_SECTOR_REG_HOB (HWIF(drive)->io_ports[IDE_SECTOR_OFFSET])
#define IDE_LCYL_REG_HOB (HWIF(drive)->io_ports[IDE_LCYL_OFFSET])
#define IDE_HCYL_REG_HOB (HWIF(drive)->io_ports[IDE_HCYL_OFFSET])
#define IDE_SELECT_REG_HOB (HWIF(drive)->io_ports[IDE_SELECT_OFFSET])
#define IDE_STATUS_REG_HOB (HWIF(drive)->io_ports[IDE_STATUS_OFFSET])
#define IDE_CONTROL_REG_HOB (HWIF(drive)->io_ports[IDE_CONTROL_OFFSET])
#define IDE_FEATURE_REG IDE_ERROR_REG
#define IDE_COMMAND_REG IDE_STATUS_REG
#define IDE_ALTSTATUS_REG IDE_CONTROL_REG
......@@ -998,7 +979,6 @@ typedef struct hwif_s {
*/
typedef ide_startstop_t (ide_pre_handler_t)(ide_drive_t *, struct request *);
typedef ide_startstop_t (ide_handler_t)(ide_drive_t *);
typedef ide_startstop_t (ide_post_handler_t)(ide_drive_t *);
typedef int (ide_expiry_t)(ide_drive_t *);
typedef struct hwgroup_s {
......@@ -1360,7 +1340,6 @@ typedef struct ide_task_s {
int command_type;
ide_pre_handler_t *prehandler;
ide_handler_t *handler;
ide_post_handler_t *posthandler;
struct request *rq; /* copy of request */
void *special; /* valid_t generally */
} ide_task_t;
......@@ -1455,19 +1434,9 @@ extern ide_startstop_t pre_task_out_intr(ide_drive_t *, struct request *);
extern ide_startstop_t task_out_intr(ide_drive_t *);
extern ide_startstop_t pre_task_mulout_intr(ide_drive_t *, struct request *);
extern ide_startstop_t task_mulout_intr(ide_drive_t *);
extern void ide_init_drive_taskfile(struct request *);
extern int ide_raw_taskfile(ide_drive_t *, ide_task_t *, u8 *);
extern ide_pre_handler_t * ide_pre_handler_parser(struct hd_drive_task_hdr *, struct hd_drive_hob_hdr *);
extern ide_handler_t * ide_handler_parser(struct hd_drive_task_hdr *, struct hd_drive_hob_hdr *);
extern ide_post_handler_t * ide_post_handler_parser(struct hd_drive_task_hdr *, struct hd_drive_hob_hdr *);
/* Expects args is a full set of TF registers and parses the command type */
extern int ide_cmd_type_parser(ide_task_t *);
int ide_taskfile_ioctl(ide_drive_t *, unsigned int, unsigned long);
int ide_cmd_ioctl(ide_drive_t *, unsigned int, unsigned long);
int ide_task_ioctl(ide_drive_t *, unsigned int, unsigned long);
......
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