Commit 25b13dbc authored by Larry Finger's avatar Larry Finger Committed by John W. Linville

rtlwifi: Move common routines to core

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent f3355dd9
...@@ -72,16 +72,4 @@ ...@@ -72,16 +72,4 @@
#define BIT30 0x40000000 #define BIT30 0x40000000
#define BIT31 0x80000000 #define BIT31 0x80000000
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#endif /* __HALBT_PRECOMP_H__ */ #endif /* __HALBT_PRECOMP_H__ */
...@@ -36,6 +36,66 @@ ...@@ -36,6 +36,66 @@
#include <linux/export.h> #include <linux/export.h>
void rtl_addr_delay(u32 addr)
{
if (addr == 0xfe)
mdelay(50);
else if (addr == 0xfd)
mdelay(5);
else if (addr == 0xfc)
mdelay(1);
else if (addr == 0xfb)
udelay(50);
else if (addr == 0xfa)
udelay(5);
else if (addr == 0xf9)
udelay(1);
}
EXPORT_SYMBOL(rtl_addr_delay);
void rtl_rfreg_delay(struct ieee80211_hw *hw, enum radio_path rfpath, u32 addr,
u32 mask, u32 data)
{
if (addr == 0xfe) {
mdelay(50);
} else if (addr == 0xfd) {
mdelay(5);
} else if (addr == 0xfc) {
mdelay(1);
} else if (addr == 0xfb) {
udelay(50);
} else if (addr == 0xfa) {
udelay(5);
} else if (addr == 0xf9) {
udelay(1);
} else {
rtl_set_rfreg(hw, rfpath, addr, mask, data);
udelay(1);
}
}
EXPORT_SYMBOL(rtl_rfreg_delay);
void rtl_bb_delay(struct ieee80211_hw *hw, u32 addr, u32 data)
{
if (addr == 0xfe) {
mdelay(50);
} else if (addr == 0xfd) {
mdelay(5);
} else if (addr == 0xfc) {
mdelay(1);
} else if (addr == 0xfb) {
udelay(50);
} else if (addr == 0xfa) {
udelay(5);
} else if (addr == 0xf9) {
udelay(1);
} else {
rtl_set_bbreg(hw, addr, MASKDWORD, data);
udelay(1);
}
}
EXPORT_SYMBOL(rtl_bb_delay);
void rtl_fw_cb(const struct firmware *firmware, void *context) void rtl_fw_cb(const struct firmware *firmware, void *context)
{ {
struct ieee80211_hw *hw = context; struct ieee80211_hw *hw = context;
......
...@@ -41,5 +41,9 @@ ...@@ -41,5 +41,9 @@
extern const struct ieee80211_ops rtl_ops; extern const struct ieee80211_ops rtl_ops;
void rtl_fw_cb(const struct firmware *firmware, void *context); void rtl_fw_cb(const struct firmware *firmware, void *context);
void rtl_addr_delay(u32 addr);
void rtl_rfreg_delay(struct ieee80211_hw *hw, enum radio_path rfpath, u32 addr,
u32 mask, u32 data);
void rtl_bb_delay(struct ieee80211_hw *hw, u32 addr, u32 data);
#endif #endif
...@@ -32,6 +32,106 @@ ...@@ -32,6 +32,106 @@
#include "base.h" #include "base.h"
#include "ps.h" #include "ps.h"
/* Description:
* This routine deals with the Power Configuration CMD
* parsing for RTL8723/RTL8188E Series IC.
* Assumption:
* We should follow specific format that was released from HW SD.
*/
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
u8 faversion, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[])
{
struct wlan_pwr_cfg cfg_cmd = {0};
bool polling_bit = false;
u32 ary_idx = 0;
u8 value = 0;
u32 offset = 0;
u32 polling_count = 0;
u32 max_polling_cnt = 5000;
do {
cfg_cmd = pwrcfgcmd[ary_idx];
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x),"
"interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
GET_PWR_CFG_OFFSET(cfg_cmd),
GET_PWR_CFG_CUT_MASK(cfg_cmd),
GET_PWR_CFG_FAB_MASK(cfg_cmd),
GET_PWR_CFG_INTF_MASK(cfg_cmd),
GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd),
GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) &&
(GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) &&
(GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) {
switch (GET_PWR_CFG_CMD(cfg_cmd)) {
case PWR_CMD_READ:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
break;
case PWR_CMD_WRITE:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
offset = GET_PWR_CFG_OFFSET(cfg_cmd);
/*Read the value from system register*/
value = rtl_read_byte(rtlpriv, offset);
value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
value |= (GET_PWR_CFG_VALUE(cfg_cmd) &
GET_PWR_CFG_MASK(cfg_cmd));
/*Write the value back to sytem register*/
rtl_write_byte(rtlpriv, offset, value);
break;
case PWR_CMD_POLLING:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
polling_bit = false;
offset = GET_PWR_CFG_OFFSET(cfg_cmd);
do {
value = rtl_read_byte(rtlpriv, offset);
value &= GET_PWR_CFG_MASK(cfg_cmd);
if (value ==
(GET_PWR_CFG_VALUE(cfg_cmd)
& GET_PWR_CFG_MASK(cfg_cmd)))
polling_bit = true;
else
udelay(10);
if (polling_count++ > max_polling_cnt)
return false;
} while (!polling_bit);
break;
case PWR_CMD_DELAY:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
if (GET_PWR_CFG_VALUE(cfg_cmd) ==
PWRSEQ_DELAY_US)
udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
else
mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
break;
case PWR_CMD_END:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
return true;
default:
RT_ASSERT(false,
"rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
break;
}
}
ary_idx++;
} while (1);
return true;
}
EXPORT_SYMBOL(rtl_hal_pwrseqcmdparsing);
bool rtl_ps_enable_nic(struct ieee80211_hw *hw) bool rtl_ps_enable_nic(struct ieee80211_hw *hw)
{ {
struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_priv *rtlpriv = rtl_priv(hw);
......
...@@ -32,6 +32,66 @@ ...@@ -32,6 +32,66 @@
#define MAX_SW_LPS_SLEEP_INTV 5 #define MAX_SW_LPS_SLEEP_INTV 5
/*---------------------------------------------
* 3 The value of cmd: 4 bits
*---------------------------------------------
*/
#define PWR_CMD_READ 0x00
#define PWR_CMD_WRITE 0x01
#define PWR_CMD_POLLING 0x02
#define PWR_CMD_DELAY 0x03
#define PWR_CMD_END 0x04
/* define the base address of each block */
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
enum pwrseq_delay_unit {
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
};
struct wlan_pwr_cfg {
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
};
#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[]);
bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
enum rf_pwrstate state_toset, u32 changesource); enum rf_pwrstate state_toset, u32 changesource);
bool rtl_ps_enable_nic(struct ieee80211_hw *hw); bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
......
...@@ -5,7 +5,6 @@ rtl8188ee-objs := \ ...@@ -5,7 +5,6 @@ rtl8188ee-objs := \
led.o \ led.o \
phy.o \ phy.o \
pwrseq.o \ pwrseq.o \
pwrseqcmd.o \
rf.o \ rf.o \
sw.o \ sw.o \
table.o \ table.o \
......
...@@ -41,7 +41,6 @@ ...@@ -41,7 +41,6 @@
#include "fw.h" #include "fw.h"
#include "led.h" #include "led.h"
#include "hw.h" #include "hw.h"
#include "pwrseqcmd.h"
#include "pwrseq.h" #include "pwrseq.h"
#define LLT_CONFIG 5 #define LLT_CONFIG 5
...@@ -815,11 +814,11 @@ static bool _rtl88ee_init_mac(struct ieee80211_hw *hw) ...@@ -815,11 +814,11 @@ static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
/* HW Power on sequence */ /* HW Power on sequence */
if (!rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
Rtl8188E_NIC_ENABLE_FLOW)) { Rtl8188E_NIC_ENABLE_FLOW)) {
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"init MAC Fail as rtl88_hal_pwrseqcmdparsing\n"); "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
return false; return false;
} }
...@@ -1346,7 +1345,7 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw) ...@@ -1346,7 +1345,7 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
} }
rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF); rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
PWR_INTF_PCI_MSK, PWR_INTF_PCI_MSK,
Rtl8188E_NIC_LPS_ENTER_FLOW); Rtl8188E_NIC_LPS_ENTER_FLOW);
...@@ -1362,7 +1361,7 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw) ...@@ -1362,7 +1361,7 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL); u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0)))); rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
PWR_INTF_PCI_MSK, Rtl8188E_NIC_DISABLE_FLOW); PWR_INTF_PCI_MSK, Rtl8188E_NIC_DISABLE_FLOW);
u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
......
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include "../wifi.h" #include "../wifi.h"
#include "../pci.h" #include "../pci.h"
#include "../core.h"
#include "../ps.h" #include "../ps.h"
#include "reg.h" #include "reg.h"
#include "def.h" #include "def.h"
...@@ -151,18 +152,7 @@ static bool config_bb_with_pgheader(struct ieee80211_hw *hw, ...@@ -151,18 +152,7 @@ static bool config_bb_with_pgheader(struct ieee80211_hw *hw,
v2 = table_pg[i + 1]; v2 = table_pg[i + 1];
if (v1 < 0xcdcdcdcd) { if (v1 < 0xcdcdcdcd) {
if (table_pg[i] == 0xfe) rtl_addr_delay(table_pg[i]);
mdelay(50);
else if (table_pg[i] == 0xfd)
mdelay(5);
else if (table_pg[i] == 0xfc)
mdelay(1);
else if (table_pg[i] == 0xfb)
udelay(50);
else if (table_pg[i] == 0xfa)
udelay(5);
else if (table_pg[i] == 0xf9)
udelay(1);
store_pwrindex_offset(hw, table_pg[i], store_pwrindex_offset(hw, table_pg[i],
table_pg[i + 1], table_pg[i + 1],
...@@ -672,24 +662,9 @@ static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, ...@@ -672,24 +662,9 @@ static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw,
u32 addr, u32 data, enum radio_path rfpath, u32 addr, u32 data, enum radio_path rfpath,
u32 regaddr) u32 regaddr)
{ {
if (addr == 0xffe) { rtl_rfreg_delay(hw, rfpath, regaddr,
mdelay(50);
} else if (addr == 0xfd) {
mdelay(5);
} else if (addr == 0xfc) {
mdelay(1);
} else if (addr == 0xfb) {
udelay(50);
} else if (addr == 0xfa) {
udelay(5);
} else if (addr == 0xf9) {
udelay(1);
} else {
rtl_set_rfreg(hw, rfpath, regaddr,
RFREG_OFFSET_MASK, RFREG_OFFSET_MASK,
data); data);
udelay(1);
}
} }
static void rtl88_config_s(struct ieee80211_hw *hw, static void rtl88_config_s(struct ieee80211_hw *hw,
...@@ -702,28 +677,6 @@ static void rtl88_config_s(struct ieee80211_hw *hw, ...@@ -702,28 +677,6 @@ static void rtl88_config_s(struct ieee80211_hw *hw,
addr | maskforphyset); addr | maskforphyset);
} }
static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw,
u32 addr, u32 data)
{
if (addr == 0xfe) {
mdelay(50);
} else if (addr == 0xfd) {
mdelay(5);
} else if (addr == 0xfc) {
mdelay(1);
} else if (addr == 0xfb) {
udelay(50);
} else if (addr == 0xfa) {
udelay(5);
} else if (addr == 0xf9) {
udelay(1);
} else {
rtl_set_bbreg(hw, addr, MASKDWORD, data);
udelay(1);
}
}
#define NEXT_PAIR(v1, v2, i) \ #define NEXT_PAIR(v1, v2, i) \
do { \ do { \
i += 2; v1 = array_table[i]; \ i += 2; v1 = array_table[i]; \
...@@ -795,7 +748,7 @@ static void set_baseband_phy_config(struct ieee80211_hw *hw) ...@@ -795,7 +748,7 @@ static void set_baseband_phy_config(struct ieee80211_hw *hw)
v1 = array_table[i]; v1 = array_table[i];
v2 = array_table[i + 1]; v2 = array_table[i + 1];
if (v1 < 0xcdcdcdcd) { if (v1 < 0xcdcdcdcd) {
_rtl8188e_config_bb_reg(hw, v1, v2); rtl_bb_delay(hw, v1, v2);
} else {/*This line is the start line of branch.*/ } else {/*This line is the start line of branch.*/
if (!check_cond(hw, array_table[i])) { if (!check_cond(hw, array_table[i])) {
/*Discard the following (offset, data) pairs*/ /*Discard the following (offset, data) pairs*/
...@@ -811,7 +764,7 @@ static void set_baseband_phy_config(struct ieee80211_hw *hw) ...@@ -811,7 +764,7 @@ static void set_baseband_phy_config(struct ieee80211_hw *hw)
while (v2 != 0xDEAD && while (v2 != 0xDEAD &&
v2 != 0xCDEF && v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2) { v2 != 0xCDCD && i < arraylen - 2) {
_rtl8188e_config_bb_reg(hw, v1, v2); rtl_bb_delay(hw, v1, v2);
NEXT_PAIR(v1, v2, i); NEXT_PAIR(v1, v2, i);
} }
......
...@@ -30,7 +30,6 @@ ...@@ -30,7 +30,6 @@
#ifndef __RTL8723E_PWRSEQ_H__ #ifndef __RTL8723E_PWRSEQ_H__
#define __RTL8723E_PWRSEQ_H__ #define __RTL8723E_PWRSEQ_H__
#include "pwrseqcmd.h"
/* /*
Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
There are 6 HW Power States: There are 6 HW Power States:
......
...@@ -2215,22 +2215,6 @@ ...@@ -2215,22 +2215,6 @@
#define BWORD1 0xc #define BWORD1 0xc
#define BWORD 0xf #define BWORD 0xf
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#define MASK4BITS 0x0f
#define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff
#define BENABLE 0x1 #define BENABLE 0x1
#define BDISABLE 0x0 #define BDISABLE 0x0
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include "../wifi.h" #include "../wifi.h"
#include "../pci.h" #include "../pci.h"
#include "../ps.h" #include "../ps.h"
#include "../core.h"
#include "reg.h" #include "reg.h"
#include "def.h" #include "def.h"
#include "hw.h" #include "hw.h"
...@@ -198,18 +199,7 @@ bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, ...@@ -198,18 +199,7 @@ bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
} }
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_reg_arraylen; i = i + 2) { for (i = 0; i < phy_reg_arraylen; i = i + 2) {
if (phy_regarray_table[i] == 0xfe) rtl_addr_delay(phy_regarray_table[i]);
mdelay(50);
else if (phy_regarray_table[i] == 0xfd)
mdelay(5);
else if (phy_regarray_table[i] == 0xfc)
mdelay(1);
else if (phy_regarray_table[i] == 0xfb)
udelay(50);
else if (phy_regarray_table[i] == 0xfa)
udelay(5);
else if (phy_regarray_table[i] == 0xf9)
udelay(1);
rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
phy_regarray_table[i + 1]); phy_regarray_table[i + 1]);
udelay(1); udelay(1);
...@@ -245,18 +235,7 @@ bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, ...@@ -245,18 +235,7 @@ bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_regarray_pg_len; i = i + 3) { for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
if (phy_regarray_table_pg[i] == 0xfe) rtl_addr_delay(phy_regarray_table_pg[i]);
mdelay(50);
else if (phy_regarray_table_pg[i] == 0xfd)
mdelay(5);
else if (phy_regarray_table_pg[i] == 0xfc)
mdelay(1);
else if (phy_regarray_table_pg[i] == 0xfb)
udelay(50);
else if (phy_regarray_table_pg[i] == 0xfa)
udelay(5);
else if (phy_regarray_table_pg[i] == 0xf9)
udelay(1);
_rtl92c_store_pwrIndex_diffrate_offset(hw, _rtl92c_store_pwrIndex_diffrate_offset(hw,
phy_regarray_table_pg[i], phy_regarray_table_pg[i],
...@@ -305,46 +284,16 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, ...@@ -305,46 +284,16 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
switch (rfpath) { switch (rfpath) {
case RF90_PATH_A: case RF90_PATH_A:
for (i = 0; i < radioa_arraylen; i = i + 2) { for (i = 0; i < radioa_arraylen; i = i + 2) {
if (radioa_array_table[i] == 0xfe) rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
mdelay(50);
else if (radioa_array_table[i] == 0xfd)
mdelay(5);
else if (radioa_array_table[i] == 0xfc)
mdelay(1);
else if (radioa_array_table[i] == 0xfb)
udelay(50);
else if (radioa_array_table[i] == 0xfa)
udelay(5);
else if (radioa_array_table[i] == 0xf9)
udelay(1);
else {
rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
RFREG_OFFSET_MASK, RFREG_OFFSET_MASK,
radioa_array_table[i + 1]); radioa_array_table[i + 1]);
udelay(1);
}
} }
break; break;
case RF90_PATH_B: case RF90_PATH_B:
for (i = 0; i < radiob_arraylen; i = i + 2) { for (i = 0; i < radiob_arraylen; i = i + 2) {
if (radiob_array_table[i] == 0xfe) { rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
mdelay(50);
} else if (radiob_array_table[i] == 0xfd)
mdelay(5);
else if (radiob_array_table[i] == 0xfc)
mdelay(1);
else if (radiob_array_table[i] == 0xfb)
udelay(50);
else if (radiob_array_table[i] == 0xfa)
udelay(5);
else if (radiob_array_table[i] == 0xf9)
udelay(1);
else {
rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
RFREG_OFFSET_MASK, RFREG_OFFSET_MASK,
radiob_array_table[i + 1]); radiob_array_table[i + 1]);
udelay(1);
}
} }
break; break;
case RF90_PATH_C: case RF90_PATH_C:
...@@ -355,6 +304,8 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, ...@@ -355,6 +304,8 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n"); "switch case not processed\n");
break; break;
default:
break;
} }
return true; return true;
} }
......
...@@ -2044,22 +2044,6 @@ ...@@ -2044,22 +2044,6 @@
#define BWORD1 0xc #define BWORD1 0xc
#define BWORD 0xf #define BWORD 0xf
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#define MASK4BITS 0x0f
#define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff
#define BENABLE 0x1 #define BENABLE 0x1
#define BDISABLE 0x0 #define BDISABLE 0x0
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include "../wifi.h" #include "../wifi.h"
#include "../pci.h" #include "../pci.h"
#include "../ps.h" #include "../ps.h"
#include "../core.h"
#include "reg.h" #include "reg.h"
#include "def.h" #include "def.h"
#include "phy.h" #include "phy.h"
...@@ -188,18 +189,7 @@ bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, ...@@ -188,18 +189,7 @@ bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
} }
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_reg_arraylen; i = i + 2) { for (i = 0; i < phy_reg_arraylen; i = i + 2) {
if (phy_regarray_table[i] == 0xfe) rtl_addr_delay(phy_regarray_table[i]);
mdelay(50);
else if (phy_regarray_table[i] == 0xfd)
mdelay(5);
else if (phy_regarray_table[i] == 0xfc)
mdelay(1);
else if (phy_regarray_table[i] == 0xfb)
udelay(50);
else if (phy_regarray_table[i] == 0xfa)
udelay(5);
else if (phy_regarray_table[i] == 0xf9)
udelay(1);
rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
phy_regarray_table[i + 1]); phy_regarray_table[i + 1]);
udelay(1); udelay(1);
...@@ -236,18 +226,7 @@ bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, ...@@ -236,18 +226,7 @@ bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata; phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_regarray_pg_len; i = i + 3) { for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
if (phy_regarray_table_pg[i] == 0xfe) rtl_addr_delay(phy_regarray_table_pg[i]);
mdelay(50);
else if (phy_regarray_table_pg[i] == 0xfd)
mdelay(5);
else if (phy_regarray_table_pg[i] == 0xfc)
mdelay(1);
else if (phy_regarray_table_pg[i] == 0xfb)
udelay(50);
else if (phy_regarray_table_pg[i] == 0xfa)
udelay(5);
else if (phy_regarray_table_pg[i] == 0xf9)
udelay(1);
_rtl92c_store_pwrIndex_diffrate_offset(hw, _rtl92c_store_pwrIndex_diffrate_offset(hw,
phy_regarray_table_pg[i], phy_regarray_table_pg[i],
phy_regarray_table_pg[i + 1], phy_regarray_table_pg[i + 1],
...@@ -294,46 +273,16 @@ bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, ...@@ -294,46 +273,16 @@ bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
switch (rfpath) { switch (rfpath) {
case RF90_PATH_A: case RF90_PATH_A:
for (i = 0; i < radioa_arraylen; i = i + 2) { for (i = 0; i < radioa_arraylen; i = i + 2) {
if (radioa_array_table[i] == 0xfe) rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
mdelay(50);
else if (radioa_array_table[i] == 0xfd)
mdelay(5);
else if (radioa_array_table[i] == 0xfc)
mdelay(1);
else if (radioa_array_table[i] == 0xfb)
udelay(50);
else if (radioa_array_table[i] == 0xfa)
udelay(5);
else if (radioa_array_table[i] == 0xf9)
udelay(1);
else {
rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
RFREG_OFFSET_MASK, RFREG_OFFSET_MASK,
radioa_array_table[i + 1]); radioa_array_table[i + 1]);
udelay(1);
}
} }
break; break;
case RF90_PATH_B: case RF90_PATH_B:
for (i = 0; i < radiob_arraylen; i = i + 2) { for (i = 0; i < radiob_arraylen; i = i + 2) {
if (radiob_array_table[i] == 0xfe) { rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
mdelay(50);
} else if (radiob_array_table[i] == 0xfd)
mdelay(5);
else if (radiob_array_table[i] == 0xfc)
mdelay(1);
else if (radiob_array_table[i] == 0xfb)
udelay(50);
else if (radiob_array_table[i] == 0xfa)
udelay(5);
else if (radiob_array_table[i] == 0xf9)
udelay(1);
else {
rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
RFREG_OFFSET_MASK, RFREG_OFFSET_MASK,
radiob_array_table[i + 1]); radiob_array_table[i + 1]);
udelay(1);
}
} }
break; break;
case RF90_PATH_C: case RF90_PATH_C:
...@@ -344,6 +293,8 @@ bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, ...@@ -344,6 +293,8 @@ bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n"); "switch case not processed\n");
break; break;
default:
break;
} }
return true; return true;
} }
......
...@@ -194,15 +194,15 @@ static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) ...@@ -194,15 +194,15 @@ static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */
rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */
ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, BMASKDWORD); ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, BMASKDWORD); ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, BMASKDWORD); ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, BMASKDWORD); ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_rate_illegal +
...@@ -214,9 +214,9 @@ static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) ...@@ -214,9 +214,9 @@ static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
/* hold cck counter */ /* hold cck counter */
rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, BMASKBYTE0); ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
falsealm_cnt->cnt_cck_fail = ret_value; falsealm_cnt->cnt_cck_fail = ret_value;
ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, BMASKBYTE3); ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
rtl92d_release_cckandrw_pagea_ctl(hw, &flag); rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
} else { } else {
...@@ -331,11 +331,11 @@ static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) ...@@ -331,11 +331,11 @@ static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) { if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) {
if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0x83); rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
rtl92d_release_cckandrw_pagea_ctl(hw, &flag); rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
} else { } else {
rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0xcd); rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
rtl92d_release_cckandrw_pagea_ctl(hw, &flag); rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
} }
de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state; de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state;
...@@ -722,7 +722,7 @@ static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) ...@@ -722,7 +722,7 @@ static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw)
RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
"===> Rx Gain %x\n", u4tmp); "===> Rx Gain %x\n", u4tmp);
for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++)
rtl_set_rfreg(hw, i, 0x3C, BRFREGOFFSETMASK, rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK,
(rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp);
} }
...@@ -737,7 +737,7 @@ static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, ...@@ -737,7 +737,7 @@ static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg,
/* Query CCK default setting From 0xa24 */ /* Query CCK default setting From 0xa24 */
rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2,
BMASKDWORD) & BMASKCCK; MASKDWORD) & MASKCCK;
rtl92d_release_cckandrw_pagea_ctl(hw, &flag); rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
for (i = 0; i < CCK_TABLE_LENGTH; i++) { for (i = 0; i < CCK_TABLE_LENGTH; i++) {
if (rtlpriv->dm.cck_inch14) { if (rtlpriv->dm.cck_inch14) {
...@@ -896,9 +896,9 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter( ...@@ -896,9 +896,9 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
rf = 1; rf = 1;
if (thermalvalue) { if (thermalvalue) {
ele_d = rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, ele_d = rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
BMASKDWORD) & BMASKOFDM_D; MASKDWORD) & MASKOFDM_D;
for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
if (ele_d == (ofdmswing_table[i] & BMASKOFDM_D)) { if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
ofdm_index_old[0] = (u8) i; ofdm_index_old[0] = (u8) i;
RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
...@@ -910,10 +910,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter( ...@@ -910,10 +910,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
} }
if (is2t) { if (is2t) {
ele_d = rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, ele_d = rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
BMASKDWORD) & BMASKOFDM_D; MASKDWORD) & MASKOFDM_D;
for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
if (ele_d == if (ele_d ==
(ofdmswing_table[i] & BMASKOFDM_D)) { (ofdmswing_table[i] & MASKOFDM_D)) {
ofdm_index_old[1] = (u8) i; ofdm_index_old[1] = (u8) i;
RT_TRACE(rtlpriv, COMP_POWER_TRACKING, RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
DBG_LOUD, DBG_LOUD,
...@@ -1091,10 +1091,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter( ...@@ -1091,10 +1091,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
value32 = (ele_d << 22) | ((ele_c & 0x3F) << value32 = (ele_d << 22) | ((ele_c & 0x3F) <<
16) | ele_a; 16) | ele_a;
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
BMASKDWORD, value32); MASKDWORD, value32);
value32 = (ele_c & 0x000003C0) >> 6; value32 = (ele_c & 0x000003C0) >> 6;
rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS, rtl_set_bbreg(hw, ROFDM0_XCTxAFE, MASKH4BITS,
value32); value32);
value32 = ((val_x * ele_d) >> 7) & 0x01; value32 = ((val_x * ele_d) >> 7) & 0x01;
...@@ -1103,10 +1103,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter( ...@@ -1103,10 +1103,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
} else { } else {
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
BMASKDWORD, MASKDWORD,
ofdmswing_table ofdmswing_table
[(u8)ofdm_index[0]]); [(u8)ofdm_index[0]]);
rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS, rtl_set_bbreg(hw, ROFDM0_XCTxAFE, MASKH4BITS,
0x00); 0x00);
rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
BIT(24), 0x00); BIT(24), 0x00);
...@@ -1204,21 +1204,21 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter( ...@@ -1204,21 +1204,21 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
ele_a; ele_a;
rtl_set_bbreg(hw, rtl_set_bbreg(hw,
ROFDM0_XBTxIQIMBALANCE, ROFDM0_XBTxIQIMBALANCE,
BMASKDWORD, value32); MASKDWORD, value32);
value32 = (ele_c & 0x000003C0) >> 6; value32 = (ele_c & 0x000003C0) >> 6;
rtl_set_bbreg(hw, ROFDM0_XDTxAFE, rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
BMASKH4BITS, value32); MASKH4BITS, value32);
value32 = ((val_x * ele_d) >> 7) & 0x01; value32 = ((val_x * ele_d) >> 7) & 0x01;
rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
BIT(28), value32); BIT(28), value32);
} else { } else {
rtl_set_bbreg(hw, rtl_set_bbreg(hw,
ROFDM0_XBTxIQIMBALANCE, ROFDM0_XBTxIQIMBALANCE,
BMASKDWORD, MASKDWORD,
ofdmswing_table ofdmswing_table
[(u8) ofdm_index[1]]); [(u8) ofdm_index[1]]);
rtl_set_bbreg(hw, ROFDM0_XDTxAFE, rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
BMASKH4BITS, 0x00); MASKH4BITS, 0x00);
rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
BIT(28), 0x00); BIT(28), 0x00);
} }
...@@ -1229,10 +1229,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter( ...@@ -1229,10 +1229,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
} }
RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
"TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n",
rtl_get_bbreg(hw, 0xc80, BMASKDWORD), rtl_get_bbreg(hw, 0xc80, MASKDWORD),
rtl_get_bbreg(hw, 0xc94, BMASKDWORD), rtl_get_bbreg(hw, 0xc94, MASKDWORD),
rtl_get_rfreg(hw, RF90_PATH_A, 0x24, rtl_get_rfreg(hw, RF90_PATH_A, 0x24,
BRFREGOFFSETMASK)); RFREG_OFFSET_MASK));
} }
if ((delta_iqk > rtlefuse->delta_iqk) && if ((delta_iqk > rtlefuse->delta_iqk) &&
(rtlefuse->delta_iqk != 0)) { (rtlefuse->delta_iqk != 0)) {
......
...@@ -985,9 +985,9 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) ...@@ -985,9 +985,9 @@ int rtl92de_hw_init(struct ieee80211_hw *hw)
/* set default value after initialize RF, */ /* set default value after initialize RF, */
rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
RF_CHNLBW, BRFREGOFFSETMASK); RF_CHNLBW, RFREG_OFFSET_MASK);
rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
RF_CHNLBW, BRFREGOFFSETMASK); RF_CHNLBW, RFREG_OFFSET_MASK);
/*---- Set CCK and OFDM Block "ON"----*/ /*---- Set CCK and OFDM Block "ON"----*/
if (rtlhal->current_bandtype == BAND_ON_2_4G) if (rtlhal->current_bandtype == BAND_ON_2_4G)
...@@ -1035,7 +1035,7 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) ...@@ -1035,7 +1035,7 @@ int rtl92de_hw_init(struct ieee80211_hw *hw)
tmp_rega = rtl_get_rfreg(hw, tmp_rega = rtl_get_rfreg(hw,
(enum radio_path)RF90_PATH_A, (enum radio_path)RF90_PATH_A,
0x2a, BMASKDWORD); 0x2a, MASKDWORD);
if (((tmp_rega & BIT(11)) == BIT(11))) if (((tmp_rega & BIT(11)) == BIT(11)))
break; break;
...@@ -1334,13 +1334,13 @@ void rtl92de_card_disable(struct ieee80211_hw *hw) ...@@ -1334,13 +1334,13 @@ void rtl92de_card_disable(struct ieee80211_hw *hw)
/* c. ========RF OFF sequence========== */ /* c. ========RF OFF sequence========== */
/* 0x88c[23:20] = 0xf. */ /* 0x88c[23:20] = 0xf. */
rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00); rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
/* APSD_CTRL 0x600[7:0] = 0x40 */ /* APSD_CTRL 0x600[7:0] = 0x40 */
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
/* Close antenna 0,0xc04,0xd04 */ /* Close antenna 0,0xc04,0xd04 */
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0); rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0); rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
/* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */ /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
......
...@@ -1295,18 +1295,4 @@ ...@@ -1295,18 +1295,4 @@
#define BWORD1 0xc #define BWORD1 0xc
#define BDWORD 0xf #define BDWORD 0xf
#define BMASKBYTE0 0xff
#define BMASKBYTE1 0xff00
#define BMASKBYTE2 0xff0000
#define BMASKBYTE3 0xff000000
#define BMASKHWORD 0xffff0000
#define BMASKLWORD 0x0000ffff
#define BMASKDWORD 0xffffffff
#define BMASK12BITS 0xfff
#define BMASKH4BITS 0xf0000000
#define BMASKOFDM_D 0xffc00000
#define BMASKCCK 0x3f3f3f3f
#define BRFREGOFFSETMASK 0xfffff
#endif #endif
...@@ -125,7 +125,7 @@ void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, ...@@ -125,7 +125,7 @@ void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
} }
tmpval = tx_agc[RF90_PATH_A] & 0xff; tmpval = tx_agc[RF90_PATH_A] & 0xff;
rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, BMASKBYTE1, tmpval); rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR, RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
tmpval, RTXAGC_A_CCK1_MCS32); tmpval, RTXAGC_A_CCK1_MCS32);
...@@ -135,7 +135,7 @@ void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, ...@@ -135,7 +135,7 @@ void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
"CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
tmpval, RTXAGC_B_CCK11_A_CCK2_11); tmpval, RTXAGC_B_CCK11_A_CCK2_11);
tmpval = tx_agc[RF90_PATH_B] >> 24; tmpval = tx_agc[RF90_PATH_B] >> 24;
rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, BMASKBYTE0, tmpval); rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR, RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
tmpval, RTXAGC_B_CCK11_A_CCK2_11); tmpval, RTXAGC_B_CCK11_A_CCK2_11);
...@@ -360,7 +360,7 @@ static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw, ...@@ -360,7 +360,7 @@ static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw,
regoffset = regoffset_a[index]; regoffset = regoffset_a[index];
else else
regoffset = regoffset_b[index]; regoffset = regoffset_b[index];
rtl_set_bbreg(hw, regoffset, BMASKDWORD, writeval); rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR, RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Set 0x%x = %08x\n", regoffset, writeval); "Set 0x%x = %08x\n", regoffset, writeval);
if (((get_rf_type(rtlphy) == RF_2T2R) && if (((get_rf_type(rtlphy) == RF_2T2R) &&
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include "../wifi.h" #include "../wifi.h"
#include "../pci.h" #include "../pci.h"
#include "../ps.h" #include "../ps.h"
#include "../core.h"
#include "reg.h" #include "reg.h"
#include "def.h" #include "def.h"
#include "phy.h" #include "phy.h"
...@@ -833,18 +834,7 @@ static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) ...@@ -833,18 +834,7 @@ static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_reg_len; i = i + 2) { for (i = 0; i < phy_reg_len; i = i + 2) {
if (phy_reg_table[i] == 0xfe) rtl_addr_delay(phy_reg_table[i]);
mdelay(50);
else if (phy_reg_table[i] == 0xfd)
mdelay(5);
else if (phy_reg_table[i] == 0xfc)
mdelay(1);
else if (phy_reg_table[i] == 0xfb)
udelay(50);
else if (phy_reg_table[i] == 0xfa)
udelay(5);
else if (phy_reg_table[i] == 0xf9)
udelay(1);
/* Add delay for ECS T20 & LG malow platform, */ /* Add delay for ECS T20 & LG malow platform, */
udelay(1); udelay(1);
...@@ -886,18 +876,7 @@ static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw, ...@@ -886,18 +876,7 @@ static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) { for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
if (phy_regarray2xtxr_table[i] == 0xfe) rtl_addr_delay(phy_regarray2xtxr_table[i]);
mdelay(50);
else if (phy_regarray2xtxr_table[i] == 0xfd)
mdelay(5);
else if (phy_regarray2xtxr_table[i] == 0xfc)
mdelay(1);
else if (phy_regarray2xtxr_table[i] == 0xfb)
udelay(50);
else if (phy_regarray2xtxr_table[i] == 0xfa)
udelay(5);
else if (phy_regarray2xtxr_table[i] == 0xf9)
udelay(1);
rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i], rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
phy_regarray2xtxr_table[i + 1], phy_regarray2xtxr_table[i + 1],
...@@ -920,18 +899,7 @@ static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw, ...@@ -920,18 +899,7 @@ static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_pg_len; i = i + 3) { for (i = 0; i < phy_pg_len; i = i + 3) {
if (phy_table_pg[i] == 0xfe) rtl_addr_delay(phy_table_pg[i]);
mdelay(50);
else if (phy_table_pg[i] == 0xfd)
mdelay(5);
else if (phy_table_pg[i] == 0xfc)
mdelay(1);
else if (phy_table_pg[i] == 0xfb)
udelay(50);
else if (phy_table_pg[i] == 0xfa)
udelay(5);
else if (phy_table_pg[i] == 0xf9)
udelay(1);
_rtl92s_store_pwrindex_diffrate_offset(hw, _rtl92s_store_pwrindex_diffrate_offset(hw,
phy_table_pg[i], phy_table_pg[i],
...@@ -1034,28 +1002,9 @@ u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) ...@@ -1034,28 +1002,9 @@ u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
switch (rfpath) { switch (rfpath) {
case RF90_PATH_A: case RF90_PATH_A:
for (i = 0; i < radio_a_tblen; i = i + 2) { for (i = 0; i < radio_a_tblen; i = i + 2) {
if (radio_a_table[i] == 0xfe) rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
/* Delay specific ms. Only RF configuration MASK20BITS, radio_a_table[i + 1]);
* requires delay. */
mdelay(50);
else if (radio_a_table[i] == 0xfd)
mdelay(5);
else if (radio_a_table[i] == 0xfc)
mdelay(1);
else if (radio_a_table[i] == 0xfb)
udelay(50);
else if (radio_a_table[i] == 0xfa)
udelay(5);
else if (radio_a_table[i] == 0xf9)
udelay(1);
else
rtl92s_phy_set_rf_reg(hw, rfpath,
radio_a_table[i],
MASK20BITS,
radio_a_table[i + 1]);
/* Add delay for ECS T20 & LG malow platform */
udelay(1);
} }
/* PA Bias current for inferiority IC */ /* PA Bias current for inferiority IC */
...@@ -1063,28 +1012,8 @@ u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) ...@@ -1063,28 +1012,8 @@ u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
break; break;
case RF90_PATH_B: case RF90_PATH_B:
for (i = 0; i < radio_b_tblen; i = i + 2) { for (i = 0; i < radio_b_tblen; i = i + 2) {
if (radio_b_table[i] == 0xfe) rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
/* Delay specific ms. Only RF configuration MASK20BITS, radio_b_table[i + 1]);
* requires delay.*/
mdelay(50);
else if (radio_b_table[i] == 0xfd)
mdelay(5);
else if (radio_b_table[i] == 0xfc)
mdelay(1);
else if (radio_b_table[i] == 0xfb)
udelay(50);
else if (radio_b_table[i] == 0xfa)
udelay(5);
else if (radio_b_table[i] == 0xf9)
udelay(1);
else
rtl92s_phy_set_rf_reg(hw, rfpath,
radio_b_table[i],
MASK20BITS,
radio_b_table[i + 1]);
/* Add delay for ECS T20 & LG malow platform */
udelay(1);
} }
break; break;
case RF90_PATH_C: case RF90_PATH_C:
......
...@@ -1165,16 +1165,4 @@ ...@@ -1165,16 +1165,4 @@
#define BTX_AGCRATECCK 0x7f00 #define BTX_AGCRATECCK 0x7f00
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MAKS12BITS 0xfffff
#define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff
#endif #endif
...@@ -10,7 +10,6 @@ rtl8723ae-objs := \ ...@@ -10,7 +10,6 @@ rtl8723ae-objs := \
led.o \ led.o \
phy.o \ phy.o \
pwrseq.o \ pwrseq.o \
pwrseqcmd.o \
rf.o \ rf.o \
sw.o \ sw.o \
table.o \ table.o \
......
...@@ -43,7 +43,6 @@ ...@@ -43,7 +43,6 @@
#include "../rtl8723com/fw_common.h" #include "../rtl8723com/fw_common.h"
#include "led.h" #include "led.h"
#include "hw.h" #include "hw.h"
#include "pwrseqcmd.h"
#include "pwrseq.h" #include "pwrseq.h"
#include "btc.h" #include "btc.h"
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include "../wifi.h" #include "../wifi.h"
#include "../pci.h" #include "../pci.h"
#include "../ps.h" #include "../ps.h"
#include "../core.h"
#include "reg.h" #include "reg.h"
#include "def.h" #include "def.h"
#include "phy.h" #include "phy.h"
...@@ -277,18 +278,7 @@ static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype) ...@@ -277,18 +278,7 @@ static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
phy_regarray_table = RTL8723EPHY_REG_1TARRAY; phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_reg_arraylen; i = i + 2) { for (i = 0; i < phy_reg_arraylen; i = i + 2) {
if (phy_regarray_table[i] == 0xfe) rtl_addr_delay(phy_regarray_table[i]);
mdelay(50);
else if (phy_regarray_table[i] == 0xfd)
mdelay(5);
else if (phy_regarray_table[i] == 0xfc)
mdelay(1);
else if (phy_regarray_table[i] == 0xfb)
udelay(50);
else if (phy_regarray_table[i] == 0xfa)
udelay(5);
else if (phy_regarray_table[i] == 0xf9)
udelay(1);
rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
phy_regarray_table[i + 1]); phy_regarray_table[i + 1]);
udelay(1); udelay(1);
...@@ -450,18 +440,7 @@ static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype) ...@@ -450,18 +440,7 @@ static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype)
if (configtype == BASEBAND_CONFIG_PHY_REG) { if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_regarray_pg_len; i = i + 3) { for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
if (phy_regarray_table_pg[i] == 0xfe) rtl_addr_delay(phy_regarray_table_pg[i]);
mdelay(50);
else if (phy_regarray_table_pg[i] == 0xfd)
mdelay(5);
else if (phy_regarray_table_pg[i] == 0xfc)
mdelay(1);
else if (phy_regarray_table_pg[i] == 0xfb)
udelay(50);
else if (phy_regarray_table_pg[i] == 0xfa)
udelay(5);
else if (phy_regarray_table_pg[i] == 0xf9)
udelay(1);
_st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i], _st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i],
phy_regarray_table_pg[i + 1], phy_regarray_table_pg[i + 1],
...@@ -488,24 +467,9 @@ bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, ...@@ -488,24 +467,9 @@ bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
switch (rfpath) { switch (rfpath) {
case RF90_PATH_A: case RF90_PATH_A:
for (i = 0; i < radioa_arraylen; i = i + 2) { for (i = 0; i < radioa_arraylen; i = i + 2) {
if (radioa_array_table[i] == 0xfe) rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
mdelay(50);
else if (radioa_array_table[i] == 0xfd)
mdelay(5);
else if (radioa_array_table[i] == 0xfc)
mdelay(1);
else if (radioa_array_table[i] == 0xfb)
udelay(50);
else if (radioa_array_table[i] == 0xfa)
udelay(5);
else if (radioa_array_table[i] == 0xf9)
udelay(1);
else {
rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
RFREG_OFFSET_MASK, RFREG_OFFSET_MASK,
radioa_array_table[i + 1]); radioa_array_table[i + 1]);
udelay(1);
}
} }
break; break;
case RF90_PATH_B: case RF90_PATH_B:
......
...@@ -30,7 +30,6 @@ ...@@ -30,7 +30,6 @@
#ifndef __RTL8723E_PWRSEQ_H__ #ifndef __RTL8723E_PWRSEQ_H__
#define __RTL8723E_PWRSEQ_H__ #define __RTL8723E_PWRSEQ_H__
#include "pwrseqcmd.h"
/* /*
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
There are 6 HW Power States: There are 6 HW Power States:
......
...@@ -2059,22 +2059,6 @@ ...@@ -2059,22 +2059,6 @@
#define BWORD1 0xc #define BWORD1 0xc
#define BWORD 0xf #define BWORD 0xf
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#define MASK4BITS 0x0f
#define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff
#define BENABLE 0x1 #define BENABLE 0x1
#define BDISABLE 0x0 #define BDISABLE 0x0
......
...@@ -8,7 +8,6 @@ rtl8723be-objs := \ ...@@ -8,7 +8,6 @@ rtl8723be-objs := \
led.o \ led.o \
phy.o \ phy.o \
pwrseq.o \ pwrseq.o \
pwrseqcmd.o \
rf.o \ rf.o \
sw.o \ sw.o \
table.o \ table.o \
......
...@@ -39,7 +39,6 @@ ...@@ -39,7 +39,6 @@
#include "../rtl8723com/fw_common.h" #include "../rtl8723com/fw_common.h"
#include "led.h" #include "led.h"
#include "hw.h" #include "hw.h"
#include "pwrseqcmd.h"
#include "pwrseq.h" #include "pwrseq.h"
#include "../btcoexist/rtl_btc.h" #include "../btcoexist/rtl_btc.h"
...@@ -818,7 +817,7 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw) ...@@ -818,7 +817,7 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
mac_func_enable = false; mac_func_enable = false;
/* HW Power on sequence */ /* HW Power on sequence */
if (!rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
RTL8723_NIC_ENABLE_FLOW)) { RTL8723_NIC_ENABLE_FLOW)) {
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
...@@ -1309,7 +1308,7 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw) ...@@ -1309,7 +1308,7 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
/* Combo (PCIe + USB) Card and PCIe-MF Card */ /* Combo (PCIe + USB) Card and PCIe-MF Card */
/* 1. Run LPS WL RFOFF flow */ /* 1. Run LPS WL RFOFF flow */
rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW); PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
/* 2. 0x1F[7:0] = 0 */ /* 2. 0x1F[7:0] = 0 */
...@@ -1328,7 +1327,7 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw) ...@@ -1328,7 +1327,7 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
/* HW card disable configuration. */ /* HW card disable configuration. */
rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW); PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
/* Reset MCU IO Wrapper */ /* Reset MCU IO Wrapper */
......
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include "../wifi.h" #include "../wifi.h"
#include "../pci.h" #include "../pci.h"
#include "../ps.h" #include "../ps.h"
#include "../core.h"
#include "reg.h" #include "reg.h"
#include "def.h" #include "def.h"
#include "phy.h" #include "phy.h"
...@@ -41,9 +42,6 @@ static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, ...@@ -41,9 +42,6 @@ static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw, static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
u8 channel, u8 *stage, u8 channel, u8 *stage,
u8 *step, u32 *delay); u8 *step, u32 *delay);
static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw,
u32 addr, u32 data);
static bool _rtl8723be_check_condition(struct ieee80211_hw *hw, static bool _rtl8723be_check_condition(struct ieee80211_hw *hw,
const u32 condition) const u32 condition)
{ {
...@@ -114,7 +112,7 @@ static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, ...@@ -114,7 +112,7 @@ static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
v1 = array_table[i]; v1 = array_table[i];
v2 = array_table[i+1]; v2 = array_table[i+1];
if (v1 < 0xcdcdcdcd) { if (v1 < 0xcdcdcdcd) {
_rtl8723be_config_bb_reg(hw, v1, v2); rtl_bb_delay(hw, v1, v2);
} else {/*This line is the start line of branch.*/ } else {/*This line is the start line of branch.*/
if (!_rtl8723be_check_condition(hw, array_table[i])) { if (!_rtl8723be_check_condition(hw, array_table[i])) {
/*Discard the following (offset, data) pairs*/ /*Discard the following (offset, data) pairs*/
...@@ -135,7 +133,7 @@ static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, ...@@ -135,7 +133,7 @@ static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
v2 != 0xCDEF && v2 != 0xCDEF &&
v2 != 0xCDCD && v2 != 0xCDCD &&
i < arraylen - 2) { i < arraylen - 2) {
_rtl8723be_config_bb_reg(hw, rtl_bb_delay(hw,
v1, v2); v1, v2);
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
} }
...@@ -389,27 +387,6 @@ static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) ...@@ -389,27 +387,6 @@ static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
[path][txnum][section] = 0; [path][txnum][section] = 0;
} }
static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw,
u32 addr, u32 data)
{
if (addr == 0xfe) {
mdelay(50);
} else if (addr == 0xfd) {
mdelay(5);
} else if (addr == 0xfc) {
mdelay(1);
} else if (addr == 0xfb) {
udelay(50);
} else if (addr == 0xfa) {
udelay(5);
} else if (addr == 0xf9) {
udelay(1);
} else {
rtl_set_bbreg(hw, addr, MASKDWORD, data);
udelay(1);
}
}
static void phy_set_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band, static void phy_set_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band,
u8 path, u8 rate_section, u8 path, u8 rate_section,
u8 txnum, u8 value) u8 txnum, u8 value)
......
...@@ -26,7 +26,6 @@ ...@@ -26,7 +26,6 @@
#ifndef __RTL8723BE_PWRSEQ_H__ #ifndef __RTL8723BE_PWRSEQ_H__
#define __RTL8723BE_PWRSEQ_H__ #define __RTL8723BE_PWRSEQ_H__
#include "pwrseqcmd.h"
/* Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd /* Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
* There are 6 HW Power States: * There are 6 HW Power States:
* 0: POFF--Power Off * 0: POFF--Power Off
......
...@@ -2242,22 +2242,6 @@ ...@@ -2242,22 +2242,6 @@
#define BWORD1 0xc #define BWORD1 0xc
#define BWORD 0xf #define BWORD 0xf
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#define MASK4BITS 0x0f
#define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff
#define BENABLE 0x1 #define BENABLE 0x1
#define BDISABLE 0x0 #define BDISABLE 0x0
......
...@@ -57,6 +57,22 @@ ...@@ -57,6 +57,22 @@
#define MASK20BITS 0xfffff #define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff #define RFREG_OFFSET_MASK 0xfffff
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#define MASK4BITS 0x0f
#define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff
#define RF_CHANGE_BY_INIT 0 #define RF_CHANGE_BY_INIT 0
#define RF_CHANGE_BY_IPS BIT(28) #define RF_CHANGE_BY_IPS BIT(28)
#define RF_CHANGE_BY_PS BIT(29) #define RF_CHANGE_BY_PS BIT(29)
......
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