Commit 25c56eec authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville

ath9k: remove ath9k_ht_macmode

This is used just to determine how to program the MAC,
either for 20 MHz operation of 40 MHz so just use conf_is_ht40()
Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 6420014c
...@@ -592,7 +592,6 @@ struct ath_softc { ...@@ -592,7 +592,6 @@ struct ath_softc {
bool ps_enabled; bool ps_enabled;
unsigned long ps_usecount; unsigned long ps_usecount;
enum ath9k_int imask; enum ath9k_int imask;
enum ath9k_ht_macmode tx_chan_width;
struct ath_config config; struct ath_config config;
struct ath_rx rx; struct ath_rx rx;
......
...@@ -26,8 +26,7 @@ ...@@ -26,8 +26,7 @@
#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
enum ath9k_ht_macmode macmode);
static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
struct ar5416_eeprom_def *pEepData, struct ar5416_eeprom_def *pEepData,
u32 reg, u32 value); u32 reg, u32 value);
...@@ -1352,8 +1351,7 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, ...@@ -1352,8 +1351,7 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
} }
static int ath9k_hw_process_ini(struct ath_hw *ah, static int ath9k_hw_process_ini(struct ath_hw *ah,
struct ath9k_channel *chan, struct ath9k_channel *chan)
enum ath9k_ht_macmode macmode)
{ {
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
int i, regWrites = 0; int i, regWrites = 0;
...@@ -1455,7 +1453,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1455,7 +1453,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
} }
ath9k_hw_override_ini(ah, chan); ath9k_hw_override_ini(ah, chan);
ath9k_hw_set_regs(ah, chan, macmode); ath9k_hw_set_regs(ah, chan);
ath9k_hw_init_chain_masks(ah); ath9k_hw_init_chain_masks(ah);
if (OLC_FOR_AR9280_20_LATER) if (OLC_FOR_AR9280_20_LATER)
...@@ -1738,8 +1736,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) ...@@ -1738,8 +1736,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
} }
} }
static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
enum ath9k_ht_macmode macmode)
{ {
u32 phymode; u32 phymode;
u32 enableDacFifo = 0; u32 enableDacFifo = 0;
...@@ -1761,7 +1758,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -1761,7 +1758,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
} }
REG_WRITE(ah, AR_PHY_TURBO, phymode); REG_WRITE(ah, AR_PHY_TURBO, phymode);
ath9k_hw_set11nmac2040(ah, macmode); ath9k_hw_set11nmac2040(ah);
REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
...@@ -1787,8 +1784,7 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah, ...@@ -1787,8 +1784,7 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
} }
static bool ath9k_hw_channel_change(struct ath_hw *ah, static bool ath9k_hw_channel_change(struct ath_hw *ah,
struct ath9k_channel *chan, struct ath9k_channel *chan)
enum ath9k_ht_macmode macmode)
{ {
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
...@@ -1812,7 +1808,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah, ...@@ -1812,7 +1808,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
return false; return false;
} }
ath9k_hw_set_regs(ah, chan, macmode); ath9k_hw_set_regs(ah, chan);
if (AR_SREV_9280_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) {
ath9k_hw_ar9280_set_channel(ah, chan); ath9k_hw_ar9280_set_channel(ah, chan);
...@@ -2323,7 +2319,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -2323,7 +2319,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
{ {
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
u32 saveLedState; u32 saveLedState;
struct ath_softc *sc = ah->ah_sc;
struct ath9k_channel *curchan = ah->curchan; struct ath9k_channel *curchan = ah->curchan;
u32 saveDefAntenna; u32 saveDefAntenna;
u32 macStaId1; u32 macStaId1;
...@@ -2348,7 +2343,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -2348,7 +2343,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
!(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { if (ath9k_hw_channel_change(ah, chan)) {
ath9k_hw_loadnf(ah, ah->curchan); ath9k_hw_loadnf(ah, ah->curchan);
ath9k_hw_start_nfcal(ah); ath9k_hw_start_nfcal(ah);
return 0; return 0;
...@@ -2408,7 +2403,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -2408,7 +2403,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
} }
r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width); r = ath9k_hw_process_ini(ah, chan);
if (r) if (r)
return r; return r;
...@@ -4063,12 +4058,12 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) ...@@ -4063,12 +4058,12 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
} }
} }
void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) void ath9k_hw_set11nmac2040(struct ath_hw *ah)
{ {
struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
u32 macmode; u32 macmode;
if (mode == ATH9K_HT_MACMODE_2040 && if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
!ah->config.cwm_ignore_extcca)
macmode = AR_2040_JOINED_RX_CLEAR; macmode = AR_2040_JOINED_RX_CLEAR;
else else
macmode = 0; macmode = 0;
......
...@@ -662,7 +662,7 @@ void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); ...@@ -662,7 +662,7 @@ void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
void ath9k_hw_reset_tsf(struct ath_hw *ah); void ath9k_hw_reset_tsf(struct ath_hw *ah);
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); void ath9k_hw_set11nmac2040(struct ath_hw *ah);
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
const struct ath9k_beacon_state *bs); const struct ath9k_beacon_state *bs);
......
...@@ -614,11 +614,6 @@ enum ath9k_cipher { ...@@ -614,11 +614,6 @@ enum ath9k_cipher {
ATH9K_CIPHER_MIC = 127 ATH9K_CIPHER_MIC = 127
}; };
enum ath9k_ht_macmode {
ATH9K_HT_MACMODE_20 = 0,
ATH9K_HT_MACMODE_2040 = 1,
};
struct ath_hw; struct ath_hw;
struct ath9k_channel; struct ath9k_channel;
struct ath_rate_table; struct ath_rate_table;
......
...@@ -299,6 +299,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, ...@@ -299,6 +299,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
struct ieee80211_conf *conf = &common->hw->conf;
bool fastcc = true, stopped; bool fastcc = true, stopped;
struct ieee80211_channel *channel = hw->conf.channel; struct ieee80211_channel *channel = hw->conf.channel;
int r; int r;
...@@ -329,9 +330,9 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, ...@@ -329,9 +330,9 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
fastcc = false; fastcc = false;
ath_print(common, ATH_DBG_CONFIG, ath_print(common, ATH_DBG_CONFIG,
"(%u MHz) -> (%u MHz), chanwidth: %d\n", "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
sc->sc_ah->curchan->channel, sc->sc_ah->curchan->channel,
channel->center_freq, sc->tx_chan_width); channel->center_freq, conf_is_ht40(conf));
spin_lock_bh(&sc->sc_resetlock); spin_lock_bh(&sc->sc_resetlock);
...@@ -2191,15 +2192,9 @@ void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, ...@@ -2191,15 +2192,9 @@ void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
} }
sc->tx_chan_width = ATH9K_HT_MACMODE_20; if (conf_is_ht(conf))
if (conf_is_ht(conf)) {
if (conf_is_ht40(conf))
sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
ichan->chanmode = ath_get_extchanmode(sc, chan, ichan->chanmode = ath_get_extchanmode(sc, chan,
conf->channel_type); conf->channel_type);
}
} }
/**********************/ /**********************/
......
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