tools arch x86: Sync the msr-index.h copy with the kernel sources

To pick up the changes in:

  7e5b3c26 ("x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation")

Addressing these tools/perf build warnings:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'
  diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

With this one will be able to use these new AMD MSRs in filters, by
name, e.g.:

  # perf trace -e msr:* --filter "msr==IA32_MCU_OPT_CTRL"
  ^C#

Using -v we can see how it sets up the tracepoint filters, converting
from the string in the filter to the numeric value:

  # perf trace -v -e msr:* --filter "msr==IA32_MCU_OPT_CTRL"
  Using CPUID GenuineIntel-6-8E-A
  0x123
  New filter for msr:read_msr: (msr==0x123) && (common_pid != 335 && common_pid != 30344)
  0x123
  New filter for msr:write_msr: (msr==0x123) && (common_pid != 335 && common_pid != 30344)
  0x123
  New filter for msr:rdpmc: (msr==0x123) && (common_pid != 335 && common_pid != 30344)
  mmap size 528384B
  ^C#

The updating process shows how this affects tooling in more detail:

  $ diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
  --- tools/arch/x86/include/asm/msr-index.h	2020-06-03 10:36:09.959910238 -0300
  +++ arch/x86/include/asm/msr-index.h	2020-06-17 10:04:20.235052901 -0300
  @@ -128,6 +128,10 @@
   #define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */
   #define TSX_CTRL_CPUID_CLEAR		BIT(1)	/* Disable TSX enumeration */

  +/* SRBDS support */
  +#define MSR_IA32_MCU_OPT_CTRL		0x00000123
  +#define RNGDS_MITG_DIS			BIT(0)
  +
   #define MSR_IA32_SYSENTER_CS		0x00000174
   #define MSR_IA32_SYSENTER_ESP		0x00000175
   #define MSR_IA32_SYSENTER_EIP		0x00000176
  $ set -o vi
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
  $ diff -u before after
  --- before	2020-06-17 10:05:49.653114752 -0300
  +++ after	2020-06-17 10:06:01.777258731 -0300
  @@ -51,6 +51,7 @@
   	[0x0000011e] = "IA32_BBL_CR_CTL3",
   	[0x00000120] = "IDT_MCR_CTRL",
   	[0x00000122] = "IA32_TSX_CTRL",
  +	[0x00000123] = "IA32_MCU_OPT_CTRL",
   	[0x00000140] = "MISC_FEATURES_ENABLES",
   	[0x00000174] = "IA32_SYSENTER_CS",
   	[0x00000175] = "IA32_SYSENTER_ESP",
  $

The related change to cpu-features.h affects this:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

This shouldn't be affecting that 'perf bench' entry:

  $ find tools/perf/ -type f | xargs grep SRBDS
  $

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Gross <mgross@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

tools/arch/x86/include/asm/cpufeatures.h

@@ -362,6 +362,7 @@
 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
 #define X86_FEATURE_FSRM		(18*32+ 4) /* Fast Short Rep Mov */
 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
+#define X86_FEATURE_SRBDS_CTRL		(18*32+ 9) /* "" SRBDS mitigation MSR available */
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
@@ -407,5 +408,6 @@
 #define X86_BUG_SWAPGS			X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
 #define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
 #define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
+#define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
 
 #endif /* _ASM_X86_CPUFEATURES_H */

tools/arch/x86/include/asm/msr-index.h

@@ -128,6 +128,10 @@
 #define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */
 #define TSX_CTRL_CPUID_CLEAR		BIT(1)	/* Disable TSX enumeration */
 
+/* SRBDS support */
+#define MSR_IA32_MCU_OPT_CTRL		0x00000123
+#define RNGDS_MITG_DIS			BIT(0)
+
 #define MSR_IA32_SYSENTER_CS		0x00000174
 #define MSR_IA32_SYSENTER_ESP		0x00000175
 #define MSR_IA32_SYSENTER_EIP		0x00000176