MIPS: malta: Incorporate PIIX4 ACPI I/O region in PCI controller resources

Boot log says:

pci 0000:00:0a.3: no compatible bridge window for [io  0x1000-0x103f]
pci 0000:00:0a.3: no compatible bridge window for [io  0x1100-0x110f]

The io resource starting point on Malta was modified by c5de50da (MIPS:
Malta: Change start address to avoid conflicts.) to avoid conflicts with
ACPI and SMB devices. In fact, that was not needed (and now causing
southbridge ACPI missing) since 166c6370 (PCI: add pci_create_root_bus()
that accepts resource list) and 7c090e5b (mips/PCI: convert to
pci_scan_root_bus() for correct root bus resources) had already done the
correct fix.

This patch actually reverts the change made by c5de50da. And with this
fix, log says:

pci 0000:00:0a.3: quirk: [io  0x1000-0x103f] claimed by PIIX4 ACPI
pci 0000:00:0a.3: quirk: [io  0x1100-0x110f] claimed by PIIX4 SMB

These things may not be used but as part of platform resources are better
off to be included.

Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6037/

arch/mips/pci/pci-malta.c

@@ -241,9 +241,9 @@ void __init mips_pcibios_init(void)
 		return;
 	}
 
-	/* Change start address to avoid conflicts with ACPI and SMB devices */
-	if (controller->io_resource->start < 0x00002000UL)
-		controller->io_resource->start = 0x00002000UL;
+	/* PIIX4 ACPI starts at 0x1000 */
+	if (controller->io_resource->start < 0x00001000UL)
+		controller->io_resource->start = 0x00001000UL;
 
 	iomem_resource.end &= 0xfffffffffULL;			/* 64 GB */
 	ioport_resource.end = controller->io_resource->end;